STMicroelectronics L7980A 2 a step-down switching regulator Datasheet

L7980
2 A step-down switching regulator
Features
■
2 A DC output current
■
4.5 V to 28 V input voltage
■
Output voltage adjustable from 0.6 V
■
250 kHz switching frequency, programmable
up to 1 MHz
■
Internal soft-start and enable
■
Low dropout operation: 100% duty cycle
■
Voltage feed-forward
■
Zero load current operation
■
Overcurrent and thermal protection
■
VFQFPN3x3-8L and HSOP8 package
HSOP8 exposed pad
Description
The L7980 is a step down switching regulator with
2.5 A (minimum) current limited embedded power
MOSFET, so it is able to deliver up to 2 A current
to the load depending on the application
conditions.
Applications
■
Consumer:
STB, DVD, DVD recorder, car audio, LCD TV
and monitors
■
Industrial:
PLD, PLA, FPGA, chargers
■
Networking: XDSL, modems, DC-DC modules
■
Computer:
Optical storage, Hard disk drive, Printers,
Audio/graphic cards
■
LED driving
Figure 1.
VFQFPN8 3x3
The input voltage can range from 4.5 V to 28 V,
while the output voltage can be set starting from
0.6 V to VIN.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
The QFN and the HSOP packages with exposed
pad allow reducing the RthJA down to 60 °C/W
and 40 °C/W respectively.
Application circuit
December 2010
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Contents
L7980
Contents
1
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
7
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5.1
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3
Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5
Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.1
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.2
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.6
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.7
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1
Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2
Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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L7980
Contents
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Pin settings
L7980
1
Pin settings
1.1
Pin connection
Figure 2.
Pin connection (top view)
OUT
SYNCH
GND
EN
FSW
COMP
1.2
FB
Pin description
Table 1.
4/44
VCC
Pin description
N.
Type
1
OUT
Description
Regulator output
2
SYNCH
Master/Slave Synchronization. When it is left floating, a signal with a
phase shift of half a period respect to the power turn on is present at the
pin. When connected to an external signal at a frequency higher than the
internal one, then the device is synchronized by the external signal, with
zero phase shift.
Connecting together the SYNCH pin of two devices, the one with higher
frequency works as master and the other one as slave; so the two
powers turn on have a phase shift of half a period.
3
EN
A logical signal (active high) enable the device. With EN higher than 1.2
V the device is ON and with EN is lower than 0.3V the device is OFF.
4
COMP
5
FB
6
FSW
The switching frequency can be increased connecting an external
resistor from FSW pin and ground. If this pin is left floating the device
works at its free-running frequency of 250kHz.
7
GND
Ground
8
VCC
Unregulated DC input voltage
Error amplifier output to be used for loop frequency compensation
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6V. To have higher regulated voltages an
external resistor divider is required from Vout to FB pin.
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L7980
2
Maximum ratings
Maximum ratings
Table 2.
Absolute maximum ratings
Symbol
3
Parameter
Vcc
Input voltage
OUT
Output DC voltage
Value
Unit
30
-0.3 to VCC
FSW, COMP, SYNCH
Analog pin
-0.3 to 4
EN
Enable pin
-0.3 to VCC
FB
Feedback voltage
-0.3 to 1.5
PTOT
Power dissipation
at TA < 60°C
VFQFPN
HSOP
1.5.
V
W
2
TJ
Junction temperature range
-40 to 150
°C
Tstg
Storage temperature range
-55 to 150
°C
Thermal data
Table 3.
Symbol
RthJA
Thermal data
Parameter
Maximum thermal resistance
junction-ambient (1)
Value
VFQFPN
60
HSOP
40
Unit
°C/W
1. Package mounted on demonstration board.
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Electrical characteristics
4
L7980
Electrical characteristics
TJ=25 °C, VCC=12 V, unless otherwise specified.
Table 4.
Electrical characteristics
Values
Symbol
Parameter
Test condition
Unit
Min
VCC
Operating input voltage
range
(1)
VCCON
Turn on VCC threshold
(1)
VCCHYS
VCC UVLO Hysteresis
(1)
RDSON
MOSFET on resistance
ILIM
4.5
Max
28
4.4
0.12
V
0.35
160
180
160
250
2.5
3.0
3.5
225
250
275
mΩ
(1)
Maximum limiting current
Typ
A
Oscillator
FSW
Switching frequency
VFSW
FSW pin voltage
D
FADJ
(1)
KHz
220
275
1.254
Duty Cycle
0
Adjustable switching
frequency
RFSW=33kΩ
V
100
1000
%
KHz
Dynamic characteristics
VFB
4.5V<VCC<28V (1)
Feedback voltage
0.593
0.6
0.607
V
2.4
mA
30
μA
DC characteristics
IQ
IQST-BY
Duty Cycle=0,
VFB=0.8V
Quiescent current
Total stand-by quiescent
current
20
Enable
Device OFF level
0.3
EN threshold voltage
V
Device ON level
EN current
1.2
EN=VCC
7.5
10
8.2
9.1
μA
Soft start
FSW pin floating
TSS
Soft start duration
FSW=1MHz,
RFSW=33kΩ
Error amplifier
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7.4
ms
2
L7980
Electrical characteristics
Table 4.
Electrical characteristics
Values
Symbol
Parameter
Test condition
Unit
Min
VCH
High level output voltage
VFB<0.6V
VCL
Low level output voltage
VFB>0.6V
IO SOURCE Source COMP pin
IO SINK
GV
Typ
Max
3
V
0.1
VFB=0.5V, VCOMP=1V
17
mA
Sink COMP pin
VFB=0.7V, VCOMP=1V
25
mA
Open loop voltage gain
(2)
100
dB
Synchronization function
High input voltage
2
3.3
V
Low input voltage
1
Slave sink current
VSYNCH=2.9V
Master output amplitude
ISOURCE=4.5mA
Output pulse width
SYNCH floating
0.7
2.0
0.9
mA
V
110
ns
Input pulse width
70
Protection
TSHDN
Thermal shutdown
150
Hysteresis
30
°C
1. Specification referred to TJ from -40 to +125°C. Specification in the -40 to +125°C temperature range are
assured by design, characterization and statistical correlation.
2. Guaranteed by design.
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Functional description
5
L7980
Functional description
The L7980 is based on a “voltage mode”, constant frequency control. The output voltage
VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing
an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of
the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
●
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed forward are implemented.
●
The soft start circuitry to limit inrush current during the start up phase.
●
The voltage mode error amplifier
●
The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch.
●
The high-side driver for embedded p-channel power MOSFET switch.
●
The peak current limit sensing block, to handle over load and short circuit conditions.
●
A voltage regulator and internal reference. It supplies internal circuitry and provides a
fixed internal reference.
●
A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
●
A thermal shutdown block, to prevent thermal run away.
Figure 3.
Block diagram
VCC
REGULATOR
TRIMMING
EN
&
BANDGAP
EN
1.254V
3.3V
0.6V
COMP
UVLO
PEAK
CURRENT
LIMIT
THERMAL
SOFTSTART
SHUTDOWN
E/A
PWM
DRIVER
S
Q
R
OUT
OSCILLATOR
FB
8/44
FSW
GND
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SYNCH
&
PHASE SHIFT
SYNCH
L7980
5.1
Functional description
Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a
constant frequency clock. Its frequency depends on the resistor externally connect to FSW
pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as
shown in Figure 6 by external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feed forward is implemented (Figure 5.b) in order to
keep the PWM gain constant versus the switching frequency (see Section 6.4 for PWM gain
expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with
higher oscillator frequency works as Master, so the Slave device switches at the frequency
of the Master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor [see L5988D data sheet].
Figure 4.
Oscillator circuit block diagram
Clock
FSW
Clock
Generator
Synchronization
SYNCH
Ramp
Generator
Sawtooth
The device can be synchronized to work at higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This changing has to be taken into account when the loop stability is studied.
To minimize the change of the PWM gain, the free running frequency should be set (with a
resistor on FSW pin) only slightly lower than the external clock frequency. This pre-adjusting
of the frequency will change the sawtooth slope in order to get negligible the truncation of
sawtooth, due to the external synchronization.
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Functional description
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L7980
Figure 5.
Sawtooth: voltage and frequency feed forward; external synchronization
Figure 6.
Oscillator frequency versus FSW pin resistor
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L7980
5.2
Functional description
Soft-start
The soft-start is essential to assure correct and safe start up of the step-down converter. It
avoids inrush current surge and makes the output voltage increases monothonically.
The soft -start is performed by a staircase ramp on the non-inverting input (VREF) of the
error amplifier. So the output voltage slew rate is:
Equation 1
SR OUT = SR VREF ⋅ ⎛ 1 + R1
--------⎞
⎝
R2⎠
where SRVREF is the slew rate of the non-inverting input, while R1and R2 is the resistor
divider to regulate the output voltage (see Figure 7). The soft-start stair case consists of 64
steps of 9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles.
So the soft start time and then the output voltage slew rate depend on the switching
frequency.
Figure 7.
Soft start scheme
Soft start time results:
Equation 2
⋅ 64
SS TIME = 32
----------------Fsw
For example with a switching frequency of 250 kHz the SSTIME is 8 ms.
5.3
Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
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Functional description
Table 5.
L7980
Uncompensated error amplifier characteristics
Low frequency gain
100dB
GBWP
4.5MHz
Slew rate
7V/μs
Output voltage swing
0 to 3.3V
Maximum source/sink current
17mA/25mA
In continuos conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter a type II compensation network can be used. Otherwise, a type
III compensation network has to be used (see Chapter 6.4 for details about the
compensation network selection).
Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe
phase margin.
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L7980
5.4
Functional description
Overcurrent protection
The L7980 implements the overcurrent protection sensing current flowing through the power
MOSFET. Due to the noise created by the switching activity of the power MOSFET, the
current sensing is disabled during the initial phase of the conduction time. This avoids an
erroneous detection of a fault condition. This interval is generally known as “masking time”
or “blanking time”. The masking time is about 200 ns.
When the overcurrent is detected, two different behaviors are possible depending on the
operating condition.
1.
Output voltage in regulation. When the overcurrent is sensed, the power MOSFET is
switched off and the internal reference (VREF), that biases the non-inverting input of the
error amplifier, is set to zero and kept in this condition for a soft start time (TSS, 2048
clock cycles). After this time, a new soft start phase takes place and the internal
reference begins ramping (see Figure 8.a).
2.
Soft start phase. If the overcurrent limit is reached the power MOSFET is turned off
implementing the pulse by pulse overcurrent protection. During the soft start phase,
under overcurrent condition, the device can skip pulses in order to keep the output
current constant and equal to the current limit. If at the end of the “masking time” the
current is higher than the overcurrent threshold, the power MOSFET is turned off and it
will skip one pulse. If, at the next switching on at the end of the “masking time” the
current is still higher than the threshold, the device will skip two pulses. This
mechanism is repeated and the device can skip up to seven pulses. While, if at the end
of the “masking time” the current is lower than the overcurrent threshold, the number of
skipped cycles is decreased of one unit. At the end of soft start phase the output
voltage is in regulation and if the overcurrent persists the behavior explained above
takes place. (see Figure 8.b)
So the overcurrent protection can be summarized as an “hiccup” intervention when the
output is in regulation and a constant current during the soft start phase. If the output is
shorted to ground when the output voltage is on regulation, the overcurrent is triggered and
the device starts cycling with a period of 2048 clock cycles between “hiccup” (power
MOSFET off and no current to the load) and “constant current” with very short on-time and
with reduced switching frequency (up to one eighth of normal switching frequency). See
Figure 32. for short circuit behavior.
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Functional description
Figure 8.
5.5
L7980
Overcurrent protection strategy
Enable function
The enable feature allows to put in stand-by mode the device.With EN pin lower than 0.3V
the device is disabled and the power consumption is reduced to less than 30 µA. With EN
pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull down
ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled.
The pin is also VCC compatible.
5.6
Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150°C. Once the junction temperature goes back to about 130°C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, so ensuring an accurate and fast temperature detection.
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L7980
Application informations
6
Application informations
6.1
Input capacitor selection
The capacitor connected to the input has to be capable to support the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have a RMS current rating higher than the maximum RMS input
current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 3
2
2
⋅ D- D
-------------I RMS = I O ⋅ D – 2
+ ------2
η
η
Where Io is the maximum DC output current, D is the duty cycle, η is the efficiency.
Considering η=1, this function has a maximum at D=0.5 and it is equal to Io/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 4
V OUT + V F
D MAX = -----------------------------------V INMIN – V SW
and
Equation 5
V OUT + V F
D MIN = ------------------------------------V INMAX – V SW
Where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across
the internal PDMOS.
The peak to peak voltage across the input capacitor can be calculated as:
Equation 6
IO
D
D
V PP = ------------------------- ⋅ ⎛⎝ 1 – ----⎞⎠ ⋅ D + ---- ⋅ ( 1 – D ) + ESR ⋅ I O
C IN ⋅ F SW
η
η
where ESR is the equivalent series resistance of the capacitor.
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Application informations
L7980
Given the physical dimension, ceramic capacitors can meet well the requirements of the
input filter sustaining an higher input RMS current than electrolytic / tantalum types. In this
case the equation of CIN as a function of the target VPP can be written as follows:
Equation 7
IO
D
C IN = --------------------------- ⋅ ⎛ 1 – D
----⎞ ⋅ D + ---- ⋅ ( 1 – D )
V PP ⋅ F SW ⎝
η
η⎠
neglecting the small ESR of ceramic capacitors.
Considering η=1, this function has its maximum in D=0.5, thus, given the maximum peak to
peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is:
Equation 8
IO
C IN_MIN = ----------------------------------------------2 ⋅ V PP_MAX ⋅ F SW
Typically CIN is dimensioned to keep the maximum peak-peak voltage in the order of 1% of
VINMAX
In Table 6. some multi layer ceramic capacitors suitable for this device are reported
Table 6.
Input MLCC capacitors
Manufacture
Series
Cap value (μF)
Rated voltage (V)
UMK325BJ106MM-T
10
50
GMK325BJ106MN-T
10
35
GRM32ER71H475K
4.7
50
Taiyo Yuden
Murata
A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that
additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability
on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to
1 µF.
6.2
Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple has to be selected.
The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current.
In the continuos current mode (CCM), the inductance value can be calculated by the
following equation:
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L7980
Application informations
Equation 9
V IN – V OUT
V OUT + V F
ΔI L = ------------------------------ ⋅ T ON = ---------------------------- ⋅ T OFF
L
L
Where TON is the conduction time of the internal high side switch and TOFF is the conduction
time of the external diode (in CCM, FSW=1/(TON + TOFF)). The maximum current ripple, at
fixed Vout, is obtained at maximum TOFF that is at minimum duty cycle (see previous section
to calculate minimum duty). So fixing ΔIL=20% to 30% of the maximum output current, the
minimum inductance value can be calculated:
Equation 10
V OUT + V F 1 – D MIN
L MIN = ---------------------------- ⋅ ----------------------ΔI MAX
F SW
where FSW is the switching frequency, 1/(TON + TOFF).
For example for VOUT=5 V, VIN=24 V, IO=2 A and FSW=250 kHz the minimum inductance
value to have ΔIL=30% of IO is about 28 μH.
The peak current through the inductor is given by:
Equation 11
ΔI
I L, PK = I O + -------L2
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In the table below some inductor part numbers are listed.
Table 7.
Inductors
Manufacturer
Coilcraft
Wurth
Series
Inductor value (μH)
Saturation current (A)
MSS1038
3.8 to 10
3.9 to 6.5
MSS1048
12 to 22
3.84 to 5.34
MSS1060
22 to 47
5 to 6.8
PD Type L
8.2 to 15
3.75 to 6.25
PD Type M
2.2 to 4.7
4 to 6
PD4 Type X
22 to 47
2.6 to 3.5
CDRH6D226/HP
1.5 to 3.3
3.6 to 5.2
CDR10D48MN
6.6 to 12
4.1 to 5.7
SUMIDA
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Application informations
6.3
L7980
Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge or discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor has to be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
Equation 12
ΔI MAX
ΔV OUT = ESR ⋅ ΔI MAX + -----------------------------------8 ⋅ C OUT ⋅ f SW
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Chapter 6.4, it will be illustrated how to consider its effect in the
system stability.
For example with VOUT=5 V, VIN=24 V, ΔIL=0.6 A (resulting by the inductor value), in order to
have a ΔVOUT=0.01·VOUT, if the multi layer ceramic capacitor are adopted, 10 µF are needed
and the ESR effect on the output voltage ripple can be neglected. In case of not negligible
ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its
ESR value. So in case of 220 with ESR=50 mΩ, the resistive component of the drop
dominates and the voltage ripple is 33 mV.
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application the output capacitor and system bandwidth
have to be chosen in order to sustain the load transient.
In the table below some capacitor series are listed.
Table 8.
Output capacitors
Manufacturer
Series
Cap value (μF)
Rated voltage (V)
ESR (mΩ)
GRM32
22 to 100
6.3 to 25
<5
GRM31
10 to 47
6.3 to 25
<5
ECJ
10 to 22
6.3
<5
EEFCD
10 to 68
6.3
15 to 55
SANYO
TPA/B/C
100 to 470
4 to 16
40 to 80
TDK
C3225
22 to 100
6.3
<5
MURATA
PANASONIC
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L7980
6.4
Application informations
Compensation network
The compensation network has to assure stability and good dynamic performance. The loop
of the L7980 is based on the voltage mode control. The error amplifier is a voltage
operational amplifier with high bandwidth. So selecting the compensation network the E/A
will be considered as ideal, that is, its bandwidth is much larger than the system one.
The transfer functions of PWM modulator and the output LC filter are studied (see Figure
10.). The transfer function of the PWM modulator, from the error amplifier output (COMP
pin) to the OUT pin, results:
Equation 13
V IN
G PW0 = -------Vs
where VS is the sawtooth amplitude. As seen in Chapter 5.1, the voltage feed forward
generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 14
V S = K ⋅ V IN
In this way the PWM modulator gain results constant and equals to:
Equation 15
V IN
1- = 13
- = --G PW0 = -------Vs
K
The synchronization of the device with an external clock provided trough SYNCH pin can
modifies the PWM modulator gain (see Chapter 5.1 to understand how this gain changes
and how to keep it constant in spite of the external synchronization).
Figure 9.
The error amplifier, the PWM modulation and the LC output filter
VCC
VS
VREF
FB
PWM
E/A
OUT
COMP
L
ESR
GPW0
GLC
COUT
The transfer function on the LC filter is given by:
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Application informations
L7980
Equation 16
s
1 + ------------------------2π ⋅ f zESR
G LC ( s ) = ------------------------------------------------------------------------2
s
s
1 + ---------------------------+ ⎛⎝ -------------------⎞⎠
2π ⋅ f LC
2π ⋅ Q ⋅ f LC
where:
Equation 17
1
f LC = -----------------------------------------------------------------------,
ESR
2π ⋅ L ⋅ C OUT ⋅ 1 + --------------R OUT
1
f zESR = ------------------------------------------2π ⋅ ESR ⋅ C OUT
Equation 18
R OUT ⋅ L ⋅ C OUT ⋅ ( R OUT + ESR )
Q = ------------------------------------------------------------------------------------------ ,
L + C OUT ⋅ R OUT ⋅ E SR
V OUT
R OUT = -------------I OUT
As seen in Chapter 5.3 two different kind of network can compensate the loop. In the two
following paragraph the guidelines to select the Type II and Type III compensation network
are illustrated.
6.4.1
Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III
compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low ESR
(<1mΩ), with very high frequency zero, so type III network is adopted to compensate the
loop.
In Figure 10 the type III compensation network is shown. This network introduces two zeros
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:
Equation 19
1
-,
f Z1 = ----------------------------------------------2π ⋅ C 3 ⋅ ( R 1 + R 3 )
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1
f Z2 = ----------------------------2π ⋅ R 4 ⋅ C 4
L7980
Application informations
Equation 20
f P0 = 0,
1
-,
f P1 = ----------------------------2π ⋅ R 3 ⋅ C 3
1
f P2 = ------------------------------------------C4 ⋅ C5
------------------2π ⋅ R 4 ⋅
C4 + C5
Figure 10. Type III compensation network
In Figure 11 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))
and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn.
Figure 11. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:
1.
Choose a value for R1, usually between 1 kΩ and 5 kΩ.
2.
Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
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Application informations
L7980
Equation 21
BW
R 4 = ---------- ⋅ K ⋅ R 1
f LC
where K is the feed forward constant and 1/K is equals to 9.
3.
Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC):
Equation 22
1
C 4 = --------------------------π ⋅ R 4 ⋅ f LC
4.
Calculate C5 by placing the second pole at four times the system bandwidth (BW):
Equation 23
C4
C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1
5.
Set also the first pole at four times the system bandwidth and also the second zero at
the output filter double pole:
Equation 24
R1
R 3 = --------------------------,
4
⋅
BW
----------------- – 1
f LC
1
C 3 = ---------------------------------------2π ⋅ R 3 ⋅ 4 ⋅ BW
The suggested maximum system bandwidth is equals to the switching frequency divided by
3.5 (FSW/3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz.
For example with VOUT=5 V, VIN=24 V, IO=2 A, L=27 μH, COUT=22 μF, ESR<1 mΩ, the type
III compensation network is:
R 1 = 4.99kΩ,
R 2 = 680Ω, R 3 = 150Ω, R 4 = 3.3kΩ,
C 3 = 4.7nF,
C 4 = 22nF,
C 5 = 220pF
In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about
54 kHz and the phase margin is 50°.
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Application informations
Figure 12. Open loop gain bode diagram with ceramic output capacitor
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Application informations
6.4.2
L7980
Type II compensation network
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency lower than the desired bandwidth (that is: 2π∗ESR∗COUT>1/BW), this zero helps
stabilize the loop. Electrolytic capacitors show not negligible ESR (>30 mΩ), so with this
kind of output capacitor the type II network combined with the zero of the ESR allows
stabilizing the loop.
In Figure 13 the type II network is shown.
Figure 13. Type II compensation network
The singularities of the network are:
1
-,
f Z1 = ----------------------------2π ⋅ R 4 ⋅ C 4
f P0 = 0,
1
f P1 = ------------------------------------------C4 ⋅ C5
2π ⋅ R 4 ⋅ -------------------C4 + C5
In Figure 14 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))
and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)) are drawn.
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Application informations
Figure 14. Open loop gain: module bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:
1.
Choose a value for R1, usually between 1 kΩ and 5 kΩ, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2.
Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 25
f ESR 2 BW V S
R 4 = ⎛ ------------⎞ ⋅ ------------ ⋅ --------- ⋅ R 1
⎝ f LC ⎠ f ESR V IN
Where fESR is the ESR zero:
Equation 26
1
f ESR = -------------------------------------------2π ⋅ ESR ⋅ C OUT
and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant.
3.
Calculate C4 by placing the zero one decade below the output filter double pole:
Equation 27
10
C 4 = -----------------------------2π ⋅ R 4 ⋅ f LC
4.
Then calculate C3 in order to place the second pole at four times the system bandwidth
(BW):
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Application informations
L7980
Equation 28
C4
C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1
For example with VOUT=5 V, VIN=24 V, IO=2 A, L=27 μH, COUT=330 μF, ESR=50 mΩ, the
type II compensation network is:
R 1 = 1.1kΩ,
R 2 = 150Ω,
R 4 = 6.8kΩ,
C 4 = 82nF,
C 5 = 82pF
In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about
24 kHz and the phase margin is 48°.
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Application informations
Figure 15. Open loop gain bode diagram with electrolytic/tantalum output capacitor
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Application informations
6.5
L7980
Thermal considerations
The thermal design is important to prevent the thermal shutdown of device if junction
temperature goes above 150 °C. The three different sources of losses within the device are:
a)
conduction losses due to the not negligible RDSon of the power switch; these are
equal to:
Equation 29
2
P ON = R DSON ⋅ ( I OUT ) ⋅ D
Where D is the duty cycle of the application and the maximum RDSon over temperature is
300 mΩ. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN,
but actually it is quite higher to compensate the losses of the regulator. So the conduction
losses increases compared with the ideal case.
b)
switching losses due to power MOSFET turn ON and OFF; these can be
calculated as:
Equation 30
( T RISE + T FALL )
P SW = V IN ⋅ I OUT ⋅ ------------------------------------------- ⋅ Fsw = V IN ⋅ I OUT ⋅ T SW ⋅ F SW
2
Where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS)
and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16.
TSW is the equivalent switching time. For this device the typical value for the equivalent
switching time is 30 ns.
c)
Quiescent current losses, calculated as:
Equation 31
P Q = V IN ⋅ I Q
where IQ is the quiescent current (IQ=2.4 mA).
The junction temperature TJ can be calculated as:
Equation 32
T J = T A + Rth JA ⋅ P TOT
Where TA is the ambient temperature and PTOT is the sum of the power losses just seen.
RthJA is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
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Application informations
of heat. The RthJA measured on the demonstration board described in the following
paragraph is about 60 °C/W for the VFQFPN package and about 40 °C/W for the HSOP
package.
Figure 16. Switching losses
6.6
Layout considerations
The PC board layout of switching DC/DC regulator is very important to minimize the noise
injected in high impedance nodes and interferences generated by the high switching current
loops.
In a step down converter the input loop (including the input capacitor, the power MOSFET
and the free wheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current are flowing through it. In order to minimize the EMI, this loop has to be
as short as possible.
The feedback pin (FB) connection to external resistor divider is a high impedance node, so
the interferences can be minimized placing the routing of feedback node as far as possible
from the high current paths. To reduce the pick up noise the resistor divider has to be placed
very close to the device.
To filter the high frequency noise, a small bypass capacitor (220 nF - 1 µF) can be added as
close as possible to the input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.
In Figure 17 a layout example is shown.
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L7980
Figure 17. Layout example
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6.7
Application informations
Application circuit
In Figure 18 the demonstration board application circuit is shown.
Figure 18. Demonstration board application circuit (rev 1.0)
Table 9.
Component list (rev 1.0)
Reference
Part number
Description
Manufacturer
C1
UMK325BJ106MM-T
10μF, 50V
Taiyo Yuden
C2
GRM32ER61E226KE15
22μF, 25V
Murata
C3
2.2nF, 50V
C4
22nF, 50V
C5
220pF, 50V
C6
470nF, 50V
R1
4.99kΩ, 1%, 0.1W 0603
R2
1.1kΩ, 1%, 0.1W 0603
R3
220Ω, 1%, 0.1W 0603
R4
2.2kΩ, 1%, 0.1W 0603
R5
100kΩ, 1%, 0.1W 0603
D1
STPS3L40
3A DC, 40V
STMicroelectronics
L1
MSS1038-103NL
10μH, 30%, 3.9A,
DCRMAX=35mΩ
Coilcraft
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Application informations
L7980
Figure 19. PCB layout: L7980 and L7980A (component side)
Figure 20. PCB layout: L7980 and L7980A (bottom side)
Figure 21. PCB layout: L7980 and L7980A (front side)
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Application informations
Figure 22. Junction temperature vs. output
current
Figure 23. Junction temperature vs. output
current
Figure 24. Junction temperature vs. output
current
Figure 25. Efficiency vs. output current
92
VIN =12V
VIN =18V
Eff [%]
87
VIN =24V
82
77
VOUT=5.0 V
fsw=250 kHz
72
0.0
0.5
1.0
1.5
2.0
Io [A]
Figure 26. Efficiency vs.output current
Figure 27. Efficiency vs. output current
95
85
90
V IN =5V
VIN =5V
80
VIN =12V
Eff [%]
Eff [%]
V IN =12V
75
85
80
70
VIN =24V
65
75
VIN =24V
60
VOUT=3.3 V
fsw=250 kHz
70
VOUT=1.8 V
fsw=250 kHz
55
50
65
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Io [A]
Io [A]
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Application informations
L7980
Figure 28. Load regulation
Figure 29. Line regulation
0.0
1.6
Vcc=5V
1.4
-0.1
Vcc=12V
1.2
Vcc=24V
ΔVFB /VFB [%]
Δ VFB /VFB [%]
-0.2
1
0.8
0.6
-0.3
-0.4
0.4
Io=1A
-0.5
0.2
0
0
0.5
1
1.5
2
Io [A]
Io=2A
-0.6
5
20
25
Figure 31. Soft start
VOUT
100mV/div
AC coupled
VOUT
500mV/div
IL
500mA/div
VIN=24V
VOUT=3.3V
COUT=47uF
L=10uH
FSW=520k
IL 500mA/div
VFB
200mV/div
Time base 1ms/div
Time base 100us/div
Figure 32. Short circuit behavior
OUT
10V/div
IL
500mA/div
OUTPUT
SHORTED
Time base 5ms/div
34/44
15
VCC [V]
Figure 30. Load transient: from 0.4 A to 2 A
VOUT
1V/div
10
Doc ID 15181 Rev 4
L7980
Application ideas
7
Application ideas
7.1
Positive buck-boost
The L7980 can implement the step up/down converter with a positive output voltage.
Figure 33. shows the schematic: one power MOSFET and one Schottky diode are added to
the standard buck topology to provide 12 V output voltage with input voltage from 4.5 V to 28
V.
Figure 33. Positive buck-boost regulator
The relationship between input and output voltage is:
Equation 33
D
V OUT = V IN ⋅ ------------1–D
So the duty cycle is:
Equation 34
V OUT
D = ----------------------------V OUT + V IN
The output voltage isn’t limited by the maximum operating voltage of the device (28 V),
because the output voltage is sense only through the resistor divider. The external power
MOSFET maximum drain to source voltage, must be higher than output voltage; the
maximum gate to source voltage must be higher than the input voltage (in Figure 33., if VIN
is higher than 16 V, the gate must be protected through zener diode and resistor)
The current flowing through the internal power MOSFET is transferred to the load only
during the OFF time, so according to the maximum DC switch current (2.0 A), the maximum
output current for the buck boost topology can be calculated from the following equation.
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Application ideas
L7980
Equation 35
I OUT
I SW = ------------- < 2 A
1–D
where ISW is the average current in the embedded power MOSFET in the on time.
To chose the right value of the inductor and to manage transient output current, that for short
time can exceed the maximum output current calculated by Equation 35, also the peak
current in the power MOSFET has to be calculated. The peak current, showed in Equation
36, must be lower than the minimum current limit (3.7 A)
Equation 36
I OUT
I SW,PK = ------------- ⋅ 1 + --r- < 2.5A
1–D
2
V OUT
2
r = ------------------------------------ ⋅ ( 1 – D )
I OUT ⋅ L ⋅ F SW
Where r is defined as the ratio between the inductor current ripple and the inductor DC
current:
So in the buck boost topology the maximum output current depends on the application
conditions (firstly input and output voltage, secondly switching frequency and inductor
value).
In Figure 34. the maximum output current for the above configuration is depicted varying the
input voltage from 4.5 V to 28 V.
The dashed line considers a more accurate estimation of the duty cycles given by Equation
37, where power losses across diodes, external power MOSFET, internal power MOSFET
are taken into account.
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Application ideas
Figure 34. Maximum output current according to max DC switch current (2.0 A):
VO=12 V
Equation 37
V OUT + 2 ⋅ V D
D = ------------------------------------------------------------------------------------------V IN – V SW – V SWE + V OUT + 2 ⋅ V D
where VD is the voltage drop across diodes, VSW and VSWE across the internal and external
power MOSFET.
7.2
Inverting buck-boost
The L7980 can implement the step up/down converter with a negative output voltage.
Figure 33. shows the schematic to regulate -5 V: no further external components are added
to the standard buck topology.
The relationship between input and output voltage is:
Equation 38
D
V OUT = – V IN ⋅ ------------1–D
So the duty cycle is:
Equation 39
V OUT
D = ----------------------------V OUT – V IN
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Application ideas
L7980
As in the positive one, in the inverting buck-boost the current flowing through the power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (2.0 A), the maximum output current can be calculated from the Equation
35, where the duty cycle is given by Equation 39.
Figure 35. Inverting buck-boost regulator
The GND pin of the device is connected to the output voltage so, given the output voltage,
input voltage range is limited by the maximum voltage the device can withstand across VCC
and GND (28 V). Thus if the output is -5 V the input voltage can range from 4.5 V to 23 V.
As in the positive buck-boost, the maximum output current according to application
conditions is shown in Figure 36. The dashed line considers a more accurate estimation of
the duty cycles given by Equation 40, where power losses across diodes and internal power
MOSFET are taken into account.
Equation 40
V OUT – V D
D = ---------------------------------------------------------------– V IN – V SW + V OUT – V D
Figure 36. Maximum output current according to max DC switch current (2.0 A):
VO=-5 V
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8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Doc ID 15181 Rev 4
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Package mechanical data
Table 10.
L7980
VFQFPN8 (3x3x1.08mm) mechanical data
mm
inch
Dim.
Min
Typ
Max
Min
Typ
Max
0.80
0.90
1.00
0.0315
0.0354
0.0394
A1
0.02
0.05
0.0008
0.0020
A2
0.70
0.0276
A3
0.20
0.0079
A
b
0.18
0.23
0.30
0.0071
0.0091
0.0118
D
2.95
3.00
3.05
0.1161
0.1181
0.1200
D2
2.23
2.38
2.48
0.0878
0.0937
0.0976
E
2.95
3.00
3.05
0.1161
0.1181
0.1200
E2
1.65
1.70
1.75
0.0649
0.0669
0.0689
e
L
0.50
0.35
0.40
ddd
0.0197
0.45
0.08
Figure 37. Package dimensions
40/44
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0.0137
0.0157
0.0177
0.0031
L7980
Package mechanical data
Table 11.
HSOP8 mechanical data
mm
inch
Dim
Min
Typ
A
Max
Min
Typ
1.70
Max
0.0669
A1
0.00
A2
1.25
b
0.31
0.51
0.0122
0.0201
c
0.17
0.25
0.0067
0.0098
D
4.80
4.90
5.00
0.1890
E
5.80
6.00
6.20
0.2283
0.2441
E1
3.80
3.90
4.00
0.1496
0.1575
e
0.15
0.00
0.0059
0.0492
0.1929
0.1969
1.27
h
0.25
0.50
0.0098
0.0197
L
0.40
1.27
0.0157
0.0500
k
0
8
0.3150
0.10
0.0039
ccc
Figure 38. Package dimensions
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Order codes
9
L7980
Order codes
Table 12.
42/44
Order codes
Order codes
Package
Packaging
L7980
VFQFPN8
Tube
L7980A
HSOP8
Tube
L7980TR
VFQFPN8
Tape and reel
L7980ATR
HSOP8
Tape and reel
Doc ID 15181 Rev 4
L7980
10
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
Changes
19-Nov-2008
1
Initial release.
12-Mar-2009
2
Content reworked to improve readability, no technical changes
01-Jul-2010
3
Added application information
13-Dec-2010
4
Updated: Section 6.5 on page 28
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L7980
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