19-4390; Rev 0; 2/09 TION KIT EVALUA BLE AVAILA DOCSIS 3.0 Upstream Amplifier Features ♦ +5V Supply Voltage ♦ Low Power: 1.25W at 31dB Gain, 64dBmV Output ♦ Ultra-Low 25mW Dissipation in Transmit-Disable Mode ♦ 63dB Gain Control Range in 1dB Steps ♦ -60dBc Harmonic Distortion at 64dBmV Output ♦ Small 5mm x 5mm Thin QFN Package ♦ Low Burst On/Off Transient ♦ 275MHz, 3dB Bandwidth Ordering Information PART TEMP RANGE PIN PACKAGE MAX3518ETP+ -40°C to +85°C 20 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Applications DOCSIS 3.0 Cable Modems VOIP Modems Set-Top Boxes Typical Application Circuit appears at end of data sheet. SPI is a trademark of Motorola, Inc. Pin Configuration/Functional Diagram GND 1 IN+ N.C. N.C. N.C. VCC N.C. 20 19 18 17 16 15 N.C. 2 14 OUT+ IN- 3 13 N.C. N.C.* 4 12 OUT- GND 5 11 N.C.* MAX3518 NOTE: N.C.* PINS MUST BE LEFT UNCONNECTED. SERIAL INTERFACE 6 7 8 9 10 SCLK SDA CS TXEN VCC ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX3518 General Description The MAX3518 is an integrated CATV upstream amplifier IC designed to meet the DOCSIS 3.0 requirements, while disspating only 1.25W. The amplifier covers a 5MHz to 85MHz input frequency range (275MHz, 3dB bandwidth), and is capable of transmitting four QPSK modulated carriers, each at +58dBmV, simultaneously within this range. Both input and output ports are differential, requiring that an external balun be used at the output port. The gain is controlled in 1dB steps over a 63dB range using a SPI™ 3-wire interface. The MAX3518 operates from a single +5V supply. Four power codes are provided to allow maximum supply current to be reduced as determined by distortion requirements. In addition, for each power code, supply current is automatically reduced as gain is reduced while maintaining distortion performance. For DOCSIS 3.0 applications, the MAX3518 draws 300mA at 33dB gain, dropping to 250mA at 31dB gain. The MAX3518 supply current drops to 5mA between bursts to minimize power dissipation in transmit-disable mode. Control logic levels are 3.3V CMOS. The MAX3518 is available in a 20-pin thin QFN package, and operates over the extended industrial temperature range (-40°C to +85°C). MAX3518 DOCSIS 3.0 Upstream Amplifier ABSOLUTE MAXIMUM RATINGS VCC to GND............................................................-0.3V to +5.5V IN+, IN-....................................................... -0.3V to (VCC + 0.3V) OUT+, OUT-................................................ -0.3V to (VCC + 3.6V) TXEN, SDA, SCLK, CS ..........................................-0.3V to +4.2V RF Input Power................................................................ +10dBm Continuous Power Dissipation (TA = +70°C) (Note 1) (derate 29mW/°C above TA = +70°C).......................2000mW Operating Temperature Range.......................... -40°C to +85°C Junction Temperature.......................................................+150°C Storage Temperature Range............................ -65°C to +165°C Lead Temperature (soldering, 10s)..................................+300°C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit as shown, VCC = 4.75V to 5.25V, VGND = 0, TXEN = high, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C.) (Note 2) PARAMETER Supply Voltage SYMBOL CONDITIONS VCC Supply Current Transmit Mode ICC Supply Current Transmit Disable Mode ICC Input High Voltage VINH MIN TYP 4.75 Gain code = 63, power code = 3 (33dB gain typ) 290 Gain code = 59, power code = 1 (29dB gain typ) 160 TXEN = low 5 2.0 MAX UNITS 5.25 V 315 mA 6.5 mA 3.6 V Input Low Voltage VINL 0.7 V Input High Current IBIASH 10 µA Input Low Current IBIASH -10 µA AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit as shown, VCC = 4.75V to 5.25V, VGND = 0, TXEN = high, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C.) (Note 2) PARAMETER Frequency Range Voltage Gain, ZIN = 200Ω, ZOUT = 75Ω, Power Code = 3 (Note 4) SYMBOL fIN (Note 3) AV CONDITIONS MIN 5 TYP MAX 85 Gain code = 63 32 33 34 Gain code = 53 22 23 24 Gain code = 43 12 13 14 Gain code = 33 2 3 4 Gain code = 23 -8 -7 -6 Gain code = 13 -18 -17 -16 Gain code = 03 -28 -27 -26 Voltage Gain Variation with Power Code, Any Gain Code Gain Rolloff Voltage gain = -28dB to +33dB, fIN = 5MHz to 85MHz Gain Step Size Voltage gain = -28dB to +33dB, fIN = 5MHz to 85MHz 0.7 UNITS MHz dB ±0.1 dB -0.3 dB 1.0 2 ________________________________________________________________________________________ 1.3 dB DOCSIS 3.0 Upstream Amplifier (Typical Application Circuit as shown, VCC = 4.75V to 5.25V, VGND = 0, TXEN = high, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C.) (Note 2) Transmit-Disable Mode Noise Any BW = 160kHz from 5MHz to 85MHz, TXEN = low, voltage gain = -27dB to +33dB (Note 5) Isolation in Transmit-Disable Mode TXEN = low Noise Figure NF 80 Transmit mode, voltage gain = +13dB to +33dB (Note 5) Noise Figure Slope Transmit mode, voltage gain = -27dB to +33dB Transmit-Disable/TransmitEnable Transient Duration Transmit-Disable/TransmitEnable Transient Step Size -66 dBmV dB 11 dB -1.0 dB/dB TXEN input rise/fall time < 0.1µs 2 µs Gain = 33dB 25 Gain = 4dB 1 50 mVP-P Balanced 200 W Input Return Loss 200Ω system 15 dB Output Return Loss 75Ω system (Note 5) 11 15 dB Output Return Loss in Transmit-Disable Mode 75Ω system, TXEN = low (Note 5) 11 15 dB Input Impedance ZIN 2nd Harmonic Distortion HD2 Input tone at 33dBmV, VOUT = +64dBmV, power code = 3 (Note 5) -70 -57 dBc 3rd Harmonic Distortion HD3 Input tone at 33dBmV, VOUT = +64dBmV, power code = 3 (Note 5) -60 -56 dBc Two-Tone 2nd-Order Distortion IM2 Input tones at 30dBmV, VOUT = +61dBmV/tone, power code = 3 (Note 5) -70 -57 dBc Two-Tone 3rd-Order Distortion IM3 Input tones at 30dBmV, VOUT = +61dBmV/tone, power code = 3 (Note 5) -60 -54 dBc Four input tones at 27dBmV, VOUT = +58dBmV/tone, power code = 3 -55 dBc Gain = 33dB 74 dBmV Four Tone Spurs Output 1dB Compression Point P1dB TIMING CHARACTERISTICS (Typical Application Circuit as shown, VCC = 4.75V to 5.25V, VGND = 0, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SEN to SCK Rise Set Time tSENS 20 ns SEN to SCK Rise Hold Time tSENH 10 ns SDA to SCK Setup Time tSDAS 20 ns SDA to SCK Hold Time tSDAH 10 ns SCK Pulse-Width High tSCLKH 50 ns SCK Pulse-Width Low tSCLKL Maximum CLK Frequency Note Note Note Note 2: 3: 4: 5: 50 10 ns MHz Min/max values are production tested at TA = +85°C. Production tested at 10MHz and 85MHz. Voltage gain does not include loss due to input and output transformers. Guaranteed by design and characterization. ________________________________________________________________________________________ 3 MAX3518 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (MAX3518 EV kit, VCC = +5V, VIN = 33dBmV, fIN = 42MHz, ZLOAD = 75Ω, TA = +25°C, power code = 3, unless otherwise noted.) 150 100 PC = 1 PC = 0 10 20 30 40 GAIN CODE 50 60 297 VCC = +4.75V -50 70 VOLTAGE GAIN vs. TEMPERATURE 33.0 VCC = +5.00V VCC = +4.75V MAX3518 toc03 4.6 4.5 4.3 100 -50 100 GC = 63 30 GC = 53 20 PC = 1 PC = 0 33.0 PC = 3 32.5 0 50 TEMPERATURE (°C) VOLTAGE GAIN vs. FREQUENCY 40 MAX3518 toc05 33.5 VCC = +5.25V 32.5 4.7 VOLTAGE GAIN vs. TEMPERATURE VOLTAGE GAIN (dB) VOLTAGE GAIN (dB) 33.5 0 50 TEMPERATURE (°C) 34.0 MAX3518 toc04 34.0 4.8 4.4 295 VOLTAGE GAIN (dB) 0 VCC = +5.00V 296 50 0 298 4.9 GC = 43 10 GC = 33 0 GC = 23 -10 GC = 13 -20 PC = 2 MAX3518 toc06 PC = 2 VCC = +5.25V 299 TXEN = LOW 5.0 SUPPLY CURRENT (mA) 250 5.1 MAX3518 toc02 300 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) PC = 3 200 301 MAX3518 toc01 350 300 TRANSMIT DISABLE CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. GAIN CODE GC = 3 -30 32.0 0 50 TEMPERATURE (°C) 32.0 100 -50 VOLTAGE GAIN vs. GAIN CODE 0 GAIN STEP SIZE vs. GAIN CODE 1.3 20 100 200 300 FREQUENCY (MHz) 400 500 NOISE FIGURE vs. GAIN CODE 30 MAX3518 toc08 30 -40 100 1.4 MAX3518 toc07 40 0 50 TEMPERATURE (°C) MAX3518 toc09 -50 25 10 0 -10 1.1 1.0 0.9 -20 0.8 -30 0.7 -40 0.6 0 10 20 30 40 GAIN CODE 50 60 70 NOISE FIGURE (dB) 1.2 GAIN STEP (dB) VOLTAGE GAIN (dB) MAX3518 DOCSIS 3.0 Upstream Amplifier 20 15 TA = +85°C 10 TA = +25°C 5 0 10 20 30 40 GAIN CODE 50 60 70 TA = -40°C 0 0 10 20 30 40 GAIN CODE 4 ________________________________________________________________________________________ 50 60 70 DOCSIS 3.0 Upstream Amplifier 3RD HARMONIC DISTORTION vs. INPUT FREQUENCY -70 -75 TA = +25°C -80 -85 TA = -40°C -90 -54 -56 -50 -60 -58 -60 TA = -40°C -64 -70 -75 -85 -66 -68 -95 -70 -100 10 20 30 40 50 60 70 80 90 100 INPUT FREQUENCY (MHz) IM3 vs. INPUT FREQUENCY (2f1 - f2) -54 TA = -40°C -56 -58 -60 -62 TA = +25°C -64 35 TA = +85°C -66 30 25 20 15 10 5 -68 0 -70 0 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (MHz) OUTPUT RETURN LOSS (dB) -10 TA = -40°C -15 TA = +85°C 0 30 40 GAIN CODE 50 0 MAX3518 toc15 -5 -20 20 60 70 OUTPUT RETURN LOSS vs. FREQUENCY (TRANSMIT DISABLE MODE) OUTPUT RETURN LOSS vs. FREQUENCY 0 10 MAX3518 toc16 IM3 (dBc) TXEN TRANSIENT vs. GAIN CODE TXEN TRANSIENT (mVP-P) POUT = +61dBmV/TONE, PDISS = 1.25W 1MHz TONE SPACING -52 10 20 30 40 50 60 70 80 90 100 FREQUENCY (MHz) 40 MAX3518 toc13 -50 0 MAX3518 toc14 0 TA = +25°C -90 TA = +25°C -95 10 20 30 40 50 60 70 80 90 100 FREQUENCY (MHz) TA = -40°C -80 -100 0 TA = +85°C -65 TA = +85°C -62 POUT = +61dBmV/TONE, PDISS = 1.25W 1MHz TONE SPACING -55 MAX3518 toc12 POUT = +64dBmV, PDISS = 1.25W -52 IM2 (dBc) TA = +85°C -65 OUTPUT RETURN LOSS (dB) 2ND HARMONIC DISTORTION (dBc) -60 -50 IM2 vs. INPUT FREQUENCY (f1 + f2) MAX3518 toc11 POUT = +64dBmV, PDISS = 1.25W -55 3RD HARMONIC DISTORTION (dBc) -50 MAX3518 toc10 2ND HARMONIC DISTORTION vs. INPUT FREQUENCY -5 -10 TA = -40°C -15 TA = +25°C 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) TA = +85°C -20 0 TA = +25°C 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) ________________________________________________________________________________________ 5 MAX3518 Typical Operating Characteristics (continued) (MAX3518 EV kit, VCC = +5V, VIN = 33dBmV, fIN = 42MHz, ZLOAD = 75Ω, TA = +25°C, power code = 3, unless otherwise noted.) MAX3518 DOCSIS 3.0 Upstream Amplifier Pin Description PIN 1, 5 NAME GND 2 IN+ Positive PGA Input 3 IN- Negative PGA Input 4, 11 N.C. No Connection. These pins must remain open. 6 SCLK Serial Interface Clock 7 SDA Serial Interface Data 8 CS TXEN Serial Interface Enable 9 FUNCTION Ground Transmit Enable. TXEN = high places the device in transmit mode. 10 VCC Supply Voltage for Serial Interface 12 OUT- Negative Output 13, 15, 16, 18, 19, 20 N.C. No Connection. Connect these pins to ground. 14 OUT+ 17 VCC — EP Positive Output Supply Voltage for Programmable-Gain Amplifier (PGA) Ground Table 1. Register Description REGISTER NAME DATA 8 BITS REGISTER ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 Power/Gain 0000 PC2 PC1 GC5 GC4 GC3 GC2 GC1 GC0 Initialize 0001 0 0 0 0 0 0 0 0 Detailed Description Programmable-Gain Amplifier The programmable-gain amplifier (PGA) provides 63dB of output level control in 1dB steps. The gain of the PGA is determined by a 6-bit gain code (GC5–GC0) programmed through the serial data interface (Tables 1 and 2). Specified performance is achieved when the input is driven differentially. Four power codes (PC1–PC0) allow the PGA to be used with reduced bias current when distortion performance can be relaxed. In addition, for each power code, bias current is automatically reduced with gain code for maximum efficiency. The PGA features a differential Class A output stage capable of driving four +58dBmV QPSK modulated signals, or a single +64dBmV QPSK modulated signal into a 75Ω load. This architecture provides superior even-order distortion performance but requires that a transformer be used to convert to a single-ended output. In transmit-disable mode, the output amplifiers are powered down, resulting in low output noise, while maintaining impedance match. 3-Wire Serial Interface (SPI) and Control Registers The MAX3518 includes two programmable registers for initializing the part and setting the gain and power consumption. The 4 MSBs are address bits; the 8 least significant bits (LSBs) are used for register data. Data is shifted MSB first. Note: The registers must be written 100µs after the device is powered up, and no earlier. Once a new set of register data is clocked in, the corresponding power code and/or gain code does not take effect until TXEN transitions from high to low. Applications Information Power Codes The MAX3518 is designed to meet the stringent linearity requirements of DOCSIS 3.0 using power code (PC) 3. For DOCSIS 2.0, PC = 1 is recommended, which results in substantial supply current reduction. The full range of gain codes can be used in any power code. The gain difference between power codes is typically less than 0.1dB. 6 ________________________________________________________________________________________ DOCSIS 3.0 Upstream Amplifier BIT LOCATION (0 = LSB) BIT NAME RECOMMENDED DEFAULT FUNCTION Sets the power code, which controls the bias current drawn by the device in transmit mode: 11 - PC = 3, maximum current draw PC[1:0] 7,6 GC[5:0] . . . 11 5,4,3,2,1,0 00 - PC = 0, minimum current draw (See the Typical Operating Characteristics.) Sets the gain code, which determines the voltage gain of the amplifier: 11 1111 - GC = 63, voltage gain = 33dB (typ). 11 1110 - GC = 62, voltage gain = 32dB (typ). . . . 11 1111 00 0011 - GC = 03, voltage gain = -27dB (typ). (See the AC Electrical Characteristics.) Table 3. Initialize Register BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT — 7,6,5,4,3,2,1,0 0000 0000 FUNCTION Must be programmed to 0000 0000 upon power-up for specified performance. tSENH tSENS CS SCLK tSDAS SDA A3 tSDAH A2 A1 A0 tSCLKH D7 D6 D5 tSCLKL D4 D3 D2 D1 D0 Figure 1. SPI 3-Wire Interface Timing Diagram Transmit Disable Mode Between bursts in a DOCSIS system, the MAX3518 should be put in transmit-disable mode by setting TXEN low. The output transient on the cable is kept well below the DOCSIS requirement during the TXEN transitions. If a gain or power change is required, new values of PC and GC should be clocked in during transmit operation (TXEN low). The new operating point of the MAX3518 is set when TXEN transitions low during the time between bursts. Output Transformer The MAX3518 output circuits are open-collector differential amplifiers. On-chip resistors across the collectors provide a nominal output impedance of 75Ω in transmit mode and transmit-disable mode. To match the output of the MAX3514/MAX3516 to a single-ended 75Ω load, a 1:1 transformer is required. This transformer must have adequate bandwidth to cover the intended application. Note that some RF transformers specify bandwidth with a 50Ω source on the primary and a matching ________________________________________________________________________________________ 7 MAX3518 Table 2. Reg 00 Gain Control MAX3518 DOCSIS 3.0 Upstream Amplifier resistance on the secondary winding. Operating in a 75Ω system tends to shift the low-frequency edge of the transformer bandwidth specification up by a factor of 1.5 due to primary inductance. Keep this in mind when specifying a transformer. Bias to the output stage is provided through the center tap on the transformer primary. This greatly diminishes the on/off transients present at the output when switching between transmit and transmit-disable modes. Commercially available transformers typically have adequate balance between half-windings to achieve substantial transient cancellation. Finally, keep in mind that transformer core inductance varies with temperature. Adequate primary inductance must be present to sustain broadband output capability as temperatures vary. Input Circuit To achieve rated performance, the inputs of the MAX3518 must be driven differentially with an appropriate input level. The differential input impedance is 200Ω. Most applications require an anti-alias filter preceding the device. The filter should be designed to match this 200Ω impedance. The MAX3518 has sufficient gain to produce an output level of 64dBmV QPSK when driven with a +33dBmV input signal. If an input level greater than +34dBmV is used, the 3rd-order distortion performance will degrade slightly. Layout Issues A well-designed printed circuit board (PCB) is an essential part of an RF circuit. For best performance, pay attention to power-supply layout issues as well as the output circuit layout. No Connect Pins Pins 4 and 11 must be left open, not connected to supply or ground or any other node in the circuit. Pins 13, 15, 16, 18, 19, and 20 should be connected to ground. Output Circuit Layout The differential implementation of the MAX3518 output has the benefit of significantly reducing even-order distortion, the most significant of which is 2nd-harmonic distortion. The degree of distortion cancellation depends on the amplitude and phase balance of the overall circuit. It is important to keep the trace lengths from the output pins equal. Power-Supply Layout For minimal coupling between different sections of the IC, the ideal power-supply layout is a star configuration. This configuration has a large-value decoupling capacitor at the central power-supply node. The power-supply traces branch out from this node, each going to a separate power-supply node in the circuit. At the end of each of these traces is a decoupling capacitor that provides a very low impedance at the frequency of interest. This arrangement provides local power-supply decoupling at each power-supply pin. The power-supply traces must be capable of carrying the maximum current without significant voltage drop. The output transformer center tap node, VCC_CT, must be connected to supply through a 3Ω resistor to reduce the supply voltage on OUT+ and OUT-. This resistor must be rated to dissipate 250mW at +85°C. Exposed Pad Thermal Considerations The exposed pad (EP) of the MAX3518’s 20-pin TQFN package provides a low thermal resistance path to the die. It is important that the PCB on which the MAX3518 is mounted be designed to conduct heat from this contact. In addition, the EP should be provided with a lowinductance path to electrical ground. It is recommended that the EP be soldered to a ground plane on the PCB, either directly or through an array of plated via holes. Chip Information PROCESS: SiGe BiCMOS 8 ________________________________________________________________________________________ DOCSIS 3.0 Upstream Amplifier VCC_RF GND IN+ + INPUT – N.C. N.C. N.C. 20 19 18 VCC N.C. 17 16 15 N.C. 1 MAX3518 OUT+ 2 14 3 13 N.C. 4 12 ANTI-ALIAS FILTER IN- N.C.* GND 1:1 VCC_CT OUTPUT OUT- SERIAL INTERFACE 5V 11 N.C.* 5 6 7 8 9 SCLK SDA CS TXEN VCC DIG 10 VCC_RF VCC VCC_DIG VCC_CT 3Ω NOTE: N.C.* PINS MUST BE LEFT UNCONNECTED. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 20 TQFN-EP T2055-5 21-140 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products 9 Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX3518 Typical Application Circuit