EMC EM78452AQ 8-bit microcontroller Datasheet

EM78452
8-Bit
Microcontroller
Product
Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
October 2007
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are trademarks of ELAN Microelectronics Corporation.
Copyright © 2007 by ELAN Microelectronics Corporation
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Printed in Taiwan
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Elan Microelectronics
Shenzhen, Ltd.
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Contents
Contents
1
2
3
4
5
General Description .................................................................................................. 1
Features ..................................................................................................................... 1
Pin Assignment ......................................................................................................... 2
Pin Description.......................................................................................................... 3
Function Description ................................................................................................ 4
5.1
Operational Registers......................................................................................... 4
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10
5.1.11
5.1.12
5.1.13
5.1.14
5.1.15
5.2
R0 (Indirect Address Register) ............................................................................4
R1 (TCC) .............................................................................................................4
R2 (Program Counter) & Stack ...........................................................................4
R3 (Status Register) ............................................................................................6
R4 (RAM Select Register)...................................................................................6
R5~R8 (Port 5 ~ Port 8) ......................................................................................6
R9 (Port9)............................................................................................................7
RA (SPIRB: SPI Read Buffer) .............................................................................8
RB (SPIWB: SPI Write Buffer).............................................................................8
RC (SPIS: SPI Status Register) ..........................................................................8
RD (SPIC: SPI Control Register) ........................................................................9
RE (TMR1: Timer 1 Register)..............................................................................9
RF (PWP: Pulse Width Preset Register)...........................................................10
R20~R3E (General-purpose Register)..............................................................10
R3F (Interrupt Status Register) .........................................................................10
Special Purpose Registers ............................................................................... 11
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
A (Accumulator).................................................................................................11
CONT (Control Register)...................................................................................11
IOC5 ~ IOC9 (I/O Port Control Register) ..........................................................11
IOCC (T1CON: Timer 1 Control Register).........................................................11
IOCD (Pull-high Control Register).....................................................................12
IOCE (WDT Control Register) ...........................................................................12
IOCF (Interrupt Mask Register).........................................................................13
5.3
TCC/WDT Presacler......................................................................................... 15
5.4
I/O Ports ........................................................................................................... 15
5.5
Serial Peripheral Interface Mode...................................................................... 17
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
Overview & Features.........................................................................................17
SPI Function Description...................................................................................19
SPI Signal & Pin Description.............................................................................21
Programmed the Related Registers..................................................................22
SPI Mode Timing ...............................................................................................25
Software Application of SPI ...............................................................................26
Product Specification (V1.0) 10.18.2007
• iii
Contents
5.6
Timer 1 ............................................................................................................. 30
5.6.1
5.6.2
5.6.3
5.7
Overview ...........................................................................................................30
Function Description..........................................................................................30
Programming the Related Registers .................................................................31
Reset and Wake-up.......................................................................................... 32
5.7.1
The Status of RST, T, and P of STATUS Register .............................................37
5.8
Interrupt ............................................................................................................ 38
5.9
Oscillator .......................................................................................................... 39
5.9.1
5.9.2
Oscillator Modes................................................................................................39
Crystal Oscillator/Ceramic Resonators (Crystal)...............................................39
5.10 Code Option Register :..................................................................................... 40
5.11 Instruction Set .................................................................................................. 41
6
7
5.12 Timing Diagrams .............................................................................................. 44
Absolute Maximum Rating ..................................................................................... 45
Electrical Characteristics ....................................................................................... 45
7.1
8
DC Characteristic ............................................................................................. 45
7.2 AC Characteristic ............................................................................................. 46
Application Circuit .................................................................................................. 47
APPENDIX
A
B
Package Type: ......................................................................................................... 48
Package Information............................................................................................... 48
B.1 40-Lead Plastic Dual in line (PDIP) — 600 mil ................................................. 48
B.2
44-Lead Quad Flat Package (QFP)................................................................. 49
Specification Revision History
Doc. Version
1.0
iv •
Revision Description
Initial released version
Date
2007/10/18
Product Specification (V1.0) 10.18.2007
EM78452
8-Bit Microcontroller
1
General Description
The EM78452 is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS
technology. It has 4K×13-bit on-chip ROM and 140×8-bit on-chip general purpose registers. Its operational
kernel is implemented with RISC-like architecture and it is available in mask ROM version. The one time
programmable (OTP) version is flexible, in both mass production and engineering test stages. OTP
provides users with unlimited volume along with favorable price opportunities. This device is equipped with
Serial Peripheral Interface (SPI) function, and it is suitable for wired communication.
There are 58
easy-to-learn instructions and the user’s program can be emulated with the EMC In-Circuit Emulator (ICE).
2
Features
„
CPU configuration
•
•
•
•
„
„
Serial Peripheral Interface (SPI)
„
Four available interrupts:
•
•
•
•
Low power consumption:
•
•
„
4K×13 bits on-chip ROM
140×8 bits on chip general purpose registers
11 special function registers
5-level stacks for subroutine nesting
Less than 3 mA at 5V/4MHz
Typically 10 μA during sleep mode
„
Peripheral configuration
•
8-bit real time clock/counter (TCC) with overflow
interrupt
•
Power down mode
•
I/O ports have Programmable wake-up function
from sleep mode
I/O port configuration
•
•
•
•
•
5 bidirectional I/O ports (35 I/O pins)
12 Wake-up pins
32 programmable pull-high input pins
2 open-drain I/O pins
2 R-option pins
External interrupt (/INT)
SPI transmission completed interrupt
TCC overflow interrupt
Timer 1 overflow interrupt
„
2 ~ 4 machine clocks for each instruction cycle
„
3 LED Direct sinking pins with internal serial resistors
„
Built-in power-on reset
„
Operating voltage range: 1.8V ~ 5.5V
„
Operating temperature range: 0°C ~70°C
„
Operating frequency range (base on two clocks):
„
Programmable free running on-chip watchdog timer
•
„
Package Type:
Crystal mode:
DC ~ 20MHz @ 5V
DC ~ 16MHz @ 2.2V
DC ~ 4MHz @ 1.8V
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
•
•
•
40-pin DIP 600mil
40-pin SOP 450mil
44-pin QFP
:
:
:
EM78452P
EM78452WM
EM78452AQ
•1
EM78452
8-Bit Microcontroller
P67
P 9 3 /S D O
8
33
P66
P 9 4 /S C K
9
32
P65
31
P64
30
P63
10
P50
11
P51
P52
12
13
29
28
33
34
32
31
30
29
28
14
27
P60
15
26
P87
16
25
P86
P56
17
24
P85
23
22
P86
P85
36
20
P84
NC
37
19
P83
VDD
38
18
P82
R-OSCI
39
OSCO
EM 78452AQ
17
NC
40
16
P81
Vss
41
15
P80
/INT
42
14
P57
DATA
43
13
P56
CLK
44
P55
P57
18
23
P84
1
P80
19
22
P83
P81
20
21
P82
Fig. 3-1a 40-pin DIP EM78452P
24
NC
P90
P55
25
35
P61
P54
26
NC
P62
P53
27
21
2
3
P92/SDI
P 9 5 //S S
P70//RESET
P87
34
4
5
6
7
8
9
10
12
11
P54
7
P60
P72
P 9 2 /S D I
P61
P71
P53
36
35
P52
5
6
EM78452P
P90
P 9 1 /S R D Y
P63
P 7 0 //R E S E T
P62
37
P51
4
P50
VDD
CLK
P64
38
P65
39
P95//SS
2
3
P94/SCK
R -O S C I
/IN T
DATA
P66
OSCO
P67
40
P93/SDO
1
P72
Vss
P71
Pin Assignment
P91/SRDY
3
Fig. 3-1b 44-pin QFP EM78452AQ
Fig. 3-1 Pin Assignment
2•
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
4
Pin Description
Symbol
Pin No.
Type
Function Description
P50~P57
11~18
I/O
8-bit bidirectional general-purpose I/O port. All of its pins can be
pulled-high individually by software.
P60~P67
27~34
I/O
8-bit bidirectional general-purpose I/O port. All of its pins can be
pulled-high by software, and pin-change wake-up pins.
P70~P72
37~35
I/O
LED direct-driving pins with internal serial resistor used as
output and is software defined.
P80~P87
19~26
I/O
8-bit bidirectional general-purpose I/O port. All of its pins can be
pulled-high by software. P80 and P81 are also used as R-option
pins.
P90~P95
5~10
I/O
6-bit bidirectional general-purpose I/O port. All of its pins can be
pulled-high by software. P90 and P91 are pin-change wake-up
pins.
LED direct-driving pin with internal serial resistor used as output
and is software defined.
P70/
RESET
Code option Bit 3 (REN): reset enable
37
I/O
REN=0 → for reset pin
REN=1 → for general purpose I/O (P70)
Internal pull high resistor 220KΩ
R-OSCI
39
I
Crystal input
OSCO
40
O
Crystal output
I/O
By connecting P74 and P76 together, P74 can be pulled-high
by software and it is also a pin-change wake-up pin.
CLK
4
P76 can be defined as an open-drain output.
DATA
3
I/O
By connecting P75 and P77 together, P75 can be pulled-high
by software and it is also a pin-change wake-up pin.
P77 can be defined as an open-drain output.
VDD
38
−
Power supply pin
VSS
1
−
Ground pin
Interrupt Schmitt trigger pin.
/INT
2
I
The interrupt function is triggerred at a falling edge.
Users can enable it by software.
SRDY
6
I/O
Slave Ready pin for SPI
SDI
7
I/O
Serial data in for SPI
SDO
8
I/O
Serial data out for SPI
SCK
9
I/O
Serial clock for SPI
/SS
10
I/O
/Slave select for SPI
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
•3
EM78452
8-Bit Microcontroller
5
Function Description
WDT Timer
WDT
Time-out
STACK 1
PC
STACK 2
Prescaler
STACK 3
Oscillator/
Timming
Control
/ INT
STACK 4
ROM
STACK 5
Interrupt
Control
R1(TCC)
Sleep
&
Wake Up
Control
Instruction
Register
ALU
Instruction
Decoder
RAM
R3
ACC
TMR1
R4
DATA & CONTROL BUS
IOC5
R5
IOC6
R6
PPPPPPPP
55555555
01234567
PPPPPPPP
66666666
01234567
IOC7
R7
P
7
0
P
7
1
IOC9
R9
IOC8
R8
P
7
2
PP PP
9 9 9 9
0 1 2 3
/ / /
S SS
R DD
D I O
Y
PPPPPPPP
88888888
01234567
P
9
4
/
S
C
K
SPI
ENGIN
P
5
5
/
/
S
S
Fig. 5-1 Functional Block Diagram
5.1 Operational Registers
5.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as register actually accesses data pointed by the
RAM Select Register (R4).
5.1.2 R1 (TCC)
„
R1 is incremented by the instruction cycle clock.
„
It is written and read by the program as any other register.
5.1.3 R2 (Program Counter) & Stack
„
R2 and the hardware stacks are 12 bits wide.
„
The structure is depicted in Fig. 5-2.
„
„
4•
Generates 4K × 13 on-chip ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
All the R2 bits are set to "1"s as a reset condition occurs.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
„
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows it to jump to any location on one page.
„
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page
„
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
at the top of the stack.
„
"MOV R2, A" allows the loading of an address from the "A" register to the lower 8
bits of PC, and the ninth and tenth bits (A8~A9) of the PC are cleared.
„
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and tenth bits of the PC are cleared.
„
Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",⋅⋅⋅⋅⋅)
(except "TBL") will cause the ninth and tenth bits (A8~A9) of the PC to be cleared.
Thus, the computed jump is limited to the first 256 locations of any program page.
„
"TBL" allows a relative address to be added to the current PC (R2+A→R2), and
contents of the ninth and tenth bits (A8~A9) of the PC are not changed. Thus, the
computed jump can be on the second (or third, 4th) 256th locations on one
program page.
„
In the case of EM78452, the most significant bits (A10~A11) will be loaded with the
contents of bits PS0~PS1 in the status register (R3) upon the execution of a "JMP",
"CALL", or any other instructions which writes to R2.
„
All instructions are single instruction cycle (fclk/2 or fclk/4 except for instructions
that would change the contents of R2. Such instruction will need one more
instruction cycle.
R3
A11 A10 A9 A8
A7
~
A0
00 PAGE0 0000~03FF
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
11 PAGE3 0C00~0FFF
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
000H
001H
002H
On-chip Program
Memory
Reset Vector
User Memory Space
CALL
RET
RETL
RETI
Hardware Vector
Software Vector
FFFH
Fig. 5-2 Program Counter Organization
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
•5
EM78452
8-Bit Microcontroller
5.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
PS1
PS0
T
P
Z
DC
C
Bit 7 (GP): General read/write bit.
Bits 6 ~ 5 (PS1 ~ PS0): Page select bits. PS0~PS1 are used to pre-select a program
memory page. When executing a "JMP", "CALL", or other instructions which
causes the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are
loaded into the 11th and 12th bits of the program counter where it selects
one of the available program memory pages. Note that RET (RETL, RETI)
instruction does not change the PS0~PS1 bits. For this reason, the return
will always be to the page from where the subroutine was called, regardless
of the current settings of PS0~PS1 bits. PS1 bit is not used (read as "0") and
cannot be modified in EM78452.
PS1
PS0
Program Memory Page [Address]
0
0
1
1
0
1
0
1
Page 0 [000-3FF]
Page 1 [400-7FF]
Page 2 [800-BFF]
Page 3 [C00-FFF]
Bit 4 (T): Time-out bit. Set to “1” with the "SLEP" and the "WDTC" commands, or
during power up and reset to “0” with the WDT timeout.
Bit 3 (P): Power down bit. Set to “1” during power on or by a "WDTC" command and
reset to “0” by a "SLEP" command.
Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
5.1.5 R4 (RAM Select Register)
Bits 7~6: determines which bank is activated among the 4 banks.
Bits 5~0: are used to select the registers (Address: 00~3F) in the indirect addressing
mode.
If indirect addressing is not used, the RSR is used as an 8-bit general-purpose
read/writer register.
See the data memory configuration in Fig. 5-3.
5.1.6 R5~R8 (Port 5 ~ Port 8)
Four general 8 bits I/O registers
6•
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Both P74 and P76 reads or writes data from the DATA pin, while both P75 and P77
reads or writes data from the CLK pin.
5.1.7 R9 (Port9)
The general 6-bit I/O register. The values of the two most significant bits are read as "0".
Address
R PAGE registers
IOC PAGE registers
00
R0
(Indirect Addressing Register)
01
R1
(Time Clock Counter)
02
R2
(Program Counter)
Reserve
03
R3
(Status Register)
Reserve
04
R4
(RAM Select Register)
Reserve
05
R5
(Port5)
IOC5 (I/O Port Control Register)
06
R6
(Port6)
IOC6 (I/O Port Control Register)
07
R7
(Port7)
IOC7 (I/O Port Control Register)
08
R8
(Port8)
IOC8 (I/O Port Control Register)
09
R9
(Port9)
IOC9 (I/O Port Control Register)
0A
RA
(SPI read buffer)
Reserve
0B
RB
(SPI write buffer)
Reserve
0C
RC
(SPI status buffer)
IOCC (Timer1 Control Register)
0D
RD
(SPI control buffer)
IOCD (Pull_high Control Register)
0E
RE
(Timer1 register)
IOCE (WDT Control Register)
0F
Reserve
10
︰
1F
General Registers
20
:
3E
Bank0
3F
R3F
Bank1
Reserve
CONT (Control Register)
IOCF (Interrupt Mask Register)
Bank2
Bank3
(Interrupt Status Register)
Fig. 5-3 Data Memory Configuration
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
•7
EM78452
8-Bit Microcontroller
5.1.8 RA (SPIRB: SPI Read Buffer)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0X0A
SPIRB/RA
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB7~SRB0 are the 8-bit data when transmission is completed by SPI.
5.1.9 RB (SPIWB: SPI Write Buffer)
Address
0x0B
Name
Bit 7
SPIWB/RB SWB7
Bit 6
Bit 5
Bit 4
Bit 3
SWB6
SWB5
SWB4
Bit 2
Bit 1
Bit 0
SWB3 SWB2 SWB1 SWB0
SWB7~SWB0 are the 8-bit data that are waiting for transmission by SPI.
5.1.10 RC (SPIS: SPI Status Register)
Address Name
0x0C
Bit 7
SPIS/RC DORD
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TD1
TD0
TM1IF
OD3
OD4
Bit 1
Bit 0
RBF
Bit 7 (DORD): Data transmission order.
0 : Shift left (MSB first)
1 : Shift right (LSB first)
Bit 6~Bit 5: SDO Status output Delay times Options
TD1
TD0
Delay Time
0
0
1
1
0
1
0
1
8 CLK
16 CLK
24 CLK
32 CLK
Bit 4 (T1ROS): Timer 1 Read Out Buffer Select Bit
0 : Read Value from Timer 1 Preset Register
1 : Read Value from Timer 1 Counter Register
Bit 3 (OD3):
Open-Drain Control bit
0 : Open-drain disable for SDO
1 : Open-drain enable for SDO
Bit 2 (OD4):
Open-Drain Control bit
0 : Open-drain disable for SCK
1 : Open-drain enable for SCK
Bit 1:
not used, read as “0”
Bit 0 (RBF): Read Buffer Full flag
0 : Receiving not completed, and SPIRB has not fully exchanged.
1 : Receiving completed; SPIRB is fully exchanged.
8•
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
5.1.11 RD (SPIC: SPI Control Register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
0x0D
SPIC/RD
CES
SPIE
SRO
SSE
Bit 3
Bit 2
Bit 1
Bit 0
SDOC SBRS2 SBRS1 SBRS0
Bit 7 (CES): Clock Edge Select bit
0 : Data shifts out on a rising edge, and shifts in on a falling edge. Data is
on hold during low-level.
1 : Data shifts out on a falling edge, and shifts in on a rising edge. Data is
on hold during high-level.
Bit 6 (SPIE): SPI Enable bit
0 : Disable SPI mode
1 : Enable SPI mode
Bit 5 (SRO): SPI Read Overflow bit
0 = No overflow
1 = A new data is received while the previous data is still being held in the
SPIB register. In this situation, the data in the SPIS register will be
destroyed. To avoid setting this bit, users are required to read the
SPIRB register although only the transmission is implemented.
Note that this can only occur in slave mode.
Bit 4 (SSE): SPI Shift Enable bit
0 = Reset as soon as shifting is completed, and the next byte is ready to
be shifted.
1 = Start to shift, and keep at “1” while the current byte is still being
transmitted.
It should be noted that this bit will be reset to 0 at every 1-byte
transmission by the hardware.
Bit 3 (SDOC): SDO output status control bit:
0 : After the Serial data output, the SDO remains high.
1 : After the Serial data output, the SDO remains low.
Bit 2~Bit 0 (SBRS): SPI Baud Rate Select bits
Refer to the SPI baud rate table illustration under the section “SPI” on the
subsequent pages.
5.1.12 RE (TMR1: Timer 1 Register)
Address
0X0E
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1/RE TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10
TMR17~TMR10 are the set of bits of Timer 1 register and such are incremented until
the value matches PWP and then it resets to 0.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
•9
EM78452
8-Bit Microcontroller
5.1.13 RF (PWP: Pulse Width Preset Register)
Address Name
0x0F
Bit 7
PWP/RF PWP7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWP6
PWP5
PWP4
PWP3
PWP2
PWP1
PWP0
PWP7~PWP0 are the set of bits with pulse width preset in advance for the desired
width of the baud clock.
5.1.14 R20~R3E (General-purpose Register)
RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
5.1.15 R3F (Interrupt Status Register)
Address Name
0x3F
ISR/R3F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
TM1IF
SPIIF
EXIF
TCIF
Bits 7~4: not used, read as “0”.
Bit 3 (TM1IF): Timer 1 interrupt flag. Set by the comparator at Timer 1 application, flag
is cleared by software.
Bit 2 (SPIIF): SPI interrupt flag. Set during data transmission completed, flag is
cleared by software.
Bit 1 (EXIF): External interrupt flag. Set by a falling edge on the /INT pin, flag is cleared
by software
Bit 0 (TCIF): TCC overflow interrupt flag. Set as TCC overflows; flag is cleared by
software.
0 : means no interrupt occurs
1 : means with interrupt request
R3F can be cleared by instruction, but cannot be set by instruction.
IOCF is the interrupt mask register.
Note that when reading R3F it will result to "logic AND" of R3F and IOCF.
10 •
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
5.2 Special Purpose Registers
5.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
5.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PHEN
/INT
-
-
PAB
PSR2
PSR1
PSR0
Bit 7 (/PHEN) I/O pin pull-high enable flag.
0: For P60~P67, P74~P75 and P90~P95, the pull-high function is enabled.
1: The pull-high function is disabled.
Bit 6 (INT) An interrupt enable flag cannot be written to by the CONTW instruction.
0: interrupt masked by the DISI instruction.
1: interrupt enabled by the ENI or RETI instruction.
Bits 5 and 4: Not used, read as “0”.
Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC/WDT prescaler bits.
Bits 0~3, and 7 of the CONT register are readable and writable.
5.2.3 IOC5 ~ IOC9 (I/O Port Control Register)
0: puts the relative I/O pin as output
1: puts the relative I/O pin into high impedance
„
Both P74 and P76 should not be defined as output pins at the same time. This also
applies to both P75 and P77.
„
Only the lower 6 bits of the IOC9 register are used.
5.2.4 IOCC (T1CON: Timer 1 Control Register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0x0C
T1CON/IOCC
0
0
0
0
0
TM1E
Bit 1
Bit 0
TM1P1 TM1P0
Bit 2 (TM1E): Timer 1 Function Enable bit
0 : Disable Timer 1 function as default
1 : Enable Timer 1 function
Bit 1~Bit 0 (TM1P): Timer 1 Prescaler bit
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 11
EM78452
8-Bit Microcontroller
Refer to the Timer 1 prescaler table for FOSC illustration under the section “Timer 1” on
the subsequent pages.
5.2.5 IOCD (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S7
-
-
-
/PU9
/PU8
/PU6
/PU5
„
The default values of /PU5, /PU6, /PU8, and /PU9 are “1”, which means that the
pull-high function is disabled.
„
/PU6 and /PU9 are “AND” gating with /PHEN, that is, when each one is written with
a “0”, pull high is enabled.
„
S7 defines the driving ability of the P70-P72.
0: Normal output
1: Enhances the driving ability of the LED
5.2.6 IOCE (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
ODE
WDTE
SLPC
ROC
-
-
/WUE
Bits 7, and 1~2 are not used.
Bit 6 (ODE) Open-drain control bit.
0 : Both P76 and P77 are normally I/O pins.
1 : Both P76 and P77 pins have the open-drain function inside.
The ODE bit can be read and written to.
Bit 5 (WDTE) Control bit used to enable the Watchdog timer.
The WDTE bit can be used only if ENWDT, the Code Option bit, is "1." If the
ENWDT bit is "1," then WDT can be disabled / enabled by the WDTE bit.
0: Disable WDT
1: Enable WDT
The WDTE bit is not used if ENWDT, the Code Option bit ENWD is "0".
That is, if the ENWDT bit is "0", WDT is always disabled no matter what the
WDTE bit is.
The WDTE bit can be read and written to.
Bit 4 (SLPC) This bit is set by hardware at a falling edge of the wake-up signal and is
cleared by software. The SLPC is used to control the oscillator operation.
The oscillator is disabled (oscillator stops, and the controller enters the
Sleep 2 mode) on the high-to-low transition and is enabled (the controller
is awakened from Sleep 2 mode) on a low-to-high transition.
12 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
In order to ensure a stable output of the oscillator, once the oscillator is
enabled again, there is a delay of approximately 18 ms (oscillator start-up
timer (OST)) before the next program instruction is executed. The OST is
always activated by wake-up from sleep mode whether the Code Option
bit ENWDT is "0" or not. After waking up, the WDT is enabled if the Code
Option ENWDT is "1". The block diagram of Sleep 2 mode and wake-up
caused by the input trigger is depicted in Fig. 5-4. The SLPC bit can be
read and written to.
Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of
the R-option pins (P80, P81) to be read by the controller. Clearing ROC
will disable the R-option function. Otherwise, the R-option function is
introduced. Users must connect the P81 pin and/or P80 pin to VSS by a
560KΩ external resistor (Rex). If Rex is connected/disconnected with
VDD, the status of P80 (P81) will be read as "0"/"1" (refer to Fig. 7(b)). The
ROC bit can be read and written to.
Bit 0 (/WUE) This control bit is used to enable the wake-up function of P60~P67,
P74~P75, and P90~P91.
0 : Enable the wake-up function
1 : Disable the wake-up function
The /WUE bit can be read and written to.
5.2.7 IOCF (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
TM1IE
SPIIE
EXIE
TCIE
Bits 4~7 Not used.
Individual interrupt is enabled by setting its associated control bit in IOCF to "1".
The IOCF Register could be read and written to.
Bit 3 (TM1IE) TM1IE interrupt enable bit.
0 : disable TM1IE interrupt
1 : enable TM1IE interrupt
Bit 2 (SPIIE) SPI interrupt enable bit.
0 : disable SPI interrupt
1 : enable SPI interrupt
Bit 1 (EXIE) EXIF interrupt enable bit.
0 : disable EXIF interrupt
1 : enable EXIF interrupt
Bit 0 (TCIE) TCIF interrupt enable bit.
0 : disable TCIF interrupt
1: enable TCIF interrupt
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 13
EM78452
8-Bit Microcontroller
/W U E
O s c illa to r
E n a b le
D is a b le
/W U E
R eset
Q
Q
C le a r
P
D
R
CLK
C
L
VCC
Set
8
/W U E
fr o m S /W
P60~P67
VCC
/W U E
/P H E N
4
P74~P75, P90~P91
Fig. 5-4 Block Diagram of Sleep Mode and Wake-up Circuits on the I/O Ports
14 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
5.3 TCC/WDT Presacler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is
available for either the TCC or WDT at any given time, and the PAB bit of CONT
register is used to determine the prescaler assignment. The PSR0~PSR2 bits
determine the prescaler ratio. The prescaler is cleared each time the instruction is
written to TCC in TCC mode. The WDT and prescaler, when assigned to WDT mode,
are cleared by the WDTC or SLEP instructions. Fig. 5-5 depicts the circuit diagram of
TCC/WDT.
„
R1 (TCC) is an 8-bit timer/counter. TCC will increase by one at every instruction
cycle (without prescaler).
„
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep
running even when the oscillator driver has been turned off (i.e. in sleep mode).
During normal or sleep mode operation, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming (if Code Option bit ENWDT is "1"). Refer to the
WDTE bit of the IOCE register. Without presacler, the WDT time-out period is
approximately 18 ms 1.
5.4 I/O Ports
The I/O registers, from Port 5 to Port 9, are bidirectional tri-state I/O ports. P60~P67,
P74~P75, and P90~P91 provides internal pull-high. P60~P67, P74~P75, and
P90~P95 provides programmable wake-up function through software. P76~P77 can
have an open-drain output by software control. P80~P81 are the R-option pins which
are enabled by software. When the R-option function is used, it is recommended that
P80 and P81 be used as output pins. During R-option enabled state, P80 and P81
must be programmed as input pins. If an external resistor is connected to P80 (P81) for
the R-option function, the current consumption should be taken as an important factor
in the applications for low power consideration.
The I/O ports can be defined as "input" or "output" pins by the I/O control registers
(IOC5~IOC9) under program control. The I/O registers and I/O control registers are
both readable and writable. The I/O interface circuit is shown in Fig. 5-6. Note that the
reading path source of input and output pins is different when reading the I/O port.
1
Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 18.0ms ± 30%
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 15
EM78452
8-Bit Microcontroller
Data Bus
CLK(=Fosc/2)
1
M
U
X
SYNC
2 cycles
TCC(R1)
0
TCC overflow interrupt
PAB
0
WDT
M
U
X
1
8-bit Counter
PSR0~PSR2
8 - to -1 MUX
0
WDTE
(in IOCE)
1
PAB
MUX
WDT timeout
Fig. 5-5 Block Diagram of TCC WDT
PCRD
P D
R
CLK
Q C
L
Q
P
R D
C CLK
Q L
PORT
PCWR
IOD
Q
0
1
M
U
X
PDWR
PDRD
Fig. 5-6 (a) I/O Port and I/O Control Register Circuit
16 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
PCRD
VCC
ROC
Q
W eakly
Pull-up
Q
PORT
Q
Q
0
Rex*
1
P
D
R
CLK
C
L
P
D
R
C CLK
L
M
U
X
PCWR
IOD
PDWR
PDRD
*The Rex is 560K ohm external resistor
Fig. 4-6(b) The Circuit of I/O Port with R-option (P80, P81)
5.5 Serial Peripheral Interface Mode
5.5.1 Overview & Features
Overview:
Figures 4-7, 4-8, and 4-9 shows how the EM78452 communicates with other devices
through SPI module. If EM78452 is a master controller, it sends clock through the SCK
pin. A couple of 8-bit data are transmitted and received at the same time. However, if
EM78452 is defined as a slave, its SCK pin could be programmed as an input pin. Data
will continue to be shifted based on both the clock rate and the selected edge. In Slave
mode when code option bit 7 (SPIHSK) is set to 0, the P91 (HSK) pin will be set to high
after SPI enable and SSE bit set to 1. You can also set SPIS bit 7(DORD) to decide the
SPI transmission order, SPIC bit3 (SDOC) to control SDO pin after serial data output
status and SPIS bit 6 (TD1), bit 5 (TD0) decides the SDO status output delay times.
Those three functions mentioned can work however; it must be based on code option
bit5 (SDOS) set to 0.
Features:
„
Operation in either Master mode or Slave mode
„
Three-wire or four-wire synchronous communication; that is, full duplex
„
Programmable baud rates of communication
„
Programming clock polarity, (RD bit7)
„
Interrupt flag available for the read buffer full
„
SPI transmission order
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 17
EM78452
8-Bit Microcontroller
„
After serial data output SDO status select
„
SDO status output delay times
„
SPI handshake pin
„
Up to 8 MHz (maximum) bit frequency
SDO
SPIW
SPIW Reg
Reg
SPIR Reg
SPIR Reg
SPIW
SPIW Reg
Reg
/SS
SPIS Reg
SDI
SPI Module
Bit 7
Master Device
SCK
Slave Device
Fig. 5-7 SPI Master/Slave Communication
SDI
SDO
SCK
/SS
Vdd
Master
P50
P51
P52
P53
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
Slave Device 1
Slave Device 2
Slave Device 3
Slave Device 4
Fig. 5-8 SPI Configuration of Single-Master and Multi-Slave
18 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
SDI
SDO
SCK
/SS
Master 1
or
Slave 1
SDI
SDO
SCK
/SS
Master 2
or
P50
Slave
6
P51
P52
P53
P50
P51
P52
P53
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
Slave 3 for Master 1
or Master 2
Slave 2 for Master 1
Slave 4 for Master 1
or Master 2
Slave 5 for Master 2
Fig. 5-9 SPI Configuration of Single-Master and Multi-Slave
5.5.2 SPI Function Description
R ead
RBF
RBFI
W rite
S P IR
SE
re g
S P IW
re g
S e t to 1
B u ffe r F u ll D e te c to r
S P IS
P 9 2 /S D I
s h ift rig h t
re g
b it 0
b it 7
S P IC re g
P 9 3 /S D O
Edge
S e le c t
SB R 0 ~SB R 2
P 9 5 / /S S
/ SS
T sco
SB R 2~SB R 0
8
N o is e
F ilte r
C lo c k S e le c t
2
P re sc a ler
4, 8 , 1 6 , 3 2 , 64
Edge
S e le c t
P 9 4 /S C K
T M R 1 /2
S P IC b it6
Fig. 5-10 SPI Block Diagram
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 19
EM78452
8-Bit Microcontroller
SPI
SPI Read Register
(0X0A)
7~0
SPIWB
/SS
SPI Write Register
(0X0B)
8-1 MUX
SPI Mode Select
Register
2 1 0
SPIC
SDO
SDI
Shift Clock
SPI Shift Buffer
FOSC
1 0
7 6 4 1 0
T1CON
SPIC SPIS
2
4
INTC
SPIC
7~0
SPIRB
DATA BUS
Fig. 5-11 The Function Block Diagram of SPI Transmission
Below are the functions of each block and explanations on how to carry out the SPI
communication with the signals depicted in Fig.4-10 and Fig.4-11:
20 •
„
P91/SRDY : Slave Ready pin
„
P92/SDI : Serial Data In
„
P93/SDO : Serial Data Out
„
P94/SCK : Serial Clock
„
P95//SS:/Slave Select (Option). This pin (/SS) may be required during slave mode.
„
RBF : Set by Buffer Full Detector, and reset by software.
„
Buffer Full Detector : Set to 1 when an 8-bit shifting is completed.
„
SSE : Loads the data in SPIS register, and begin to shift
„
SPIS reg. : Shifting byte in and out. The MSB is shifted first. Both the SPIS and
the SPIW registers are loaded at the same time. Once data are written, SPIS starts
transmission / reception. The data received will be moved to the SPIR register as
the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the
RBFI (Read Buffer Full Interrupt) flag are then set.
„
SPIR reg. : Read buffer. The buffer will be updated as the 8-bit shifting is
completed. The data must be read before the next reception is completed. The
RBF flag is cleared as the SPIR register reads.
„
SPIW reg. : Write buffer. The buffer will deny any attempts to write until the 8-bit
shifting is completed.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
The SSE bit will be kept in “1“ if the communication is still undergoing. This flag must
be cleared as the shifting is completed. Users can determine if the next write attempt is
available.
„
SBRS2~SBRS0: Programming the clock frequency/rates and sources.
„
Clock Select:Selects either the internal or the external clock as the shifting clock.
„
Edge Select: Selects the appropriate clock edges by programming the CES bit
5.5.3 SPI Signal & Pin Description
The detailed functions of the four pins, SDI, SDO, SCK, and /SS, which are shown in
Fig. 5-8.
SRDY/P92 (Pin 6):
„
Slave ready pin
„
In Slave mode when code option bit 7 (SPIHSK) set to 0, P91 (SRDY) this pin will
be set to high after SPI enable and SSE bit set to 1.
SDI/P92 (Pin 7):
„
Serial Data In,
„
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last,
„
Defined as high-impedance, if not selected,
„
Program the same clock rate and clock edge to latch on both the master and slave
devices,
„
The byte received will update the transmitted byte,
„
Both the RBF and RBFIF bits (located in Register 0x0C) will be set as the SPI
operation is completed.
„
Timing is shown in Fig. 5-12 and 5-13.
SDO/P93 (Pin 8):
„
Serial Data Out,
„
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last,
„
Program the same clock rate and clock edge to latch on both the master and slave
devices,
„
The received byte will update the transmitted byte,
„
The CES (located in Register 0x0D) bit will be reset, as the SPI operation is
completed.
„
Timing is shown in Fig. 5-12 and 5-13.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 21
EM78452
8-Bit Microcontroller
SCK/P94 (Pin 9):
„
Serial Clock
„
Generated by a master device
„
Synchronize the data communication on both the SDI and SDO pins
„
The CES (located in Register 0x0D) is used to select the edge to communicate.
„
The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of
communication
„
The CES, SBR0, SBR1, and SBR2 bits have no effect in slave mode
„
Timing is shown in Fig. 5-12 and Fig. 5-13
/SS/P95 (Pin 10):
„
Slave Select; negative logic
„
Generated by a master device to signify the slave(s) to receive data
„
Goes low before the first cycle of SCK appears, and remains low until the last
(eighth) cycle is completed
„
Ignores the data on the SDI and SDO pins while /SS is high, because the SDO is
no longer driven.
„
Timing is shown in Fig. 5-12 and Fig. 5-13.
5.5.4 Programmed the Related Registers
As the SPI mode is defined, the related registers of this operation are shown in Table 2
and Table 3.
Table 1 Related Control Registers in SPI Mode
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0D
*SPIC/RD
CES
SPIE
SRO
SSE
SDOC
SBR2
SBR1
SBR0
0x0F
INTC/IOCF
--
--
--
--
TM1IE
SPIIE
EXIE
TCIE
SPIC: SPI Control Register.
Bit 7 (CES): Clock Edge Select bit
0 : Data shifts out on rising edge, and shifts in on falling edge. Data is on
hold during the low level.
1 : Data shifts out on falling edge, and shifts in on rising edge. Data is on
hold during the high level.
22 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Bit 6 (SPIE): SPI Enable bit
0 : Disable SPI mode
1 : Enable SPI mode
Bit 5 (SRO): SPI Read Overflow bit
0 : No overflow.
1 : A new data is received while the previous data is still being on hold in
the SPIB register. Under this condition, the data in the SPIS register
will be destroyed. To avoid setting this bit, users should read the
SPIRB register even if the transmission is implemented only.
Note that this can only occur in slave mode.
Bit 4 (SSE): SPI Shift Enable bit
0 : Reset as soon as the shifting is completed and the next byte is ready
to shift.
1 : Start to shift, and stays on 1 while the current byte continues to
transmit.
Note that this bit can be reset by hardware only.
Bit 3 (SDOC): SDO output status control bit:
1 : After Serial data output SDO keep low.
0 : After Serial data output SDO keep High
Bits 2~0 (S BRS): SPI Baud Rate Select Bits
SBRS2 (Bit 2)
SBRS1 (Bit 1)
SBRS0 (Bit 0)
Mode
Baud Rate
0
0
0
Master
Fosc/2
0
0
1
Master
Fosc/4
0
1
0
Master
Fosc/8
0
1
1
Master
Fosc/16
1
0
0
Master
Fosc/32
1
0
1
Slave
/SS enable
1
1
0
Slave
/SS disable
1
1
1
Master
TMR1/2
Note: In Mater mode, the /SS pin is disabled.
INTC: Interrupt control register
Bit 3 (TM1IE) TM1IE interrupt enable bit.
0 : disable TM1IE interrupt
1 : enable TM1IE interrupt
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 23
EM78452
8-Bit Microcontroller
Bit 2 (SPIIE) SPI interrupt enable bit.
0 : disable SPI interrupt
1 : enable SPI interrupt
Bit 1 (EXIE) EXIF interrupt enable bit.
0 : disable EXIF interrupt
1 : enable EXIF interrupt
Bit 0 (TCIE) TCIF interrupt enable bit.
0 : disable TCIF interrupt
1 : enable TCIF interrupt
Table 2 Related Status/Data Registers of the SPI Mode
Address
0X0A
0x0B
0x0C
Name
Bit 7
SPIRB/RA SRB7
SPIWB/RB SWB7
SPIS/RC DORD
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SRB6
SWB6
TD1
SRB5
SWB5
TD0
SRB4
SWB4
TM1IF
SRB3
SWB3
OD3
SRB2
SWB2
OD4
Bit 0
SRB1 SRB0
SWB1 SWB0
RBF
SPIRB:
SPI Read Buffer. Once the serial data is received completely, it will be
loaded to SPIRB from SPISR. The RBF bit and the RBFIF bit in the SPIS
register will also be set.
SPIWB:
SPI Write Buffer. As transmitted data is loaded, the SPIS register stands
by and start to shift the data when sensing SCK edge with SSE set to
“1”.
SPIS: SPI Status register
Bit 7 (DORD): Read Buffer Full Interrupt flag
0 : Shift left (MSB first)
1 : Shift right (LSB first)
Bit 6~Bit 5: SDO Status Output Delay Times Options
24 •
TD1
TD0
Delay Time
0
0
8 CLK
0
1
16 CLK
1
0
24 CLK
1
1
32 CLK
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
T1ROS (Bit 4): Timer 1 Read Outbuffer Select Bit
0 : Read Value from Timer 1 Preset Register
1 : Read Value from Timer 1 Counter Register
Bit 4 (TM1IF): Timer 1 interrupt flag
Bit 3 (OD3) Open-Drain Control bit (P93)
0 : Open-drain disable for SDO
1 : Open-drain enable for SDO
Bit 2 (OD4): Open Drain-Control bit (P94)
0 : Open-drain disable for SCK
1 : Open-drain enable for SCK
Bit 0 (RBF): Read Buffer Full flag
0 = Receive is ongoing, SPIB is empty.
1 = Receive is completed, SPIB is full.
5.5.5 SPI Mode Timing
The edge of SCK is selected by programming bit CES. The waveform shown in Fig.
5-12 is applicable regardless whether the EM78452 is in master or slave mode with /SS
disabled. However, the waveform in Fig. 5-13 can only be implemented in slave mode
with /SS enabled.
Fig. 5-12 SPI Mode with /SS Disabled
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 25
EM78452
8-Bit Microcontroller
Fig. 4-13 SPI Mode with /SS Enable
5.5.6 Software Application of SPI
Example for SPI:
For Master
ORG 0X0
Setting:
CLRA
IOW 0X05
IOW 0X06
MOV 0X05,A
MOV A,@0B11001111
CONTW
MOV A,@0B00010001
IOW 0X0E
MOV A,@0B00000000
IOW 0X0F
MOV A,@0x07
IOW 0x09
MOV A,@0B10000000
MOV 0x0C,A
MOV A,@0B11100000
MOV 0X0D,A
26 •
; Set Port 5 output
; Set Port 6 output
; Set prescaler for WDT
; Disable wake-up function
; Disable interrupt
; SDI input and SDO, SCK output
; Clear RBF and RBFIF flag
; Select clock edge and enable SPI
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Start:
WDTC
BC 0X0C,1
MOV A,@0XFF
MOV 0X05,A
MOV 0X0A,A
MOV A,@0XAA
MOV 0X0B,A
BS 0X0D,4
NOP
JMP SETTING
JMP $-2
BC 0X03,2
CALL DELAY
MOV A,0X0A
XOR A,@0X5A
JBS 0X03,2
JMP START
FLAG:
MOV A,@0X55
MOV 0X05,A
CALL DELAY
JMP START
DELAY:
; Clear RBFIF flag
; Show a signal at Port 5
; Move FF at read buffer
; Move AA at write buffer
; Start to shift SPI data
; Polling loop for checking SPI
; transmission completed
; To catch the data from slaver
; Compare the data from slaver
; Show the signal when receiving
; correct data from slaver
; (user’s program)
EOP
ORG 0XFFF
JBC 0X0D,4
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 27
EM78452
8-Bit Microcontroller
For Slaver
ORG 0X0
INITI:
JMP INIT
ORG 0X2
INTERRUPT:
MOV A,@0X55
MOV 0X06,A
MOV A,@0B11100110
MOV 0X0D,A
BS 0X0D,4
MOV A,@0X00
MOV 0X0B,A
BS 0X0D,4
NOP
JBC 0X0D,4
JMP $-2
BS 0X0D,4
BC
MOV
MOV
XOR
JBS
JMP
JMP
28 •
0X03,2
A,0X0A
0X06,A
A,@0XAA
0X03,2
SPI
$-6
; Interrupt address
; Show a signal at Port 6 when entering
; interrupt
; Enable SPI, /SS disabled
; Keep SSE at 1 to wait for SCK signal in
order to shift data
; Move 00 to write buffer in order to keep
; master’s read buffer as 00
; Keep SSE at 1 to wait for SCK signal in
; order to shift data
; Polling loop for checking SPI
; transmission completed
; Keep SSE at 1 to wait for SCK signal in
; order to shift data
; Read master’s data from read buffer
; Check pass signal from read buffer
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
ORG 0X30
INIT:
CLRA
IOW 0X05
IOW 0X06
MOV 0x05,A
MOV 0X06,A
MOV A,@0XFF
IOW 0X08
MOV A,@0B11001111
CONTW
MOV A,@0B00010001
IOW 0X0E
MOV A,@0B00000010
IOW 0XF
ENI
MOV A,@0B00110111
IOW 0x09
BC 0X3F,1
NOP
JBS 0X3F,1
JMP $-2
JMP INTERRUPT
SPI:
BS 0X0D,4
WDTC
MOV A,@0X0F
MOV 0X06,A
JBC 0X08,1
JMP SPI
MOV A,@0X5A
MOV 0X0B,A
NOP
JBC 0X0D,4
JMP $-2
BS 0XD,4
NOP
NOP
MOV A,@0XF0
; Set prescaler for WDT
; Disable wakeup function
; Enable external interrupt
; Clear RBFIF flag
; Polling loop for checking interrupt
; occurrences
; Keep SSE enabled as long as possible
; Show a signal when entering SPI loop
; Choose P81 as a signal button
; Move 5A into write buffer when P81 button
; is pushed
; Polling loop for checking SPI
; transmission completed
; Display at Port6 when P81 button is pushed
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 29
EM78452
8-Bit Microcontroller
MOV 0X06,A
MOV A,@0X00
; Send a signal to master to prevent
; infinite loop
MOV 0X0B,A
NOP
JBC 0X0D,4
JMP $-2
BS 0X0D,4
JMP INITI
BC 0x0C,1
NOP
JMP SPI
DELAY:
; (user’s program)
EOP
ORG 0XFFF
BS 0x0C,7
5.6 Timer 1
5.6.1 Overview
Timer 1 (TMR1) is an 8-bit clock counter with programmable prescaler. The TMR1 is in
SPI baud rate clock generator mode (SBRS0, SBRS1and SBRS2 a1l set to 1) and then
SPI control register Bit 4 (SSE) is set to “1”. Timer 1 will be enabled automatically
without setting TM1E. TMR1 can be read and written to, and cleared on any reset
conditions.
5.6.2 Function Description
Fig. 5-14 shows Timer 1 block diagram. Each signal and block is described as follows:
Set predict value
TM1E
0
TMR1 value
1
Set TM1IF
TMR1
up Counter
In SPI baud
generator mode ?
Yes
Interrupt
and
SPI clock output
Overflow
T1ROS
Prescaler
1:1~1:16
No
Interrupt
OSC / 4
Fig. 5-14 Timer 1 Block Diagram
30 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
„
OSC/4: Input clock.
„
Prescaler: Option of 1:1, 1:4, 1:8, and 1:16 defined by T1P1 and T1P2 (T1CON<1, 0>). It
is cleared when a value is written to TMR1 or T1CON, and during any kind of reset as well.
„
TMR1: Timer 1 register. TMR1 increases until it overflows, and then resets to 0. If
it is in the SPI baud rate generator mode, its output is fed as a shifting clock. TMR1
register; increases until it overflows, and then reloads the predicted value. If a
value is written to Timer 1, the predicted value and TMR1 value will be the set
value. However, If TRIOS is set to “1” and value is read from TMR1, the value will
be TMR1 direct value. Or else, TRIOS is set to “0” and the value is read from
TMR1, the value will be TMR1 predicted value.
5.6.3 Programming the Related Registers
The related registers of the defining TMR1 operation are shown in Table 4 and Table 5
Table 3 Related Control Registers of the TMR1
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0C
SPIS/RC
DORD
TD1
TD0
T1ROS
OD3
OD4
-
RBF
0x0F
INTC/IOCF
0
0
0
0
TM1IE
SPIIE
EXIE
TCIE
Bit 3
Bit 2
Bit 1
Bit 0
Table 4 Related Status/Data Registers ofTMR1
Address
0X0E
0x0C
„
Name
Bit 7
Bit 6
Bit 5
Bit 4
TMR1/RE TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10
T1CON/IOCC
0
0
0
0
0
TM1E TM1P1 TM1P0
TMR1: Timer 1 Register
TMR17~TMR10 are bit set of Timer1 register and it increases until the value
matches PWP and then it resets to 0.
„
T1ROS (Bit 3): Timer Read Buffer Select Bit
0: Read Value from Timer 1 Preset Register
1: Read Value from Timer 1 Counter Register.
„
T1CON: Timer 1 Control Register
Bit 2 (TM1E): Timer1 enable bit
Bit 1 (TM1P1) and Bit 0 (TM1P): Timer 1 prescaler for FSCO
TM1P1
TM1P0
Prescaler Rate
0
0
1:1
0
1
1:4
1
0
1:8
1
1
1:16
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 31
EM78452
8-Bit Microcontroller
5.7 Reset and Wake-up
A reset is initiated by
(1) Power-on reset, or
(2) /RESET pin input “low”, or
(3) WDT timeout. (if enabled)
VDD
D
Q
CLK
CLR
Oscillator
CLK
Poweron Reset
Voltage
Detector
WDTE
Setup
Time
WDT timeout
WDT
Reset
Fig. 5-15 Block Diagram of Reset
The EM78452 POR voltage range is between 1.2V~2.0V. Under customer application,
when power is OFF, the Vdd must drop below 1.2V and remains OFF for 10μs before
power can be switched ON again. This way, the EM78452 will reset and work normally.
The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or
less). However, in most cases where critical applications are involved, extra devices
are required to assist in solving the power-up problem.
The device is kept in a RESET condition for a period of approx. 18ms 2 (one oscillator
start-up timer period) after the reset is detected and Fig. 5-15 is the block diagram of
reset. Once the RESET occurs, the following functions are performed.
„
The oscillator is running, or will be started.
„
The Program Counter (R2) is set to all "1".
„
When power is switched on, Bits 5~6 of R3 and the upper 2 bits of R4 are cleared.
„
All I/O port pins are configured as input mode (high-impedance state).
„
The Watchdog timer and prescaler are cleared.
2
32 •
Vdd = 5V, set up time period = 16.20ms ± 30%
Vdd = 3V, set up time period = 18.0ms ±30%
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
„
The Watchdog timer is enabled if the Code Option bit ENWDT is "1".
„
The CONT register is set to all "1" except for Bit 6 (INT flag).
„
Bits 3 and 6 of the IOCE register are cleared, Bits 0, 4~5 of the IOCE register are
set to "1".
„
Bit 0 of R3F and Bit 0 of the IOCF registers are cleared.
The sleep mode (power down) is achieved by executing the SLEP instruction (named
as Sleep 1 MODE). While entering sleep mode, the WDT (if enabled) is cleared but
keeps on running. The controller is awakened by WDT timeout (if enabled), and it will
cause the controller to reset. The T and P flags of R3 are used to determine the source
of the reset (wake-up).
In addition to the basic Sleep 1 Mode, the EM78452 has another sleep mode (caused
by clearing "SLPC" bit of IOCE register, designated as Sleep 2 Mode). In the Sleep 2
Mode, the controller can be awakened by:
(a) Any of the wake-up pin(s) is set to “0.” (Refer to Fig. 5-16). Upon waking, the
controller will continue to execute the program in-line. In this case, before entering
Sleep 2 Mode, the wake-up function of the trigger sources (P60~P67, P74~P75,
and P90~P91) should be selected (e.g. input pin) and enabled (e.g. pull-high,
wake-up control). One caution should be noted is that after waking up, the WDT is
enabled if the Code Option bit ENWDT is "1". The WDT operation (to be enabled or
disabled) should be appropriately controlled by software after waking up.
(b) WDT time-out (if enabled) or external reset input on /RESET pin will trigger a
controller reset.
Table 5 Usage of Sleep and Sleep 2 Mode
Usage of Sleep and Sleep2 Mode
SLEEP2
(a) Before Sleep
1. Set Port6 or P74 or P75 or P90 or P91
Input
SLEEP
(a) Before Sleep
1. Execute SLEP instruction
2. Enable Pull-high and set WDT
prescaler over 1:1 (Set CONT.7 and
CONT.3 ~ CONT.0)
3. Enable Wake-up ( IOCE.0)
4. Execute Sleep 2 (Set IOCE.4)
(b) After Wake-up
1. Next instruction
(b) After Wake-up
1. Reset
2. Disable Wake-up
3. Disable WDT (Set IOCE.5)
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 33
EM78452
8-Bit Microcontroller
If Port6 Input Status Changed Wake-up is used to wake-up the EM78452 (Case [a]
above), the following instructions must be executed before entering Sleep 2 mode:
MOV
A, @11111111b
; Set Port 6 input
IOW
IOC6
MOV
A, @0xxx1010b
; Set Port6 pull-high, WDT prescaler,
; prescaler must set over 1:1
MOV
A, @xx00xxx0b
; Enable Port 6 wake-up function, Enable
; Sleep 2
IOW
IOCE
CONTW
After
Wake-up
NOP
MOV
A, @ xx01xxx1b
IOW
IOCE
; Disable Port 6 wake-up function;
; Disable WDT
After waking up from the Sleep 2 mode, WDT is automatically enabled. The WDT
enabled/disabled operation after waking up from Sleep 2 mode should be properly
defined in the software.
To avoid a reset from occurring when the Port 6 “Input Status Changed Interrupt”
enters into an interrupt vector or is used to wake-up the MCU, the WDT prescaler must
be set above the ratio of 1:1.
34 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Table 6 Summary of the Initialized Values for Registers
Address
Name
N/A
IOC5
N/A
IOC6
N/A
IOC7
N/A
IOC8
N/A
IOC9
N/A
CONT
0x00
R0 (IAR)
0x01
R1 (TCC)
0x02
R2 (PC)
0x03
R3 (SR)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin Change
C57
1
1
P
C67
1
1
P
C77
1
1
P
C87
1
1
P
C97
1
1
P
C56
1
1
P
C66
1
1
P
C76
1
1
P
C86
1
1
P
C96
1
1
P
/INT
0
P
P
U
P
P
0
0
P
1
1
**P
PS1
0
0
P
C55
1
1
P
C65
1
1
P
C75
1
1
P
C85
1
1
P
C95
1
1
P
1
1
P
U
P
P
0
0
P
1
1
**P
PS0
0
0
P
C54
1
1
P
C64
1
1
P
C74
1
1
P
C84
1
1
P
C94
1
1
P
1
1
P
U
P
P
0
0
P
1
1
**P
T
t
t
t
C53
1
1
P
C63
1
1
P
C73
1
1
P
C83
1
1
P
C93
1
1
P
PAB
1
1
P
U
P
P
0
0
P
1
1
**P
P
t
t
t
C52
C51
C50
1
1
1
1
1
1
P
P
P
C62
C61
C60
1
1
1
1
1
1
P
P
P
C72
C71
C70
1
1
1
1
1
1
P
P
P
C82
C81
C80
1
1
1
1
1
1
P
P
P
C92
C91
C90
1
1
1
1
1
1
P
P
P
PSR2 PSR1 PSR0
1
1
1
1
1
1
P
P
P
U
U
U
P
P
P
P
P
P
0
0
0
0
0
0
P
P
P
1
1
1
1
1
1
**P
**P
**P
Z
DC
C
U
U
U
P
P
P
P
P
P
-
-
-
-
-
-
U
U
U
U
U
U
Bit Name
0x04
R4 (RSR)
/PHEN
1
1
P
U
P
P
0
0
P
1
1
**P
GP
0
0
P
RSR.1 RSR.0
Power-on
0
0
Bit 1
Bit 0
/RESET and WDT
0
0
P
P
P
P
P
P
Wake-up from Pin Change
P
P
P
P
P
P
P
P
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 35
EM78452
8-Bit Microcontroller
Address
0x05
Name
R5 (P5)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
P57
P56
P55
P54
P53
P52
P51
P50
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin Change
0x06
0x07
0x08
R6 (P6)
R7 (P7)
R8 (P8)
P
P
P
P
P
P
P
P
Bit Name
P67
P66
P65
P64
P63
P62
P61
P60
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
P77
P76
P75
P74
P73
P72
P71
P70
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
P87
P86
P85
P84
P83
P82
P81
P80
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin Change
0x09
R9 (P9)
P
P
P
P
P
P
P
P
Bit Name
P97
P96
P95
P94
P93
P92
P91
P90
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
0x0A
RA
Power-on
(SPIRB) /RESET and WDT
Wake-up from Pin Change
Bit Name
0x0B
RB
Power-on
(SPIWB) /RESET and WDT
Wake-up from Pin Change
Bit Name
0x0C
RC
(SPIS)
RD
(SPIC)
0x3F
36 •
R3F (ISR)
U
U
U
U
U
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
OD4
-
RBF
DORD TD1
TD2 T1ROS OD3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bit Name
CES
SPIE
SRO
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Wake-up from Pin Change
RE
(TMR1)
U
/RESET and WDT
Bit Name
0x0E
U
Power-on
Wake-up from Pin Change
0x0D
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
Power-on
SPISE SDOC SBRS2 SBRS1 SBRS0
TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
T1IF
Power-on
U
U
U
U
0
SPIIF EXIF
/RESET and WDT
U
U
U
U
0
0
0
0
Wake-up from Pin Change
U
U
U
U
P
P
P
P
0
0
TCIF
0
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Address
0x0C
0x0D
0x0E
0x0F
0x0F~0x3E
Name
IOCC
IOCD
IOCE
IOCF
GPR
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
T1P1 T1P0
Bit Name
-
-
-
-
-
T1E
Power-on
0
0
0
0
0
0
Bit 0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
S7
-
-
-
/PU9
/PU8
/PU6
/PU5
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
ODE
-
-
/WUE
Power-on
U
0
1
1
0
U
U
1
/RESET and WDT
U
0
1
1
0
U
U
1
Wake-up from Pin Change
U
P
1
1
P
U
U
P
WTE SLPC ROC
Bit Name
-
-
-
-
T1IE
Power-on
U
U
U
U
0
SPIIE EXIE
/RESET and WDT
U
U
U
U
0
0
0
0
Wake-up from Pin Change
U
U
U
U
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin Change
P
P
P
P
P
P
P
P
0
TCIE
0
0
**To execute the next instruction after the ”SLPC” bit status of IOCE register being on high-to-low transition.
U: Unknown or don’t care
P: Previous value before reset
X: Not used
–: Not defined
t: Check Table 7
5.7.1 The Status of RST, T, and P of STATUS Register
A reset condition is initiated by the following events:
1. Power-on condition
2. Watchdog timer time-out
The values of T and P, listed in Table 7 are used to check how the processor wakes up.
Table 8 shows the events that may affect the status of T and P.
Table 7 The Values of RST, T and P After RESET
Reset Type
T
P
Power on
1
1
WDT during Operating mode
0
P
WDT wake-up during Sleep 1 mode
0
0
WDT wake-up during Sleep 2 mode
0
P
Wake-Up on pin change during Sleep 2 mode
P
P
*P: Previous value before reset
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 37
EM78452
8-Bit Microcontroller
Table 8 The Status of RST, T and P Being Affected by Events
Event
T
P
Power on
1
1
WDTC instruction
1
1
WDT time-out
0
*P
SLEP instruction
1
0
Wake-up on pin change during Sleep 2 mode
P
P
*P: Previous value before reset
5.8 Interrupt
The EM78452 has the following interrupts.
1. /TCC overflow interrupt
2. External interrupt (/INT)
3. Serial Peripheral Interface (SPI) transmission completed interrupt.
4. Timer 1 overflow interrupt.
R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF
is the interrupt mask register. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (if enabled) is generated, it will
cause the next instruction to be fetched from address 001H. Once in the interrupt
service routine the source of the interrupt can be determined by polling the flag bits in
the R3F register. The interrupt flag bit must be cleared by software before leaving the
interrupt service routine and enabling interrupts to avoid recursive interrupts.
The flag in the Interrupt Status Register (R3F) is set regardless of the status of its mask
bit or the execution of ENI instruction. Note that reading R3F will obtain the output of
logic AND of R3F and IOCF (refer to Fig. 5-16). The RETI instruction exits the interrupt
routine and enables the global interrupt (execution of ENI instruction).
When an interrupt is generated by INT instruction (if enabled), it causes the next
instruction to be fetched from address 002H.
38 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
IRQn
PQ
R
CLK C
L Q
R3F
D
/IRQn
interrupt
IRQm
RFRD
ENI/DISI
Q P D
R
C CLK
Q L
IOD
IOCFWR
IOCF
RESET
IOCFRD
RFWR
Fig. 5-16 Interrupt Input Circuit
5.9 Oscillator
5.9.1 Oscillator Modes
The EM78452 can only operate in high Crystal oscillator mode.
5.9.2 Crystal Oscillator/Ceramic Resonators (Crystal)
EM78452 can be driven by an external clock signal through the OSCI pin as shown in
Fig 5-18. In most applications, pin OSCI and pin OSCO is connected with a crystal or
ceramic resonator to generate oscillation. Fig. 5-18 depicts such circuit. Table 9
provides the recommended values of C1 and C2. Since each resonator has its own
attribute, user should refer to its specification for appropriate values of C1 and C2. RS,
a serial resistor may be necessary for AT strip cut crystal or low frequency mode.
OSCI
Ext. Clock
OSCO
Fig. 5-17 Circuit for External Clock Input
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 39
EM78452
8-Bit Microcontroller
C1
OSCI
XTAL
OSCO
C2
RS
Fig. 5-18 Circuit for Crystal/Resonator
Table 10 Capacitor Selection Guide for Crystal Oscillator Ceramic Resonators
Oscillator Type
Frequency Mode
Ceramic Resonator
HXT
Crystal Oscillator
HXT
Frequency
C1 (pF)
C2 (pF)
455 KHz
1.0 MHz
2.0 MHz
4.0 MHz
455 KHz
1.0 MHz
2.0 MHz
4.0 MHz
10~150
40~80
20~40
10~30
20~40
15~30
15
15
10~150
40~80
20~40
10~30
20~150
15~30
15
15
Fig. 5-19 Circuit for External R, Internal C Oscillator Mode
5.10 Code Option Register :
Word 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ENWDT
CLKS
SPIHSK
REN
SDOS
WUTT
Bit 5 (ENWDT): Watchdog Timer enabled.
0: Enable
1: Disable
Bit 4 (CLKS): Clocks of each instruction cycle.
0: Two clocks
1: Four clocks
Bit 3 (SPIHSK): SPI handshake enable bit
0: enable SPI handshake function. When this bit is set to “0.” In SPI
Slave mode, after SPI control register bit 4(SSE) is set to “1” it will
send a high level through P91 (SRDY). Inform the “master” that the
“Slave” is ready.
1: disable SPI handshake function
40 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Bit 2 (REN): reset pin enable bit
0: enable, P70/reset → reset pin
1: disable, P70/reset → P70
Bit 1(SDOS): Serial data output status select bit
0: enable, SDOC Function enable.,
1: disable, SPI Function, the same as EM78452 waveform.
Bit 0 (WUTT): Wake up Trigger Type
0: Wake up trigger method as EM78P156 (Edge Trigger)
1: Wake up trigger as before (Low Level Trigger).
5.11 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and it
includes one or more operands. All instructions are executed within one single
instruction cycle (consisting of 2 oscillator periods), unless the program counter is
changed by:
(a) Executing the instruction "MOV R2,A", "ADD R2,A", "TBL", or any other instructions
that write to R2 (e.g. "SUB R2,A", "BS R2,6", "CLR R2", ⋅⋅⋅⋅).
(b) execute CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA, DJZ,
DJZA) which were tested to be true.
Under these cases, the execution takes two instruction cycles.
In addition, the instruction set has the following features:
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same
instruction can operate on I/O register.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 41
EM78452
8-Bit Microcontroller
Convention:
R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
42 •
Binary Instruction
Hex
Mnemonic
Operation
0 0000 0000 0000
0000
NOP
No Operation
0 0000 0000 0001
0001
DAA
Decimal Adjust A
0 0000 0000 0010
0002
CONTW
0 0000 0000 0011
0003
0 0000 0000 0100
Status Affected
None
C
A → CONT
None
SLEP
0 → WDT, Stop oscillator
T, P
0004
WDTC
0 → WDT
T, P
0 0000 0000 rrrr
000r
IOW R
A → IOCR
None 1
0 0000 0001 0000
0010
ENI
Enable Interrupt
None
0 0000 0001 0001
0011
DISI
Disable Interrupt
None
0 0000 0001 0010
0012
RET
[Top of Stack] → PC
None
0 0000 0001 0011
0013
RETI
[Top of Stack] → PC,
Enable Interrupt
None
0 0000 0001 0100
0014
CONTR
CONT → A
None
0 0000 0001 rrrr
001r
IOR R
IOCR → A
None 1
0 0000 0010 0000
0020
TBL
0 0000 01rr rrrr
00rr
MOV R,A
A→R
None
0 0000 1000 0000
0080
CLRA
0→A
Z
0 0000 11rr rrrr
00rr
CLR R
0→R
Z
0 0001 00rr rrrr
01rr
SUB A,R
R-A → A
Z, C, DC
0 0001 01rr rrrr
01rr
SUB R,A
R-A → R
Z, C, DC
0 0001 10rr rrrr
01rr
DECA R
R-1 → A
Z
0 0001 11rr rrrr
01rr
DEC R
R-1 → R
Z
0 0010 00rr rrrr
02rr
OR A,R
A ∨ VR → A
Z
0 0010 01rr rrrr
02rr
OR R,A
A ∨ VR → R
Z
0 0010 10rr rrrr
02rr
AND A,R
A&R→A
Z
0 0010 11rr rrrr
02rr
AND R,A
A&R→R
Z
0 0011 00rr rrrr
03rr
XOR A,R
A⊕R→A
Z
0 0011 01rr rrrr
03rr
XOR R,A
A⊕R→R
Z
0 0011 10rr rrrr
03rr
ADD A,R
A+R→A
Z, C, DC
0 0011 11rr rrrr
03rr
ADD R,A
A+R→R
Z, C, DC
0 0100 00rr rrrr
04rr
MOV A,R
R→A
Z
0 0100 01rr rrrr
04rr
MOV R,R
R→R
Z
R2+A → R2,
Bits 8~9 of R2 unchanged
Z, C, DC
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
Binary Instruction
Hex
Mnemonic
0 0100 10rr rrrr
04rr
COMA R
/R → A
Z
0 0100 11rr rrrr
04rr
COM R
/R → R
Z
0 0101 00rr rrrr
05rr
INCA R
R+1 → A
Z
0 0101 01rr rrrr
05rr
INC R
R+1 → R
Z
0 0101 10rr rrrr
05rr
DJZA R
R-1 → A, skip if zero
None
0 0101 11rr rrrr
05rr
DJZ R
R-1 → R, skip if zero
None
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0 0111 01rr rrrr
07rr
SWAP R
0 0111 10rr rrrr
07rr
0 0111 11rr rrrr
0 0110 10rr rrrr
Operation
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
Status Affected
C
C
C
C
None
R(0-3) ↔ R(4-7)
None
JZA R
R+1 → A, skip if zero
None
07rr
JZ R
R+1 → R, skip if zero
None
0 100b bbrr rrrr
0xxx
BC R,b
0 → R(b)
None 2
0 101b bbrr rrrr
0xxx
BS R,b
1 → R(b)
None 3
0 110b bbrr rrrr
0xxx
JBC R,b
if R(b)=0, skip
None
0 111b bbrr rrrr
0xxx
JBS R,b
if R(b)=1, skip
None
None
1 00kk kkkk kkkk
1kkk
CALL k
PC+1 → [SP],
(Page, k) → PC
1 01kk kkkk kkkk
1kkk
JMP k
(Page, k) → PC
None
1 1000 kkkk kkkk
18kk
MOV A,k
k→A
None
1 1001 kkkk kkkk
19kk
OR A,k
A∨k→A
Z
1 1010 kkkk kkkk
1Akk
AND A,k
A&k→A
Z
1 1011 kkkk kkkk
1Bkk
XOR A,k
A⊕k→A
Z
1 1100 kkkk kkkk
1Ckk
RETL k
k → A, [Top of Stack] →
PC
1 1101 kkkk kkkk
1Dkk
SUB A,k
k-A → A
1 1110 0000 0010
1E02
INT
1 1111 kkkk kkkk
1Fkk
ADD A,k
PC+1 → [SP], 002H → PC
k+A → A
None
Z, C, DC
None
Z, C, DC
1
Note: This instruction is applicable to IOC5~IOC9, IOCD ~ IOCF only.
2
3
This instruction is not recommended for RF operation.
This instruction cannot operate on R3F.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 43
EM78452
8-Bit Microcontroller
5.12 Timing Diagrams
AC Test Input/Output W aveform
2.4
2.0
0.8
TEST POINTS
2.0
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
44 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
6
Absolute Maximum Rating
Items
Rating
Temperature under bias
0°C
to
70°C
Storage temperature
-65°C
to
150°C
Input voltage
-0.3V
to
+6.0V
Output voltage
-0.3V
to
+6.0V
DC
to
20MHz
Operating Frequency (2clk)
7
Electrical Characteristics
7.1 DC Characteristic
Ta=25°C, VDD=5V±5%, VSS=0V
Symbol
Parameter
Condition
Crystal VDD to 1.8V
FXT
Crystal VDD to 3.3V
Min
Crystal VDD to 5V
Max
−
4
DC
−
16
DC
−
20
DC
Two clocks
Typ
Unit
MHz
IIL
Input Leakage Current
−
−
±1
μA
VIH1
Input High Voltage VDD=5V)
−
2.0
−
−
V
VIL1
Input Low Voltage (VDD=5V)
−
−
−
0.8
V
VIHX1
Clock Input High Voltage
(VDD=5V)
OSCI
2.5
−
−
V
VILX1
Clock Input Low Voltage
(VDD=5V)
OSCI
−
−
1.0
V
VIHT1
Input high threshold voltage
(Schmitt trigger)
P70/RESET pin
2.0
−
−
V
VILT1
Input low threshold voltage
(Schmitt trigger)
P70/RESET pin
−
−
0.8
V
VIH2
Input High Voltage (VDD=3V)
−
1.5
−
−
V
VIL2
Input Low Voltage (VDD=3V)
−
−
−
0.4
V
OSCI
1.5
−
−
V
OSCI
−
−
0.6
V
2.4
−
−
V
2.4
−
2.4
−
−
2.4
−
−
VIHX2
VILX2
Clock Input High Voltage
(VDD=3V)
Clock Input Low Voltage
(VDD=3V)
VIN = VDD, VSS
Output High Voltage
VOH1
(Ports 5, 6, 8, P74~P77,
IOH = -12.0mA
P90~P92, P95~P97,)
VOH2
VOH3
Output High Voltage
(P70~P72)
Output High Voltage
(P93/SDO, P94/SCK)
S7=1 (IOCD Register Bit 7),
IOH = -9.0mA
S7=0 (IOCD Register Bit 7),
IOH = -12.0mA
IOH = -12.0mA
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
2
V
V
• 45
EM78452
8-Bit Microcontroller
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IOL =12.0mA
−
−
0.4
V
S7=1 (IOCD Register Bit 7),
IOH = 9.0mA
S7=0 (IOCD Register Bit 7),
IOH = 12.0mA
−
0.4
0.8
−
−
0.4
IOL = 12.0mA
−
−
0.4
IOL = 15.0mA
−
−
0.4
Pull-high active, input pin at
VSS
-50
-100
-240
μA
(P74,P75)
Pull-high active, input pin at
VSS
−
1
−
mA
IPH3
Pull high current
(P70/RESET)
Pull-high active, input pin at
VSS
-16
-22
-29
μA
ISB
Power down current
−
−
10
μA
ICC
Operating supply current
−
−
3
mA
Output Low Voltage
VOL1
(Ports 5, 6, 8, P74~P77,
P90~P92, P95~P97)
VOL2
VOL3
VOL4
Output Low Voltage
(P70~P72)
Output Low Voltage
(P93/SDO, P94/SCK)
Output Low Voltage
(P74~P77)
Pull-high current
IPH
IPH2
Pull-high current
V
All input and I/O pin at VDD,
output pin floating, WDT
enabled
/RESET="High",
Fosc=1.84324MHz (CK2="0"),
output pin floating
V
−
6.2 AC Characteristic
Ta=0°C~70°C, VDD=5V±5%, VSS=0V
Symbol
Dclk
Tins
Parameter
Min
Typ
Max
Unit
−
45
50
55
%
500
−
DC
ns
(Tins+20)/N*
−
−
ns
−
18
−
ms
−
ms
Input CLK duty cycle
Instruction cycle time
(CK2="0")
Ttcc
TCC input period
Twdt
Watchdog timer period
Tdrh
Conditions
Device reset hold period
RC Type
−
Ta=25°C
Ta=25°C
−
18
3
*N= selected prescaler ratio.
3
46 •
Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 18.0ms ± 30%
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
8
Application Circuit
EM78452
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 47
EM78452
8-Bit Microcontroller
APPENDIX
A Package Type:
OTP MCU
Package Type
Pin Count
Package Size
EM78452P
DIP
40
600 mil
EM78452WM
SOP
40
450 mil
EM78452AQ
QFP
44
B Package Information
B.1 40-Lead Plastic Dual in line (PDIP) — 600 mil
48 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
EM78452
8-Bit Microcontroller
B.2 44-Lead Quad Flat Package (QFP)
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
• 49
EM78452
8-Bit Microcontroller
50 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
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