DATASHEET ISL59833 FN6334 Rev 1.00 March 5, 2007 200MHz Single Supply Video Driver With Charge Pump The ISL59833 is a revolutionary device that allows true singlesupply operation of video amplifiers. Designed for systems requiring output swing below ground but lacking a negative power supply, the ISL59833 generates the required negative rail internally from a +3.3V power supply. This allows for DC-accurate coupling of video onto a 75 double-terminated line. The buffers have an integrated 6dB, eliminating the need for external gain-setting resistors. An external reference voltage can be applied to the REF pin to shift the analog video level down by the desired amount. • Triple single-supply buffer • Generates negative rail from from single +3.3V supply • No output DC blocking capacitor needed • 200MHz -3dB bandwidth • 50MHz 0.1dB bandwidth • Fixed gain of 2 output buffer • Amplifier enable/disable function control Ordering Information • Outputs are high impedance in power-down mode PART NUMBER PART TAPE & (Note) MARKING REEL ISL59833IAZ Features PACKAGE (Pb-free) PKG. DWG. # 59833 IAZ - 16 Ld QSOP MDP0040 ISL59833IAZ-T7 59833 IAZ 7” 16 Ld QSOP MDP0040 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Pb-free plus anneal available (RoHS compliant) Applications • Driving video Pinout ISL59833 (16 LD QSOP) TOP VIEW RIN 1 16 ROUT GIN 2 15 GOUT BIN 3 14 BOUT REF 4 13 VCC VEE 5 12 EN GND 6 11 VCC VEEOUT 7 DGND 8 FN6334 Rev 1.00 March 5, 2007 10 NC 9 DVCC Page 1 of 15 ISL59833 Absolute Maximum Ratings Thermal Information VCC, Supply Voltage between VS and GND . . . . . . . . . . . . . . . . .5V VIN, VREF . . . . . . . . . . . . . . . . . . . . . . . . . .VCC + 0.3V, VEE - 0.3V Voltage between VIN and VREF . . . . . . . . . . . . . . . . . . . . . . . . . .±2V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA AC Electrical Specifications PARAMETER BW - 3dB VCC = DVCC = +3.3V, REF = GND, TA = +25°C, RL = 150, unless otherwise specified. DESCRIPTION 3dB Bandwidth CONDITIONS MIN TYP MAX UNIT VOUT = 200mVPP 200 MHz VOUT = 2VPP 100 MHz 50 MHz BW 0.1dB 0.1dB Bandwidth VOUT = 2VPP SR Slew Rate VIN = 2VPP dG Differential Gain 0.07 % dP Differential Phase 0.06 ° XT Hostile Crosstalk 6MHz -90 dB I Input to Output Isolation 6MHz -70 dB VN Input Noise Voltage 20 nV/Hz fCP Charge Pump Switching Frequency 168 MHz Load Reg VEE Load Regulation VRIPPLE Output Amp Ripple Voltage 500 IEE = 0mA to 10mA 9 With Bead Core to DVCC DC Electrical Specifications PARAMETER V/µs 30 mV 30 mV 10 mV VCC = DVCC = +3.3V, REF = GND, TA = +25°C, RL = 150, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP UNIT 3.6 V 1.5 % V+ Supply Range VG% Gain Error RL = 150, VOUT = -1V to +2.5V G Gain Matching RL = 150 0.5 IIN Analog Input Leakage Current VIN = 0V to 1.5V ±0.1 ±1 µA VOS Output Offset Voltage VREF = 0 -25 7 +25 mV VOUT + Maximum Output Voltage RL = 75 2.4 2.5 V RL = 150 2.7 2.9 V VOUT - Minimum Output Voltage 3.0 MAX RL = 75 -1.3 -1 V RL = 150 -1.5 -1.2 V IOUT + Output Current RL = 10, VIN = 1.2V IOUT - Output Current RL = 10, VIN = -0.3V -40 ZOUT Disabled Output Impedance EN = 3.3V (Amp Disabled) 500 IREF Reference Input Leakage Current 1 2.3 PSRR Power Supply Rejection Ratio 50 62 FN6334 Rev 1.00 March 5, 2007 % 50 80 mA -18 mA k 3.5 µA dB Page 2 of 15 ISL59833 DC Electrical Specifications PARAMETER IS VCC = DVCC = +3.3V, REF = GND, TA = +25°C, RL = 150, unless otherwise specified. (Continued) DESCRIPTION CONDITIONS Supply Current MIN TYP MAX UNIT EN = GND (Amp Enabled) 97 130 mA EN = 3.3V (Amp Disabled) 60 90 mA Pin Descriptions PIN NUMBER PIN NAME 1 RIN PIN FUNCTION EQUIVALENT CIRCUIT Analog input VCC VEE CIRCUIT 1 2 GIN Analog input Reference Circuit 1 3 BIN Analog input Reference Circuit 1 4 REF Reference input High impedance input controlling offset of amplifiers RIN GIN BIN VCC x1 REF ROUT GOUT BOUT + 3 VEE CIRCUIT 2 5 VEE Chip substrate (negative power supply for amplifiers) VCC VEE OUT - + DVCC VEE CHARGE PUMP DGND CIRCUIT 3 6 GND 7 VEE OUT Charge pump output Reference Circuit 3 8 DGND Charge pump ground Reference Circuit 3 9 DVCC Charge pump supply voltage Reference Circuit 3 10 NC 11, 13 VCC FN6334 Rev 1.00 March 5, 2007 Analog ground Not connected Positive power supply Page 3 of 15 ISL59833 Pin Descriptions (Continued) PIN NUMBER PIN NAME PIN FUNCTION EQUIVALENT CIRCUIT 12 EN Power-down Input Low: Normal Operation High: Power-down Charge Pump and Amplifiers VCC VEE CIRCUIT 4 14 BOUT Analog output VCC VEE CIRCUIT 5 15 GOUT Analog output Reference Circuit 5 16 ROUT Analog output Reference Circuit 5 Typical Performance Curves 5 AV = +2 CL = 0pF 2 1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 3 1k 0 500 -1 -2 150 AV = +2 RL = 500 9pF 4.7pF 3 2.2pF 1 0pF -1 -3 75 -3 1M 10M 100M -5 100k 1G -5 -10 -15 -20 -25 300 AV = +2 RL = 500 240 -3dB ROLL-OFF 180 120 60 -0.1dB ROLL-OFF -30 -35 1G FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD GAIN ROLL-OFF (MHz) NORMALIZED OUTPUT (dB) AV = +2 CL = 0pF RL = 500 0 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD 5 10M 1M 1 100 200 300 400 500 FREQUENCY (MHz) FIGURE 3. VREF PIN OUTPUT FREQUENCY RESPONSE FN6334 Rev 1.00 March 5, 2007 0 2.25 2.80 3.35 3.90 4.45 5.00 TOTAL SUPPLY VOLTAGE, VCC - VEE (V) FIGURE 4. GAIN ROLL-OFF Page 4 of 15 ISL59833 Typical Performance Curves (Continued) 1.6 AV = +2 -40 RL = 500 -50 CROSS TALK (dB) 1.2 PEAKING (dB) -30 AV = +2 RL = 500 CL = 3.9pF 0.8 0.4 -60 ENABLED -70 -80 DISABLED -90 -100 -110 0 2.2 2.6 2.4 2.8 3.0 3.2 3.4 3.6 3.8 -120 100k 4.0 120 SUPPLY CURRENT (mA) AV = +2 -30 RL = 500 ISOLATION (dB) -40 -50 -60 -70 -80 -90 10M 100M AV = +2 RL = 500 100 80 60 40 20 0 1.0 1G 1.5 FREQUENCY (Hz) 3.0 3.5 FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE 200 95 AV = +2 RL = 500 120 80 40 SUPPLY CURRENT (mA) -3dB BANDWIDTH (MHz) 2.5 2.0 SUPPLY VOLTAGE (V) FIGURE 7. INPUT TO OUTPUT ISOLATION vs FREQUENCY 160 1G FIGURE 6. CROSS TALK CHANNEL TO CHANNEL (TYPICAL) -20 1M 100M FREQUENCY (Hz) SUPPLY VOLTAGE (V) FIGURE 5. PEAKING vs SUPPLY VOLTAGE -100 100k 10M 1M 90 AV = +2 RL = 500 VCL = 3.3V 85 80 -0.1dB 0 25 55 85 115 TEMPERATURE (°C) FIGURE 9. BANDWIDTH vs TEMPERATURE FN6334 Rev 1.00 March 5, 2007 145 75 25 55 85 115 145 TEMPERATURE (°C) FIGURE 10. SUPPLY CURRENT vs TEMPERATURE Page 5 of 15 ISL59833 Typical Performance Curves (Continued) 0 VCC = DVCC = 3.3V -10 VAC = 100mVP-P RL = 150 -20 100 PSRR (dB) IMPEDANCE () 10 1 -30 -40 -50 -60 0.1 -70 0.01 10k 100k 1M -80 10k 100M 10M 100k FIGURE 12. POWER SUPPLY REJECTION RATIO vs FREQUENCY -30 HARMONIC DISTORTION (dBc) 1k VOLTAGE NOISE (nV/Hz), CURRENT NOISE (pA/Hz) 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY 100 eN 10 IN+ 1 IN0.1 10 1M 100 1k 10k 100k 1M -40 -60 -70 2ND HD 3RD HD -80 -90 -100 10M THD -50 0 10 20 30 40 FUNDAMENTAL FREQUENCY (MHz) FREQUENCY (Hz) FIGURE 13. VOLTAGE AND CURRENT NOISE vs FREQUENCY FIGURE 14. HARMONIC DISTORTION vs FREQUENCY -30 0 -40 DIFFERENTIAL GAIN (%) THD (dBc) -50 THD FIN = 10MHz -60 -70 THD FIN = 1MHz -80 -90 0.5 1.0 1.5 2.0 -0.02 -0.04 -0.06 -0.08 2.5 3.0 3.5 IRE OUTPUT VOLTAGE (VP-P) FIGURE 15. THD vs OUTPUT VOLTAGE FN6334 Rev 1.00 March 5, 2007 FIGURE 16. DIFFERENTIAL GAIN Page 6 of 15 ISL59833 Typical Performance Curves (Continued) VOLTS (500mV/DIV) DIFFERENTIAL PHASE (°) 0 -0.02 -0.04 -0.06 -0.08 TIME (2µs/DIV) IRE FIGURE 18. DISABLE TIME VOLTS (50mV/DIV) VOLTS (500mV/DIV) FIGURE 17. DIFFERENTIAL PHASE TIME (200ns/DIV) FIGURE 19. ENABLE TIME TIME (10ns/DIV) FIGURE 20. SMALL SIGNAL RISE AND FALL TIMES 0 -10 NOISE (dBV) VOLTS (500mV/DIV) -20 -30 -40 -50 -60 -70 -80 -90 TIME (10ns/DIV) FIGURE 21. LARGE SIGNAL RISE AND FALL TIMES FN6334 Rev 1.00 March 5, 2007 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (Hz) FIGURE 22. NOISE FLOOR WITH CHARGE PUMP HARMONICS Page 7 of 15 ISL59833 Typical Performance Curves (Continued) 1.6 BACKDRIVE CURRENT (mA) OUTPUT RANGE (V) 3.25 3.00 2.75 2.50 50 AV = +2 CL = 3.9pF 250 450 650 850 1.2 VCC = 3.3V 0.8 0.4 0 1050 BACKDRIVE ACROSS 5 RESISTOR TYPICAL CHANNEL 0 2 1 LOAD RESISTANCE () 5 FIGURE 24. BACKDRIVE VOLTAGE vs CURRENT AMP DISABLED OUTPUT LOADING JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.8 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.6 1.2 POWER DISSIPATION (W) POWER DISSIPATION (W) 4 BACKDRIVE VOLTAGE (V) FIGURE 23. MAXIMUM OUTPUT MAGNITUDE vs LOAD RESISTANCE 1.4 3 1.0 791mW 0.8 QS OP 16 A= +1 58 °C /W J 0.6 0.4 0.2 1.4 1.116W 1.2 1.0 J QS A= +1 0.8 OP 12 0.6 16 °C /W 0.4 0.2 0 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6334 Rev 1.00 March 5, 2007 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Page 8 of 15 ISL59833 Block Diagram VCC RIN + 6dB ROUT 6dB GOUT 6dB BOUT REF GIN + - BIN + - DVCC CHARGE PUMP VEE-OUT VEE VOUT = 2VIN - VREFERENCE FN6334 Rev 1.00 March 5, 2007 Page 9 of 15 ISL59833 FN6334 Rev 1.00 March 5, 2007 ISL59833 + DC-Restore Solution 1 IN1 IN2 16 2 COM1 COM2 15 3 NC1 NC2 14 4 V- R7 2k V+ 13 5 GND NC 12 (No Connect) 6 NC4 NC3 11 7 COM4 YO Pb Pr R1 75 R2 75 COM3 10 8 IN4 IN3 9 ISL43140 C4 0.1µF C5 0.1µF C6 0.1µF C7 0.1µF R3 75 VEE (-1.6V) R9 2k 1k R12 VCC C11 0.1µF OFFSET CONTROL CN = Option for lower charge pump noise R10 2k 1 RIN ROUT 16 2 GIN GOUT 15 3 BIN BOUT 14 4 REF VCC 13 5 VEE EN 12 6 GND VCC 11 7 VEEOUT 8 DGND 75 R5 75 R6 75 C12 20pF C13 20pF VCC C1 0.1µF ENABLE 2 1 NC 10 DVCC 9 R4 C15 0.1µF 3 C14 20pF VCC VCC GND + C16 YO Pb Pr VCC 1µF ISL59833 C4 0.1µF Page 10 of 15 C10 0.1µF 1 COMP VDD 8 2 COMP OUT 7 SYNC OUT VIDEO IN 3 VSYNC OUT 4 GND RESET 6 BACK PORCH 5 OUT EL1881 C8 0.1µF R13 C9 0.1µF 681k Option: Panasonic 120Bead EXC3BP121H Lower Amp output noise from charge pump ISL59833 Demo Board Schematic RED_IN R1 75 RED_OUT GREEN_IN R2 75 C4 0.1µF R3 75 VCC R4 R8 C2 0.1µF 499 1k OFFSET CONTROL 1 RIN ROUT 16 2 GIN GOUT 15 3 BIN BOUT 14 4 REF VCC 13 5 VEE EN 12 6 GND VCC 11 7 VEEOUT 8 DGND Description of Operation and Application Information Theory Of Operation The ISL59833 is a highly practical and robust marriage of three high bandwidth, high speed, low power, rail-to-rail voltage feedback amplifiers with a charge pump to provide a negative rail without an additional power supply. Designed to operate with a single supply voltage range from 0V to 3.3V, the ISL59833 eliminates the need for a split supply with the incorporation of a charge pump capable of generating a bottom rail as much as 1.6V below ground for a 4.9V range on a single 3.3V supply. This performance is ideal for NTSC video with its negative-going sync pulses. THE AMPLIFIER The ISL59833 fabricated on a di-electrically isolated high speed 5V Bi-CMOS process with 4GHz PNPs and NPN transistor exceeding 20GHz - perfect for low distortion, low power demand and high frequency circuits. While the ISL59833 utilizes somewhat standard voltage mode feedback topologies, there are many non-standard analog features providing its outstanding bandwidth, rail-to-rail operation, and output drive capabilities. The input signal initially passes through a folded cascode, a topology providing enhanced frequency response by essentially fixing the base collector voltage at the junction of the input and gain stage. The collector of each input device looks directly into an emitter that is tied closely to ground through a resistor and biased with a very stable DC source. Since the voltage of this collector is "locked stable" the effective bandwidth limiting of the Miller capacitance is greatly reduced. The signal is then passed through a second fully-realized differential gain stage and FN6334 Rev 1.00 March 5, 2007 75 R5 75 R6 75 GREEN_OUT VCC BLUE_OUT C3 0.1µF ENABLE 2 1 NC 10 DVCC 9 R4 C5 0.1µF VCC 3 Option: Panasonic 120Bead EXC3BP121H Lower Amp output noise from charge pump finally through a proprietary common emitter output stage for improved rail-to-rail output performance. The result is a highly-stable, low distortion, low power, and high frequency amplifier capable of driving moderately capacitive loads with near rail-to-rail performance. INPUT OUTPUT RANGE The three amplifier channels have an input common mode voltage range from 0.15V below the bottom rail to within 100mV of the positive supply, VS+ pin (Note: bottom rail is established by the charge pump at negative one half the positive supply). As the input signal moves outside the specified range, the output signal will exhibit increasingly higher levels of harmonic distortion. And of course, as load resistance becomes lower, the current drive capability of the device will be challenged and its ability to drive close to each rail is reduced. For instance, with a load resistance of 1k the output swing is within a 100mV of the rails, while a load resistance of 150 limits the output swing to within around 300mV of the rails. AMPLIFIER OUTPUT IMPEDANCE To achieve near rail-to-rail performance, the output stage of the ISL59833 uses transistors in the common emitter configuration, typically producing higher output impedance than the standard emitter follower output stage. The exceptionally high open loop gain of the ISL59833 and local feedback reduces output impedance to less than a 2 at low frequency. However, since output impedance of the device is exponentially modulated by the magnitude of the open loop gain, output impedance increases with frequency as the open loop gain decreases with frequency. This inductive-like effect of the output impedance is countered in the ISL59833 with Page 11 of 15 ISL59833 proprietary output stage topology, keeping the output impedance low over a wide frequency range and making it possible to easily and effectively drive relatively heavy capacitive loads (see Figure 11). THE CHARGE PUMP The ISL59833 charge pump provides a bottom rail up to 1.65V below ground while operating on a 0V to 3.3V power supply. The charge pump is internally regulated to one-half the potential of the positive supply. This internal multi-phase charge pump is driven by a 110MHz differential ring oscillator driving a series of inverters and charge storage circuitry. Each series inverter charges and places parallel adjoining charge circuitry slightly out of phase with the immediately preceding block. This generates a negative rail of about -1.6V with a low amplitude ripple voltage from the charge pump action. Some of this ripple is coupled into the output signals at a very low IN+ amplitude, as seen in Figure 22. The ripple on the outputs is typically well below the noise floor of the signal. There are two ways to further reduce the output supply noise: • Add a 120bead in series between VCC and DVCC. This reduces the coupling between the charge pump and the analog amplifier supplies. • Add a 20pF capacitor between the back load 75 resistor and ground (see “ISL59833 + DC-Restore Solution” on page 10). This will attenuate frequencies above 100MHz. The system operates at sufficiently high frequencies that any related charge pump noise is far beyond standard video bandwidth requirements. Still, appropriate bypassing discipline must be observed, and all pins related to either the power supply or the charge pump must be properly bypassed. See “Power Supply Bypassing and Printed Circuit Board Layout” on page 14. IN- OUT BIAS FIGURE 27. SIMPLIFIED SCHEMATIC FN6334 Rev 1.00 March 5, 2007 Page 12 of 15 ISL59833 THE VREF PIN Applying a voltage to the VREF pin simply places that voltage on what would usually be the ground side of the gain resistor of the amplifier, resulting in a DC-level shift of the output signal. Applying 100mV to the VREF pin would apply a -100mV DC level shift to the outgoing signal. The charge pump provides sufficient bottom room to accommodate the shifted signal. VREF may be connected to ground for back porch at ground. The ISL59833 buffers the VREF voltage before applying it to the triple amplifiers, isolating the input from the amplifiers and allowing it to be driven by moderate-impedance voltage sources. THE VEE PIN The VEE pin is the output pin for the charge pump. A voltmeter applied to this pin will display the output of the charge pump. This pin does not affect the functionality of the part. One may use this pin as an additional voltage source. Keep in mind that the output of this pin is generated by the internal charge pump and a fully regulated supply that must be properly bypassed. We recommend a 0.1µF ceramic capacitor placed as close to the pin and connected to the ground plane of the board. INPUT, OUTPUT AND SUPPLY VOLTAGE RANGE The ISL59833 is designed to operate with a single supply voltage range of from 0V to 3.3V. The need for a split supply has been eliminated with the incorporation of a charge pump capable of generating a bottom rail as much as 1.6V below ground, for a 4.9V range on a single 3.3V supply. This performance is ideal for NTSC video with its negative-going sync pulses. VIDEO PERFORMANCE For good video performance, an amplifier is required to maintain the same output impedance and the same frequency and phase response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150 because of the change in output current with changing DC levels. Special circuitry has been incorporated into the ISL59833 for the reduction of output impedance variation with the current output. This results in outstanding differential gain and differential phase specifications of 0.06% and 0.1°, while driving 150 at a gain of +2. Driving higher impedance loads would result in similar or better differential gain and differential phase performance. NTSC The ISL59833 (generating a negative rail internally) is ideally suited for NTSC video with its accompanying negative-going sync signals, which is easily handled by the ISL59833 without the need for an additional supply as the ISL59833 generates a negative rail with an internal charge pump referenced at negative 1/2 the positive supply. FN6334 Rev 1.00 March 5, 2007 YPbPr YPbPr signals originating from a DVD player requiring three channels of very tightly-controlled amplifier gain accuracy present no difficulty for the ISL59833. Specifically, this standard encodes sync on the Y channel and it is a negativegoing signal, which is easily handled by the ISL59833 without the need for an additional supply as the ISL59833 generates a negative rail placed at negative 1/2 the positive supply. Additionally, the Pb and Pr are bipolar analog signals and the video signals are negative-going, and again, easily handled by the ISL59833. DRIVING CAPACITIVE LOADS AND CABLES The ISL59833 (internally-compensated to drive 75 cables) will drive 10pF loads in parallel with 1k with less than 5dB of peaking. If less peaking is required, a small series resistor, usually between 5 to 50, can be placed in series with the output. This will reduce peaking at the expense of a slight closed loop gain reduction. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a backtermination resistor. Again, a small series resistor at the output can help to reduce peaking. The ISL59833 is a triple amplifier designed to drive three channels; simply deal with each channel separately as described in this section. DC-RESTORE When the ISL59833 is AC-coupled it becomes necessary to restore the DC reference for the signal. This is accomplished with a DC-restore system applied between the capacitive "AC" coupling and the input of the device. Refer to “ISL59833 + DCRestore Solution” on page 10. AMPLIFIER DISABLE The ISL59833 can be disabled and its output placed in a high impedance state. The turn-off time is around 25ns and the turnon time is around 200ns. When disabled, the amplifier's supply current is reduced to 80mA typically, reducing power consumption. The amplifier's power-down can be controlled by standard TTL or CMOS signal levels at the EN pin. The applied logic signal is relative to the GND pin. Letting the EN pin float or applying a signal that is less than 0.8V above GND will enable the amplifier. The amplifier will be disabled when the signal at EN pin is 2V above GND. The VEE charge pump remains active. OUTPUT DRIVE CAPABILITY The ISL59833 does not have internal short-circuit protection circuitry. A short-circuit current of 80mA sourcing and 150mA sinking for the output is connected half way between the rails with a 10 resistor. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output Page 13 of 15 ISL59833 current never exceeds ±40mA, after which the electromigration limit of the process will be exceeded and the part will be damaged. This limit is set by the design of the internal metal interconnections. Where: VS = Supply voltage ISMAX = Maximum quiescent supply current POWER DISSIPATION VOUT = Maximum output voltage of the application With the high output drive capability of the ISL59837, it is possible to exceed the +150°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. RLOAD = Load resistance tied to ground The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX PD MAX = -------------------------------------------- JA (EQ. 1) Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: for sourcing: V OUT i PD MAX = V S I SMAX + V S – V OUT i ----------------RL i (EQ. 2) for sinking: PD MAX = V S I SMAX + V OUT i – V S I LOAD i (EQ. 3) FN6334 Rev 1.00 March 5, 2007 ILOAD = Load current i = Number of output channels By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout Strip line design techniques are recommended for the input and output signal traces. As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VSpin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split-internal supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire-wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is also very important. Page 14 of 15 ISL59833 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X © Copyright Intersil Americas LLC 2006-2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6334 Rev 1.00 March 5, 2007 Page 15 of 15