STMicroelectronics M40SZ100WMQ 5v or 3v nvram supervisor for lpsram Datasheet

M40SZ100Y
M40SZ100W
5V or 3V NVRAM SUPERVISOR FOR LPSRAM
FEATURES SUMMARY
■ CONVERT LOW POWER SRAMs INTO
NVRAMs
■
5V OR 3V OPERATING VOLTAGE
■
PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
■
AUTOMATIC WRITE-PROTECTION WHEN
VCC IS OUT-OF-TOLERANCE
■
CHOICE OF SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
■
– M40SZ100Y: VCC = 4.5 to 5.5V;
4.20V ≤ VPFD ≤ 4.50V
– M40SZ100W: VCC = 2.7 to 3.6V;
2.55V ≤ VPFD ≤ 2.70V
RESET OUTPUT (RST) FOR POWER ON
RESET
■
1.25V REFERENCE (for PFI/PFO)
■
LESS THAN 10ns CHIP ENABLE ACCESS
PROPAGATION DELAY (at 5V)
■
OPTIONAL PACKAGING INCLUDES A 28LEAD SOIC and SNAPHAT® TOP (to be
ordered separately)
■
■
28-LEAD SOIC PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY
Figure 1. 16-pin SOIC Package
16
1
SO16 (MQ)
Figure 2. 28-pin SOIC Package*
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
BATTERY LOW PIN (BL)
* Contact Local Sales Office
September 2003
Rev. 1.3
1/19
M40SZ100Y, M40SZ100W
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram (Figure 3.) . . . . . . .
Signal Names (Table 1.) . . . . . . . .
SOIC16 Connections (Figure 4.) . .
SOIC28 Connections (Figure 5.) . .
Block Diagram (Figure 6.) . . . . . . .
Hardware Hookup (Figure 7.) . . . .
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...........4
...........4
...........4
...........5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Testing Load Circuit (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Testing Input/Output Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Down Timing (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Up Timing (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Down/Up AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-on Reset Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset Input (RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RSTIN Timing Waveform (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Battery Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply Voltage Protection (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SNAPHAT® Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
M40SZ100Y, M40SZ100W
SUMMARY DESCRIPTION
The M40SZ100Y/W NVRAM Controller is a selfcontained device which converts a standard lowpower SRAM into a non-volatile memory. A precision voltage reference and comparator monitors
the VCC input for an out-of-tolerance condition.
When an invalid VCC condition occurs, the conditioned chip enable output (ECON) is forced inactive
to write protect the stored data in the SRAM. During a power failure, the SRAM is switched from the
VCC pin to the lithium cell within the SNAPHAT (or
external battery for the 16-lead SOIC) to provide
the energy required for data retention. On a subsequent power-up, the SRAM remains write protected until a valid power condition returns.
The 28-pin, 330 mil SOIC provides sockets with
gold plated contacts for direct connection to a separate SNAPHAT® housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent improper insertion. This unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a soldered holder. Providing non-volatility becomes a
“SNAP.” This feature is also available in the “topless” 16-pin SOIC package (MQ).
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion.
The 28-pin SOIC and battery packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4ZXX-BR00SH” (see Table 13, page 17).
Caution: Do not place the SNAPHAT battery top
in conductive foam, as this will drain the lithium
button-cell battery.
Figure 3. Logic Diagram
Table 1. Signal Names
E
VCC VBAT(1)
VOUT
PFI
ECON
Conditioned Chip Enable Output
RST
Reset Output (Open Drain)
RSTIN
BL
E
Chip Enable Input
Reset Input
Battery Low Output (Open Drain)
BL
M40SZ100Y
M40SZ100W
ECON
VOUT
Supply Voltage Output
VCC
Supply Voltage
PFO
RSTIN
VBAT (1)
Back-up Supply Voltage
RST
VSS
Note: 1. For 16-pin SOIC package only.
PFI
Power Fail Input
PFO
Power Fail Output
VSS
Ground
NC
Not Connected Internally
AI03933
Note: 1. For SO16 only.
3/19
M40SZ100Y, M40SZ100W
Figure 4. SOIC16 Connections
1
16
15
2
14
3
4 M40SZ100Y 13
5 M40SZ100W 12
11
6
7
10
8
9
NC
NC
RST
NC
RSTIN
PFO
VBAT
VSS
Figure 5. SOIC28 Connections
VCC
NC
VOUT
NC
PFI
BL
E
ECON
AI03935
BL
NC
NC
NC
NC
NC
NC
NC
RSTIN
NC
NC
NC
PFO
VSS
1
28
27
2
26
3
25
4
24
5
23
6
7 M40SZ100Y 22
8 M40SZ100W 21
20
9
19
10
18
11
17
12
16
13
15
14
VCC
NC
NC
VOUT
NC
NC
PFI
NC
E
NC
RST
NC
NC
ECON
AI03934
Note: 1. DU = Do Not Use
Figure 6. Block Diagram
VOUT
VCC
VBAT
VBL= 2.5V
COMPARE
VSO = 2.5V
COMPARE
VPFD= 4.4V
COMPARE
BL
(1)
POR
(2.65V for SZ100W)
RSTIN
RST(1)
E
ECON
PFI
COMPARE
PFO
1.25V
AI04766
Note: Open drain output
4/19
M40SZ100Y, M40SZ100W
Figure 7. Hardware Hookup
3.0V, 3.3V or 5V
Regulator
Unregulated
Voltage
VIN
VCC
VOUT
VCC
VCC
0.1µF
M40SZ100Y
M40SZ100W
0.1µF
1Mb or 4Mb
LPSRAM
E
E
From Microprocessor
RSTIN
R1
ECON
PFI
PFO
To Microprocessor NMI
VSS
RST
To Microprocessor Reset
BL
To Battery Monitor Circuit
R2
VBAT(1)
AI04767
Note: 1. User supplied for the 16-pin package
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
TSTG
TSLD(1)
Parameter
Storage Temperature (VCC Off)
Value
Unit
SNAPHAT
–40 to 85
°C
SOIC
–55 to 125
°C
260
°C
–0.3 to VCC +0.3
V
M40SZ100Y
–0.3 to 7
V
M40SZ100W
–0.3 to 4.6
V
20
mA
1
W
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltages
VCC
Supply Voltage
IO
Output Current
PD
Power Dissipation
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
5/19
M40SZ100Y, M40SZ100W
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 3. DC and AC Measurement Conditions
Parameter
M40SZ100Y
M40SZ100W
VCC Supply Voltage
4.5 to 5.5V
2.7 to 3.6V
Ambient Operating Temperature
–40 to 85°C
–40 to 85°C
Load Capacitance (CL)
100pF
50pF
Input Rise and Fall Times
≤ 5ns
≤ 5ns
Input Pulse Voltages
0.2 to 0.8VCC
0.2 to 0.8VCC
Input and Output Timing Ref. Voltages
0.3 to 0.7VCC
0.3 to 0.7VCC
Figure 9. AC Testing Input/Output Waveforms
Figure 8. AC Testing Load Circuit
333Ω
DEVICE
UNDER
TEST
0.8VCC
CL = 100pF
or 50pF
0.7VCC
1.73V
0.3VCC
0.2VCC
AI02568
CL includes JIG capacitance
AI02393
Note: 1. CL = 100pF for M40SZ100Y and 50pF for M40SZ100W.
Table 4. Capacitance
Parameter(1,2)
Symbol
CIN
COUT(3)
Max
Unit
Input Capacitance
7
pF
Output Capacitance
10
pF
Note: 1. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected
6/19
Min
M40SZ100Y, M40SZ100W
Table 5. DC Characteristics
Sym
ICC
ICCDR
ILI(3)
Parameter
Supply Current
Test Condition(1)
M40SZ100Y
Min
Outputs open
50
0V ≤ VIN ≤ VCC
Input Leakage
Current (PFI)
Max
Min
Typ
1
Data Retention Mode
Current(2)
Input Leakage
Current
Typ
M40SZ100W
200
50
±1
–25
2
25
–25
2
Max
Unit
0.5
mA
200
nA
±1
µA
25
nA
Output Leakage
Current
0V ≤ VOUT ≤ VCC
±1
±1
µA
VOUT Current
(Active)
VOUT > VCC – 0.3
175
100
mA
IOUT2
VOUT Current
(Battery Back-up)
VOUT > VBAT – 0.3
100
100
µA
VBAT
Battery Voltage
3.5(6)
V
VCC + 0.3
V
0.3VCC
V
ILO(4)
IOUT1(5)
2.5
VIH
Input High Voltage
0.7VCC
VIL
Input Low Voltage
–0.3
VOH
Output High
Voltage(7)
VOHB
VOL
VPFD
VPFI
IOH = –1.0mA
2.4
VOH Battery Backup(8)
IOUT2 = –1.0µA
2.5
Output Low Voltage
IOL = 3.0mA
Output Low Voltage
(open drain)(9)
IOL = 10mA
Power-fail Deselect
Voltage
PFI Input Threshold
PFI Hysteresis
VSO
Battery Back-up
Switchover Voltage
VCC = 5V(Y)
VCC = 3V(V)
PFI Rising
3.0
3.5(6)
2.5
3.0
VCC + 0.3 0.7VCC
0.3VCC
–0.3
2.4
2.9
3.5
2.5
V
2.9
3.5
V
0.4
0.4
V
0.4
0.4
V
4.20
4.40
4.50
2.55
2.60
2.70
V
1.225
1.250
1.275
1.225
1.250
1.275
V
20
70
20
70
mV
2.5
2.5
V
Note: 1.
2.
3.
4.
5.
6.
7.
8.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V(except where noted).
Measured with VOUT and ECON open.
RSTIN internally pulled-up to VCC through 100kΩ resistor.
Outputs deselected.
External SRAM must match SUPERVISOR chip VCC specification (3V or 5V).
For rechargeable back-up, VBAT (max) may be considered VCC – 0.5V.
For PFO pin (CMOS).
Chip Enable output (ECON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will reduce battery life.
9. For RST & BL pins (Open Drain).
7/19
M40SZ100Y, M40SZ100W
OPERATION
The M40SZ100Y/W, as shown in Figure 7, page 5,
can control one (two, if placed in parallel) standard
low-power SRAM. This SRAM must be configured
to have the chip enable input disable all other input
signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not.
During normal operating conditions, the conditioned chip enable (ECON) output pin follows the
chip enable (E) input pin with timing shown in Table 6, page 10. An internal switch connects VCC to
VOUT. This switch has a voltage drop of less than
0.3V (IOUT1).
When VCC degrades during a power failure, ECON
is forced inactive independent of E. In this situation, the SRAM is unconditionally write protected
as VCC falls below an out-of-tolerance threshold
(VPFD). For the M40SZ100Y/W the power fail detection value associated with VPFD is shown in Table 5, page 7.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to completion before the memory is write protected. If the
memory cycle is not terminated within time tWPT,
ECON is unconditionally driven high, write protecting the SRAM. A power failure during a WRITE cycle may corrupt data at the currently addressed
location, but does not jeopardize the rest of the
SRAM's contents. At voltages below VPFD (min),
the user can be assured the memory will be write
protected within the Write Protect Time (tWPT) provided the VCC fall time does not exceed tF (see Table 6, page 10).
As VCC continues to degrade, the internal switch
disconnects VCC and connects the internal battery
to VOUT. This occurs at the switchover voltage
(VSO ). Below the VSO, the battery provides a voltage VOHB to the SRAM and can supply current
IOUT2 (see Table 5, page 7).
When VCC rises above VSO, VOUT is switched
back to the supply voltage. Output ECON is held inactive for tCER (120ms maximum) after the power
8/19
supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure
11, page 10).
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40SZ100Y/W NVRAM Controller. There are, however some criteria which should
be used in making the final choice of which SRAM
to use. The SRAM must be designed in a way
where the chip enable input disables all other inputs to the SRAM. This allows inputs to the
M40SZ100Y/W and SRAMs to be “Don't care”
once VCC falls below VPFD(min) (see Figure 10,
page 9). The SRAM should also guarantee data
retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system
needs with the chip enable propagation delays included.
If data retention lifetime is a critical parameter for
the system, it is important to review the data retention current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally
at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the
SRAMs can then be added to the ICCDR value of
the M40SZ100Y/W to determine the total current
requirements for data retention. The available battery capacity for the SNAPHAT® of your choice
(see Table 13, page 17) can then be divided by
this current to determine the amount of data retention available.
CAUTION: Take care to avoid inadvertent discharge through VOUT and ECON after battery has
been attached.
For a further more detailed review of lifetime calculations, please see Application Note AN1012.
M40SZ100Y, M40SZ100W
Figure 10. Power Down Timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO
tF
tFB
E
tWPT
VOHB
ECON
RST
PFO
VALID
AI03936
9/19
M40SZ100Y, M40SZ100W
Figure 11. Power Up Timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO
tR
tRB
tCER
E
tEPD
ECON
tEPD
VOHB
tREC
RST
PFO
VALID
AI03937
Table 6. Power Down/Up AC Characteristics
Parameter(1)
Symbol
Min
Max
Unit
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB(3)
VPFD (min) to VSS VCC Fall Time
10
µs
tPFD
PFI to PFO Propagation Delay
15
VPFD(min) to VPFD (max) VCC Rise Time
10
tR
25
µs
µs
M40SZ100Y
10
ns
M40SZ100W
15
ns
tEPD
Chip Enable Propagation Delay (Low or High)
tRB
VSS to VPFD (min) VCC Rise Time
1
tCER
Chip Enable Recovery
40
120
ms
tREC
VPFD (max) to RST High
40
200
ms
tWPT
Write Protect Time
40
200
µs
µs
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V(except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after VCC
passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
10/19
M40SZ100Y, M40SZ100W
Power-on Reset Output
All microprocessors have a reset input which forces them to a known state when starting. The
M40SZ100Y/W has a reset output (RST) pin which
is guaranteed to be low by VPFD (see Table 5,
page 7). This signal is an open drain configuration.
An appropriate pull-up resistor to VCC should be
chosen to control the rise time. This signal will be
valid for all voltage conditions, even when VCC
equals VSS (with valid battery voltage).
Once VCC exceeds the power failure detect voltage VPFD, an internal timer keeps RST low for
tREC to allow the power supply to stabilize.
Reset Input (RSTIN)
The M40SZ100Y/W provides one independent input which can generate an output reset. The duration and function of this reset is identical to a reset
generated by a power cycle. Table 7 and Figure 12
illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH will not generate a
reset condition. RSTIN is internally pulled up to
VCC through a 100kΩ resistor.
Figure 12. RSTIN Timing Waveform
RSTIN
tRLRH
RST
(1)
tR1HRH
AI04768
Note: With pull-up resistor
Table 7. Reset AC Characteristics
Symbol
Parameter(1)
Min
tRLRH(2)
RSTIN Low to RSTIN High
200
tR1HRH(3)
RSTIN High to RST High
40
Max
Unit
ns
200
ms
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. CL = 5pF (see Figure 8, page 6).
11/19
M40SZ100Y, M40SZ100W
Battery Low Pin
The M40SZ100Y/W automatically performs battery voltage monitoring upon power-up, and at factory-programmed time intervals of at least 24
hours. The Battery Low (BL) pin will be asserted if
the battery voltage is found to be less than approximately 2.5V. The BL pin will remain asserted until
completion of battery replacement and subsequent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below
2.5V and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced.
The M40SZ100Y/W only monitors the battery
when a nominal VCC is applied to the device. Thus
applications which require extensive durations in
the battery back-up mode should be powered-up
periodically (at least once every few months) in order for this technique to be beneficial. Additionally,
if a battery low is indicated, data integrity should
be verified upon power-up via a checksum or other
technique. The BL pin is an open drain output and
an appropriate pull-up resistor to VCC should be
chosen to control the rise time.
Power-fail Input/Output
The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from the
VPFD comparator). If PFI is less than the power-fail
threshold (VPFI), the Power-Fail Output (PFO) will
go low. This function is intended for use as an under-voltage detector to signal a failing power supply. Typically PFI is connected through an external
voltage divider (see Figure 7, page 5) to either the
unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI
falls below VPFI several milliseconds before the
regulated VCC input to the M40SZ100Y/W or the
microprocessor drops below the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This oc-
12/19
curs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of VPFI
for the write protect time (tREC), which is the time
from VPFD (max) until the inputs are recognized. At
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to VSS and PFO
left unconnected.
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to
VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
Figure 13. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI00622
M40SZ100Y, M40SZ100W
PACKAGE MECHANICAL INFORMATION
Figure 14. SO16 – 16-lead Plastic Small Package Outline
A
A2
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 8. SO16 – 16-lead Plastic Small Plastic Package Mechanical Data
mm
inches
Symbol
Typ.
Min.
A
Max.
Typ.
Min.
1.75
A1
0.10
A2
Max.
0.069
0.25
0.004
1.60
0.010
0.063
B
0.35
0.46
0.014
0.018
C
0.19
0.25
0.007
0.010
D
9.80
10.00
0.386
0.394
E
3.80
4.00
0.150
0.158
–
–
–
–
H
5.80
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
a
0°
8°
0°
8°
N
16
e
CP
1.27
0.050
16
0.10
0.004
13/19
M40SZ100Y, M40SZ100W
Figure 15. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 9. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
inches
Symbol
Typ
Min
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
CP
14/19
Max
1.27
0.050
28
0.10
0.004
M40SZ100Y, M40SZ100W
Figure 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline
A1
A2
A
eA
A3
B
L
eB
D
E
SHZP-A
Note: Drawing is not to scale.
Table 10. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
mm
inches
Symbol
Typ
Min
A
Max
Typ
Min
9.78
Max
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
15/19
M40SZ100Y, M40SZ100W
Figure 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline
A1
A2
A
eA
A3
B
L
eB
D
E
SHZP-A
Note: Drawing is not to scale.
Table 11. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
mm
inches
Symbol
Typ
Min
A
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
A3
16/19
Max
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
M40SZ100Y, M40SZ100W
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M40SZ
100Y
MQ
6
TR
Device Type
M40SZ
Supply Voltage and Write Protect Voltage
100Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
100W = VCC = 2.7 to 3.6V; VPFD = 2.6 to 2.7V
Package
MQ = SO16
MH(1,2) = SOH28
Temperature Range
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT ®) which is ordered separately under the part number
“M4ZXX-BR00SHX” in plastic tube or “M4ZXX-BR00SHXTR” in Tape & Reel form.
2. Contact Local Sales Office
Caution: Do not place the SNAPHAT battery package “M4Zxx-BR00SH” in conductive foam as it will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 13. SNAPHAT® Battery Table
Part Number
Description
Package
M4Z28-BR00SH
SNAPHAT Housing for 48mAh Battery
SH
M4Z32-BR00SH
SNAPHAT Housing for 120mAh Battery
SH
17/19
M40SZ100Y, M40SZ100W
REVISION HISTORY
Table 14. Document Revision History
Date
Rev. #
December 2001
1.0
First Issue
13-May-02
1.1
Modify reflow time and temperature footnote (Table 2)
01-Aug-02
1.2
Add marketing status (Figure 2; Table 12)
15-Sep-03
1.3
Remove reference to M68xxx (obsolete) part (Figure 7); update disclaimer
18/19
Revision Details
M40SZ100Y, M40SZ100W
M40SZ100, M40SZ100Y, M40SZ100W, 40SZ100, 40SZ100Y, 40SZ100W, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER,
ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, I2C, I2C, I2C,
I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C,
I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, RTC, RTC, RTC, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator,
Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator,
Oscillator, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor,
LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM,
LPSRAM, LPSRAM, LPSRAM, LPSRAM, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI,
PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFO, PFO, PFO, PFO, PFO,
PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write
Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect,
Write Protect, Write Protect, Write Protect, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover,
Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Power-fail, Power-fail, Power-fail,
Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC,
SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,
5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V,
3V, 3V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
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19/19
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