CS44L11
Low Voltage Class-D PWM Headphone Amplifier
Features
Description
Up to 95 dB Dynamic Range
The CS44L11 is a complete stereo digital-to-PWM
Class-D audio amplifier system controller including interpolation, volume control, and a headphone amplifier
in a 16-pin TSSOP package.
1.8 V to 2.4 V Analog and Digital Supplies
Sample Rates up to 96 kHz
Digital Tone Control
–
–
3 Selectable HPF and LPF Corner
Frequencies
12 dB Boost for Bass and Treble - 1 dB step
size
Programmable Digital Volume Control
–
+18 to -96 dB in 1 dB steps
Peak Signal Soft Limiting
De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz
Selectable Outputs for Each Channel, including
–
–
The CS44L11 architecture uses a direct-to-digital approach that maintains digital signal integrity to the final
output filter. This minimizes analog interference effects
that can negatively affect system performance.
The CS44L11 contains on-chip digital bass and treble
boost, peak signal limiting, and de-emphasis. The PWM
amplifier can achieve greater than 90% efficiency. This
efficiency leads to longer battery life for portable systems, smaller device package, less heat sink
requirements, and smaller power supplies.
The CS44L11 is ideal for portable audio, headphone
amplifiers, and mobile phones.
Channel A: R, L, mono (L + R) / 2, mute
Channel B: R, L, mono (L + R) / 2, mute
PWM PopGuard®
ORDERING INFORMATION
CS44L11-CZZ, Lead Free -10 to 70 °C 16-pin TSSOP
23 mW/Channel into 16 Ω @ 2.4 V
SCL/DIF0
SDA/DEM
VA_HPA
Control Port
Digital Volume
Control,
Bass/Treble
Boost,
Compression
Limiting,
De-emphasis
SDIN
SCLK
Serial
Audio
Port
LRCK
Preliminary Product Information
http://www.cirrus.com
PWM
Conversion
Multibit ∆Σ
Modulator with
Correction
PWM
Conversion
Level
Shifter
HP_A
GND_HPA
Interpolation
VA_HPB
Input Sampling Rate
LRCLK/MCLK Ratio
RST
Multibit ∆Σ
Modulator with
Correction
MCLK
Level
Shifter
HP_B
GND_HPB
VD
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
JULY '05
DS640PP4
CS44L11
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4
PERFORMANCE SPECIFICATIONS.................................................................................................... 5
SWITCHING CHARACTERISTICS ....................................................................................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................... 9
2. TYPICAL CONNECTION DIAGRAMS ................................................................................................ 10
3. REGISTER QUICK REFERENCE
................................................................................................... 12
4. REGISTER DESCRIPTIONS ............................................................................................................... 13
4.1 Power and Muting Control (address 02h) ..................................................................................... 13
4.1.1 Soft Ramp and Zero Cross Control (SZC) ....................................................................... 13
4.1.2 Power Down (PDN) ......................................................................................................... 13
4.1.3 Float Output (FLT) .......................................................................................................... 13
4.1.4 Ramp-Up Bypass (RUPBYP) ........................................................................................... 14
4.1.5 Ramp-Down Bypass (RDNBYP) ...................................................................................... 14
4.2 Channel A Volume Control (address 03h) (VOLA) ....................................................................... 14
4.3 Channel B Volume Control (address 04h) (VOLB) ....................................................................... 14
4.4 Tone Control (address 05h) .......................................................................................................... 15
4.4.1 Bass Boost Level (BB) ..................................................................................................... 15
4.4.2 Treble Boost Level (TB) ................................................................................................... 15
4.5 Mode Control 1 (address 06h) ...................................................................................................... 15
4.5.1 Bass Boost Corner Frequency (BBCF) ............................................................................ 16
4.5.2 Treble Boost Corner Frequency (TBCF) .......................................................................... 16
4.5.3 Tone Control Mode (TC) .................................................................................................. 17
4.5.4 Tone Control Enable (TC_EN) ........................................................................................ 17
4.5.5 Peak Signal Limiter Enable (LIM_EN) ............................................................................. 17
4.6 Limiter Attack Rate (address 07h) (ARATE) ................................................................................. 18
4.7 Limiter Release Rate (address 08h) (RRATE) ........................................................................ 18
4.8 Volume and Mixing Control (address 09h) ................................................................................... 19
4.8.1 Ramp Speed (RMP_SP) .................................................................................................. 19
4.8.2 ATAPI Channel Mixing and Muting (ATAPI) .................................................................... 19
4.9 Mode Control 2 (address 0Ah) ..................................................................................................... 20
4.9.1 Master Clock Divide Enable (MCLKDIV) ......................................................................... 20
4.9.2 Clock Divide (CLKDIV) ..................................................................................................... 20
4.9.3 Double-Speed Mode (DBS) ............................................................................................. 21
4.9.4 Frequency Shift (FRQSFT) .............................................................................................. 21
4.9.5 De-Emphasis Control (DEM) .......................................................................................... 22
4.10 Mode Control 3 (address 0Bh) ................................................................................................... 23
4.10.1 Digital Interface Formats (DIF) ....................................................................................... 23
4.10.2 Channel A Volume = Channel B Volume (A=B) ............................................................. 23
4.10.3 Volume Control Bypass (VCBYP) .................................................................................. 23
4.10.4 Control Port Enable (CP_EN) ........................................................................................ 23
4.10.5 Freeze (FREEZE) .......................................................................................................... 24
4.11 Revision Indicator (address 0Ch)[Read Only] ........................................................................... 24
5. PIN DESCRIPTION .............................................................................................................................. 25
6. APPLICATIONS ................................................................................................................................. 26
6.1 Grounding and Power Supply Decoupling .................................................................................... 26
6.2 Clock Modes ................................................................................................................................. 26
6.3 De-Emphasis ................................................................................................................................ 26
6.4 PWM PopGuard Transient Control ............................................................................................... 26
6.5 Recommended Power-Up Sequence ........................................................................................... 27
6.5.1 Stand-Alone Mode ........................................................................................................... 27
6.5.2 Control Port Mode ............................................................................................................ 27
7. CONTROL PORT INTERFACE ........................................................................................................... 28
2
DS640PP4
CS44L11
7.1 I²C Format .................................................................................................................................... 28
7.1.1 Writing in I²C Format ........................................................................................................ 28
7.1.2 Reading in I²C Format ...................................................................................................... 28
7.2 Memory Address Pointer (MAP) ................................................................................................. 28
7.2.1 INCR (Auto Map Increment Enable) ................................................................................ 28
7.2.2 MAP3-0 (Memory Address Pointer) ................................................................................. 29
8. PARAMETER DEFINITIONS ............................................................................................................... 32
9. REFERENCES ..................................................................................................................................... 32
10. PACKAGE DIMENSIONS ................................................................................................................. 33
11. REVISION HISTORY ......................................................................................................................... 34
LIST OF FIGURES
Figure 1. Serial Audio Data Interface Timing ............................................................................................... 8
Figure 2. Control Port Timing - I²C Format................................................................................................... 9
Figure 3. Typical CS44L11 Connection Diagram Stand-Alone Mode ........................................................ 10
Figure 4. Typical CS44L11 Connection Diagram Control Port Mode......................................................... 11
Figure 5. Dynamics Control Block Diagram ............................................................................................... 20
Figure 6. De-Emphasis Curve.................................................................................................................... 22
Figure 7. Control Port Timing, I²C Format.................................................................................................. 29
Figure 8. Single-Speed Stopband Rejection .............................................................................................. 29
Figure 9. Single-Speed Transition Band .................................................................................................... 29
Figure 10. Single-Speed Transition Band (Detail)...................................................................................... 29
Figure 11. Single-Speed Passband Ripple ................................................................................................ 29
Figure 12. Double-Speed Stopband Rejection........................................................................................... 30
Figure 13. Double-Speed Transition Band................................................................................................. 30
Figure 14. Double-Speed Transition Band (Detail) .................................................................................... 30
Figure 15. Double-Speed Passband Ripple............................................................................................... 30
Figure 16. Left-Justified, up to 24-Bit Data................................................................................................. 31
Figure 17. Right-Justified, 24-Bit Data ....................................................................................................... 31
Figure 18. I²S, Up to 24-Bit Data................................................................................................................ 31
Figure 19. Right-Justified, 16-Bit Data ....................................................................................................... 31
LIST OF TABLES
Table 1. Register Quick Reference ............................................................................................................ 12
Table 2. Example Volume Settings ............................................................................................................ 14
Table 3. Example Bass Boost Settings ...................................................................................................... 15
Table 4. Example Treble Boost Settings.................................................................................................... 15
Table 5. Base Boost Corner Frequencies in Single-Speed Mode.............................................................. 16
Table 6. Base Boost Corner Frequencies in Double-Speed Mode ............................................................ 16
Table 7. Treble Boost Corner Frequencies in Single-Speed Mode............................................................ 16
Table 8. Example Limiter Attack Rate Settings.......................................................................................... 18
Table 9. Example Limiter Release Rate Settings....................................................................................... 18
Table 10. ATAPI Decode ........................................................................................................................... 19
Table 11. Single-Speed Clock Modes - Control Port Mode ....................................................................... 21
Table 12. Single-Speed Clock Modes - Stand-Alone Mode....................................................................... 21
Table 13. Double-Speed Clock Modes - Control Port Mode ...................................................................... 22
Table 14. Digital Interface Format (Stand-Alone Mode)............................................................................. 25
Table 15. Revision History ......................................................................................................................... 34
DS640PP4
3
CS44L11
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and
TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V)
Parameters
DC Power Supplies:
Headphone
Digital
Ambient Temperature
Symbol
VA_HPx
VD
TA
Min
1.7
1.7
-10
Typ
-
Max
2.5
2.5
70
Units
V
V
°C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the
device. Normal operation is not guaranteed at these extremes.)
Parameters
DC Power Supplies:
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
4
Headphone
Digital
Symbol
VA_HPx
VD
Iin
VIND
TA
Tstg
Min
-0.3
-0.3
-0.3
-55
-65
Max
3.0
3.0
±10
VD + 0.4
125
150
Units
V
V
mA
V
°C
°C
DS640PP4
CS44L11
PERFORMANCE SPECIFICATIONS
(Full-Scale Output Sine Wave, 997 Hz, MCLK = 12.288 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless
otherwise specified; Fs for Single-Speed Mode = 48 kHz, SCLK = 3.072 MHz; Fs for Double-Speed Mode =
96 kHz, SCLK = 6.144 MHz. Test load RL= 16 Ω, CL = 10 pF. Performance results are measured in production
using a 4700 µF capacitor on the VA_HPx pins. Results will be degraded if smaller value capacitors are used.)
Parameter
Symbol
Min
Typ
Max
Unit
90
88
88
86
95
93
93
91
-
dB
dB
dB
dB
-
-60
-73
-33
-55
-
dB
dB
dB
-
TBD
-
dB
87
85
85
83
92
90
90
88
-
dB
dB
dB
dB
-
-55
-70
-30
-50
-
dB
dB
dB
-
60
-
dB
Full-Scale Headphone Output Voltage
-
0.75 x
VA_HP
-
Vpp
Headphone Output Quiescent Voltage
-
0.5 x
VA_HP
-
VDC
Interchannel Gain Mismatch
-
0.1
-
dB
-
-
85
%
-
38
28
-
mA
mA
Headphone Output Dynamic Performance for VD = VA_HPx = 2.4 V
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
A-Weighted
UnWeighted
A-Weighted
Unweighted
0 dBFS
-20 dBFS
-60 dBFS
Interchannel Isolation
THD+N
(1 kHz)
Headphone Output Dynamic Performance for VD = VA_HPx = 1.8 V
Dynamic Range
18 to 24-Bit
16-Bit
A-Weighted
UnWeighted
A-Weighted
Unweighted
Total Harmonic Distortion + Noise
0 dB
-20 dB
-60 dB
Interchannel Isolation
(1 kHz)
THD+N
PWM Headphone Output
Modulation Index
Maximum Headphone Output
RMS AC-Current
VA_HPx=2.4 V
VA_HPx=1.8 V
IHP
Single-Speed Mode
Parameter
Symbol
Double-Speed Mode
Min
Typ
Max
Min
Typ
Max
Unit
0
0
-
.4535
.4998
0
0
-
.4426
.4984
Fs
Fs
Fs
-.02
-
+.08
0
-
+0.11
dB
.5465
-
-
.577
-
-
Fs
50
-
-
55
-
-
dB
-
9/Fs
-
-
4/Fs
-
s
Digital Filter Response (Note 1))
Passband
(Note 2)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
(Note 3)
StopBand
StopBand Attenuation
Group Delay
DS640PP4
(Note 4)
tgd
5
CS44L11
Single-Speed Mode
Parameter
Passband Group Delay Deviation
De-emphasis Error
(Relative to 1 kHz)
Symbol
Double-Speed Mode
Min
Typ
Max
Min
Typ
Max
Unit
0 - 40 kHz
0 - 20 kHz
-
±0.36/Fs
-
-
±1.39/Fs
±0.23/Fs
-
s
s
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
+.2/-.1
+.05/-.14
+0/-.22
(Note 5)
dB
dB
dB
Notes:
1. Filter response is not tested but is guaranteed by design.
2. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 8-15) have been
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
3. Referenced to a 1 kHz, full-scale sine wave.
4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
5. De-emphasis is not available in Double-Speed Mode.
6
DS640PP4
CS44L11
DIGITAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol
VIH
VIL
Iin
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Input Capacitance
Min
0.7 x VD
-
Typ
8
Max
0.3 x VD
±10
-
Units
V
V
µA
pF
POWER AND THERMAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V. HP_x outputs unloaded.)
Parameters
Symbol
Min
Typ
Max
Units
VD = VA_HPx = 2.4 V
VD = VA_HPx = 1.8 V
-
380
110
-
µA
µA
Power Supply Current
VD = VA_HPx = 2.4 V
VD = VA_HPx = 1.8 V
Total Power DissipationNormal Operation (Note 6)
VD = VA_HPx = 2.4 V
VD = VA_HPx = 1.8 V
-
14
9
34
16
-
mA
mA
mW
mW
-
23
13
0
75
-
mW
mW
dB
°C/Watt
Power Down (Note 6)
Power Supply Current
Normal Operation (Note 7)
Maximum Headphone Power Output
(1 kHz full-scale sine wave
into 16 Ω load)
VA_HPx = 2.4 V
VA_HPx = 1.8 V
Power Supply Rejection Ratio
Package Thermal Resistance
PSRR
θJA
Notes:
6. Power Down Mode is defined as RST = LOW with all clocks and data lines held static.
7. Normal operation is defined as RST = HI.
DS640PP4
7
CS44L11
SWITCHING CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Input Sample Rate
Single-Speed Mode
Double-Speed Mode
Symbol
Fs
Fs
Single-Speed Mode
tsclkl
tsclkh
tsclkw
Double-Speed Mode
tsclkw
MCLK Duty Cycle
LRCK Duty Cycle
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
SCLK rising to LRCK edge delay
Min
8
50
40
40
20
20
1
---------------------( 128 )Fs
1
------------------( 64 )Fs
tslrd
tslrs
tsdlrs
tsdh
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
20
20
20
20
Typ
50
50
-
Max
50
100
60
60
-
Units
kHz
kHz
%
%
ns
ns
ns
-
-
ns
-
-
ns
ns
ns
ns
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sclkw
t sdlrs
t sdh
SDI N
Figure 1. Serial Audio Data Interface Timing
8
DS640PP4
CS44L11
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(GND = 0 V; all voltages with respect to 0 V.)
Symbol
Min
Max
Unit
SCL Clock Frequency
Parameter
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trc
-
1
µs
Fall Time SCL and SDA
tfc, tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
tack
-
(Note 10)
ns
Setup Time for Repeated Start Condition
(Note 8)
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
(Note 9)
Acknowledge Delay from SCL Falling
Notes:
8. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
9. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
10.
5
--------------------256 × Fs
for Single-Speed Mode and
5
--------------------128 × Fs
for Double-Speed Mode.
RST
t
irs
Stop
R e p e ate d
Sta rt
Start
t rd
t fd
Stop
SDA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t ack
t sust
t rc
Figure 2. Control Port Timing - I²C Format
DS640PP4
9
CS44L11
2. TYPICAL CONNECTION DIAGRAMS
1.8 to 2.4 V
Supply
+
1.0µF
100µF
0.1µF
Low ESR
Tantalum
12
VA_HPA
7
1.8 to 2.4 V
Supply
5
1.0µF +
13
VA_H PB
VD
VD
0.1µF
CS44L11
4
HP_A
MCLK
Digital
Audio
Source
3
2
1
9
Mode
Control
16
8
11
0.22
µF
SCLK
LRCK
HP_B 14
SDIN
220 µF
+
100 µH
100 µH
16 Ω
Headphones
+
0.22
220 µF
µF
DEM
RST
DIF0
GND
10
GND
GND
15
6
* Filter component values shown are for a 16 Ω load. Please see the CDB44L11 datasheet for information
on how to calculate filter values for other loads.
Figure 3. Typical CS44L11 Connection Diagram Stand-Alone Mode
10
DS640PP4
CS44L11
.8 to 2.4 V
Supply
+
1.0µF
100µF
0.1µF
Low ESR
Tantalum
12
VA_HPA
7
1.8 to 2.4 V
Supply
5
1.0µF +
13
VA_H PB
VD
VD
0.1µF
CS44L11
4
HP_A
MCLK
Digital
Audio
Source
3
2
1
11
0.22
µF
SCLK
LRCK
HP_B 14
SDIN
1.8 to 2.4 V
Supply
220 µF
+
100 µH
100 µH
16 Ω
Headphones
+
0.22
220 µF
µF
Rpullup
9
Control
Logic
SDA
8
SCL
16
RST
GND
10
GND
GND
15
6
* Filter component values shown are for a 16 Ω load. Please see the CDB44L11 datasheet for information on how to calculate filter values for other loads.
Figure 4. Typical CS44L11 Connection Diagram Control Port Mode
DS640PP4
11
CS44L11
3. REGISTER QUICK REFERENCE
Addr
Function
2h
Power and Muting
Control
3h
Channel A
Volume Control
4h
Channel B
Volume Control
5h
Tone Control
default
default
default
default
6h
Mode Control 1
7h
Limiter Attack Rate
default
default
8h
Limiter Release Rate
9h
Volume and Mixing
Control
default
default
Ah
Mode Control2
Bh
Mode Control 3
6
5
4
SZC0
PDN
FLT
default
Revision Indicator
default
3
2
1
0
RUPBYP RDNBYP Reserved Reserved
1
0
1
0
0
0
0
0
VOLA7
VOLA6
VOLA5
VOLA4
VOLA3
VOLA2
VOLA1
VOLA0
0
0
0
0
0
0
0
0
VOLB7
VOLB6
VOLB5
VOLB4
VOLB3
VOLB2
VOLB1
VOLB0
0
0
0
0
0
0
0
0
BB3
BB2
BB1
BB0
TB3
TB2
TB1
TB0
0
0
0
0
0
0
0
0
BBCF1
BBCF0
TBCF1
TBCF0
TC1
TC0
TC_EN
LIM_EN
0
0
0
0
0
0
0
0
ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0
0
0
0
1
0
0
0
0
RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0
0
0
1
0
Reserved Reserved RMP_SP RMP_SP
1
0
0
mclkdiv
default
Ch
7
SZC1
0
0
CLKDV1 CLKDV0
0
0
0
0
ATAPI3
ATAPI2
ATAPI1
ATAPI0
1
0
0
1
DEM1
DEM0
0
0
1
DBS
FRQSFT FRQSFT
1
0
0
0
0
0
0
DIF1
DIF0
A=B
VCBYP
CP_EN
0
0
0
0
0
0
0
0
REV3
REV2
REV1
REV0
Read
Only
Read
Only
Read
Only
Read
Only
Reserved Reserved Reserved Reserved
0
0
0
0
0
FREEZE Reserved Reserved
Table 1. Register Quick Reference
12
DS640PP4
CS44L11
4. REGISTER DESCRIPTIONS
4.1
Power and Muting Control (address 02h)
7
SZC1
1
4.1.1
6
SZC0
0
5
PDN
1
4
FLT
0
3
RUPBYP
0
2
RDNBYP
0
1
Reserved
0
0
Reserved
0
Soft Ramp and Zero Cross Control (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross Control
10 - Ramped Control
11 - Reserved
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross Control
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
time-out period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.
Ramped Control
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Note:
4.1.2
Ramped Control is not available in Double-Speed Mode.
Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port Mode can occur.
4.1.3
Float Output (FLT)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will cause the headphone output of the CS44L11 to float when in the power down
state (PDN=1). The float function can be used in single-ended applications to maintain the charge on the
DS640PP4
13
CS44L11
DC-blocking capacitor during power transients. On power transitions, the output will quickly change to the
bias point; however, if the DC-blocking capacitor still has a full charge, as in short power cycles, the transition will be very small, often inaudible. Refer to Section 6.4.
4.1.4
Ramp-Up Bypass (RUPBYP)
Default = 0
0 - Normal
1 - Bypass
Function:
When in normal mode, the duty cycle of the output PWM signal is increased at a rate determined by the
Ramp Speed variable (RMP_SPx). Normal mode is used in Single-Ended applications to reduce pops in
the output caused by the DC-blocking capacitor. When the ramp-up function is bypassed in Single-Ended
applications, there will be an abrupt change in the output signal. Refer to Section 6.4.
4.1.5
Ramp-Down Bypass (RDNBYP)
Default = 0
0 - Disabled
1 - Enabled
Function:
When in normal mode, the duty cycle of the output PWM signal is decreased at a rate determined by the
Ramp Speed variable (RMP_SPx). Normal mode is used in Single-Ended applications to reduce pops in
the output caused by the DC-blocking capacitor and changes in bias conditions. When the ramp-down
function is bypassed in Single-Ended applications, there will be an abrupt change in the output signal.
Refer to Section 6.4.
4.2
Channel A Volume Control (address 03h) (VOLA)
4.3
Channel B Volume Control (address 04h) (VOLB)
7
VOLx7
0
6
VOLx6
0
5
VOLx5
0
4
VOLx4
0
3
VOLx3
0
2
VOLx2
0
1
VOLx1
0
0
VOLx0
0
Default = 0 dB (No attenuation)
Function:
The Volume Control registers allow independent control of the signal levels in 1 dB increments from +18 to
-96 dB. Volume settings are decoded using a 2’s complement code, as shown in Table 2. The volume
changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -96 dB
are equivalent to muting the channel via the ATAPI bits (see Section 4.8.2).
Note:
All volume settings greater than +18 dB are interpreted as +18 dB.
Binary Code
Decimal Value
Volume Setting
00001100
12
+12 dB
00000111
7
+7 dB
00000000
0
0 dB
11000100
-60
-60 dB
10100110
-90
-90 dB
Table 2. Example Volume Settings
14
DS640PP4
CS44L11
4.4
Tone Control (address 05h)
7
BB3
0
4.4.1
6
BB2
0
5
BB1
0
4
BB0
0
3
TB3
0
2
TB2
0
1
TB1
0
0
TB0
0
Bass Boost Level (BB)
Default = 0 dB (No Bass Boost)
Function:
The level of the shelving Bass Boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 3. Levels above
+12 dB are interpreted as +12 dB.
Binary Code
Decimal Value
Boost Setting
0000 0000
0
0 dB
0000 0010
2
+2 dB
0000 0110
6
+6 dB
0000 1001
9
+9 dB
0000 1100
12
+12 dB
Table 3. Example Bass Boost Settings
4.4.2
Treble Boost Level (TB)
Default = 0 dB (No Treble Boost)
Function:
The level of the shelving Treble Boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 4. Levels above
+12 dB are interpreted as +12 dB.
Note:
Treble Boost is not available in Double-Speed Mode.
Binary Code
0000 0000
0000 0010
0000 0110
0000 1001
0000 1100
Decimal Value
0
2
6
9
12
Boost Setting
0 dB
+2 dB
+6 dB
+9 dB
+12 dB
Table 4. Example Treble Boost Settings
4.5
Mode Control 1 (address 06h)
7
BBCF1
0
DS640PP4
6
BBCF0
0
5
TBCF1
0
4
TBCF0
0
3
TC1
0
2
TC0
0
1
TC_EN
0
0
LIM_EN
0
15
CS44L11
4.5.1
Bass Boost Corner Frequency (BBCF)
Default = 00
00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - Reserved
Function:
The Bass Boost corner frequency is user-selectable. The corner frequency is a function of LRCK (sampling frequency), the DBS bit and the BBCF bits as shown in Table 5 and Table 6.
BBCF
48 kHz
Fs
00
01
10
11
LRCK in Single-Speed Mode (DBS=0)
24 kHz
12 kHz
8 kHz
50 Hz
100 Hz
200 Hz
Reserved
25 Hz
50 Hz
100 Hz
Reserved
12.5 Hz
25 Hz
50 Hz
Reserved
8.33 Hz
16.7 Hz
33.3 Hz
Reserved
Table 5. Base Boost Corner Frequencies in Single-Speed Mode
BBCF
Fs
00
01
10
11
LRCK in Double-Speed Mode (DBS=1)
96 kHz
48 kHz
24 kHz
16 kHz
50 Hz
25 Hz
12.5 Hz
8.33 Hz
100 Hz
50 Hz
25 Hz
16.7 Hz
200 Hz
100 Hz
50 Hz
33.3 Hz
Reserved
Reserved
Reserved
Reserved
Table 6. Base Boost Corner Frequencies in Double-Speed Mode
4.5.2
Treble Boost Corner Frequency (TBCF)
Default = 00
00 - 2 kHz
01 - 4 kHz
10 - 7 kHz
11 - Reserved
Function:
The Treble Boost corner frequency is user selectable. The corner frequency is a function of LRCK (sampling frequency) and the TBCF bits as shown in Table 7.
Note:
Treble Boost is not available in Double-Speed Mode.
TBCF
Fs
00
01
10
11
LRCK in Single-Speed Mode (DBS=0)
48 kHz
24 kHz
12 kHz
8 kHz
2 kHz
1 kHz
0.5 kHz
0.33 kHz
4 kHz
2 kHz
1 kHz
0.67 kHz
7 kHz
3.5 kHz
1.75 kHz
1.17 kHz
Reserved
Reserved
Reserved
Reserved
Table 7. Treble Boost Corner Frequencies in Single-Speed Mode
16
DS640PP4
CS44L11
4.5.3
Tone Control Mode (TC)
Default = 00
00 - All settings are taken from user registers
01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
Function:
The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured.
The user-defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used
when these bits are set to ‘00’. Alternately, one of three pre-defined settings may be used (these settings
are a function of LRCK - refer to Tables 5, 6, and 7).
Note:
4.5.4
Treble Boost is not available in Double-Speed Mode.
Tone Control Enable (TC_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass Boost and Treble Boost features are active when this function is enabled.
4.5.5
Peak Signal Limiter Enable (LIM_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS44L11 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is
still clipping, the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate
register.
Once the signal has dropped below the clipping level, the attenuation is decreased back to the user-selected level, followed by the Bass Boost being increased back to the user-selected level. The release rate
is determined by the Limiter Release Rate register.
Note:
DS640PP4
The A=B bit should be set to ‘1’ for optimal limiter performance.
17
CS44L11
4.6
Limiter Attack Rate (address 07h) (ARATE)
7
ARATE7
0
6
ARATE6
0
5
ARATE5
0
4
ARATE4
1
3
ARATE3
0
2
ARATE2
0
1
ARATE1
0
0
ARATE0
0
Default = 10h - 2 LRCK’s per 1/8 dB
Function:
The limiter attack rate is user-selectable. The rate is a function of sampling frequency, Fs, and the value in
the Limiter Attack Rate register. Rates are calculated using the function RATE = 32/{value}, where {value}
is the decimal value in the Limiter Attack Rate register and RATE is in LRCK’s per 1/8 dB of change.
A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the
LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)").
Binary Code
00000001
00010100
00101000
00111100
01011010
Decimal Value
1
20
40
60
90
LRCK’s per 1/8 dB
32
1.6
0.8
0.53
0.356
Table 8. Example Limiter Attack Rate Settings
4.7
Limiter Release Rate (address 08h) (RRATE)
7
RRATE7
0
6
RRATE6
0
5
RRATE5
1
4
RRATE4
0
3
RRATE3
0
2
RRATE2
0
1
RRATE1
0
0
RRATE0
0
Default = 20h - 16 LRCK’s per 1/8 dB
Function:
The limiter release rate is user-selectable. The rate is a function of sampling frequency, Fs, and the value
in the Limiter Release Rate register. Rates are calculated using the function RATE = 512/{value}, where
{value} is the decimal value in the Limiter Release Rate register and RATE is in LRCK’s per 1/8 dB of
change.
Note:
A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)").
Binary Code
00000001
00010100
00101000
00111100
01011010
Decimal Value
1
20
40
60
90
LRCK’s per 1/8 dB
512
25
12
8
5
Table 9. Example Limiter Release Rate Settings
18
DS640PP4
CS44L11
4.8
Volume and Mixing Control (address 09h)
7
Reserved
0
4.8.1
6
Reserved
0
5
RMP_SP1
0
4
RMP_SP0
0
3
ATAPI3
1
2
ATAPI2
0
1
ATAPI1
0
0
ATAPI0
1
Ramp Speed (RMP_SP)
Default = 01
00 - Ramp speed = approximately 0.1 seconds
01 - Ramp speed = approximately 0.2 seconds
10 - Ramp speed = approximately 0.3 seconds
11 - Ramp speed = approximately 0.65 seconds
Function:
This feature is used in Single-Ended applications to reduce pops in the output caused by the DC-blocking
capacitor. When in Control Port Mode, the Ramp Speed sets the time for the PWM signal to linearly ramp
up and down from the bias point (50% PWM duty cycle). Refer to Section 6.4.
4.8.2
ATAPI Channel Mixing and Muting (ATAPI)
Default = 1001 - HP_A = L, HP_B = R (Stereo)
Function:
The CS44L11 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 10 and Figure 5 for additional information.
Note:
All mixing functions occur prior to the digital volume control.
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HP_A
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
[(L+R)/2]
[(L+R)/2]
[(L+R)/2]
[(L+R)/2]
HP_B
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
Table 10. ATAPI Decode
DS640PP4
19
CS44L11
Channel A
Digital
Volume
Control
& Mute
Left Channel
Audio Data
EQ
HP_A
EQ
HP_B
Σ
Channel B
Digital
Volume
Control
& Mute
Right Channel
Audio Data
Figure 5. Dynamics Control Block Diagram
4.9
Mode Control 2 (address 0Ah)
7
6
5
4
3
2
1
0
mclkdiv
0
CLKDV1
0
CLKDV0
0
DBS
0
FRQSFT1
0
FRQSFT0
0
DEM1
0
DEM0
0
4.9.1
Master Clock Divide Enable (MCLKDIV)
Default = 0
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to Tables 11, 12, 13, and Section 6.2.
4.9.2
Clock Divide (CLKDIV)
Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to
Tables 11, 12, 13, and Section 6.2.
20
DS640PP4
CS44L11
4.9.3
Double-Speed Mode (DBS)
Default = 0
0 - Single-Speed
1 - Double-Speed (DBS)
Function:
Single-Speed supports 8 kHz to 50 kHz sample rates and Double-Speed supports 50 kHz to 96 kHz sample rates. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements.
Refer to Tables 11, 12, 13, and Section 6.2.
Note:
4.9.4
De-emphasis, ramp control, and treble control are not available in Double-Speed Mode.
Frequency Shift (FRQSFT)
Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to
Tables 11, 12, 13, and Section 6.2.
DBS = 0
MCLKDIV = 0
DBS = 0
MCLKDIV = 1
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
MCLK/
LRCK
MCLK
(MHz)
48
48
44.1
44.1
32
32
24
24
12
12
256
512
256
512
512
1024
512
1024
1024
2048
12.288
24.576
11.2896
22.5792
16.384
32.768
12.288
24.576
12.288
24.576
512
1024
512
1024
1024
2048
1024
2048
2048
4096
24.576
49.152
22.5792
45.1584
32.768
65.536
24.576
49.152
24.576
49.152
PWM
Switching
Freq.
(kHz)
FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
384
352.8
512
384
384
Table 11. Single-Speed Clock Modes - Control Port Mode
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
48
48
44.1
44.1
32
24
12
256
512
256
512
1024
1024
2048
12.288
24.576
11.2896
22.5792
32.768
24.576
24.576
PWM
Switching
Freq. (kHz)
384
352.8
512
384
Table 12. Single-Speed Clock Modes - Stand-Alone Mode
DS640PP4
21
CS44L11
DBS = 1
MCLKDIV = 0
DBS = 1
MCLKDIV = 1
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
MCLK/
LRCK
MCLK
(MHz)
96
96
88.2
88.2
128
256
128
256
12.288
24.576
11.2896
22.5792
256
512
256
512
24.576
49.152
22.5792
45.1584
PWM
Switching
Freq.
(kHz)
FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
384
352.8
Table 13. Double-Speed Clock Modes - Control Port Mode
4.9.5
De-Emphasis Control (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates (see Figure 6).
Note:
De-emphasis is not available in Double-Speed Mode.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 6. De-Emphasis Curve
22
DS640PP4
CS44L11
4.10
Mode Control 3 (address 0Bh)
7
DIF1
0
6
DIF0
0
5
A=B
0
4
VCBYP
0
3
CP_EN
0
2
FREEZE
0
1
HPSEN
0
0
Reserved
0
4.10.1 Digital Interface Formats (DIF)
Default = 00
00 - I²S
01 - Right Justified, 16 bit
10 - Left Justified
11 - Right Justified, 24 bit
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 16 through 19.
4.10.2 Channel A Volume = Channel B Volume (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The HP_A and HP_B volume levels are independently controlled by the A and the B Channel Volume
Control Bytes when this function is disabled. The volume on both HP_A and HP_B are determined by the
A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.
4.10.3 Volume Control Bypass (VCBYP)
Default = 0
0 - Disabled
1 - Enabled
Function:
The digital volume control section is bypassed when this function is enabled. This disables the digital volume control, muting, bass boost, treble boost, limiting, and ATAPI functions.
4.10.4 Control Port Enable (CP_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. Refer to Section 6.5.2.
DS640PP4
23
CS44L11
4.10.5 Freeze (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes being taking effect until
the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, you will first enable the FREEZE Bit, then make all register changes, then Disable the FREEZE bit.
4.11
Revision Indicator (address 0Ch)[Read Only]
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
REV3
0
2
REV2
0
1
REV1
0
0
REV0
0
Default = none
0001 - Revision A
0010 - Revision B
0011 - Revision C
etc.
Function:
This read-only register indicates the revision level of the device.
24
DS640PP4
CS44L11
5. PIN DESCRIPTION
Serial Data
SDIN
1
16
RST
Reset
Left/Right Clock
LRCK
2
15
GND
Headphone B Ground
Serial Clock
SCLK
3
14
HP_B
Headphone B Output
Master Clock
MCLK
4
13
VA_HPB Headphone B Power
Digital Power
VD
5
12
VA_HPA Headphone A Power
Ground
GND
6
11
HP_A
Headphone A Output
Digital Power
VD
7
10
GND
Headphone A Ground
SCL/DIF0
SCL/DIF0
8
9
SDA/DEM SDA/DEM
SDIN
1
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
LRCK
2
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SCLK
3
Serial Clock (Input) - Serial clock for the serial audio interface.
MCLK
4
Master Clock (Input) - Clock source for the PWM modulator and digital filters. Tables 11, 12, 13 and
14 illustrate several standard audio sample rates and required master clock frequencies.
VD
5
7
GND
HP_A
6, 10 Ground (Input) - Ground Reference.
& 15
11
14
Headphone Outputs (Output) - PWM Headphone Outputs. An external LC filter should be added to
suppress high frequency switching noise. A DC blocking capacitor is also required. Refer to Typical
Connection Diagrams.
12
13
Headphone Amplifier Power (Input) - Positive power supply for the headphone amplifier. Refer to
"Specified Operating Conditions" for appropriate voltages.
16
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low. The control port cannot be accessed when Reset is low. See Section 6.5.
HP_B
VA_HPA
Digital Power (Input) - Positive power supply for the digital section. Refer to "Specified Operating
Conditions" for appropriate voltages.
VA_HPB
RST
Control Port Definitions
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an
SCL
8
external pull-up resistor to VD in I²C mode.
Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up
SDA
9
resistor to the logic interface voltage.
Stand-Alone Definitions
DIF0
8
Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial clock
and serial data is defined by the Digital Interface Format and the options are detailed below
DIF0
DESCRIPTION
0 I²S, up to 24-bit data
1 Right Justified, 16-bit Data
FIGURE
18
19
Table 14. Digital Interface Format (Stand-Alone Mode)
DEM
DS640PP4
9
De-emphasis Control (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response at
44.1 kHz sample rates. NOTE: De-emphasis is not available in Double- or Quad-Speed Modes. When
DEM is grounded, de-emphasis is disabled.
25
CS44L11
6. APPLICATIONS
6.1
Grounding and Power Supply Decoupling
As with any switching converter, the CS44L11 requires careful attention to power supply and grounding arrangements to optimize performance. Figures 3 and 4 show the recommended power arrangement with VD
and VA_HPx connected to clean supplies. Decoupling capacitors should be located as close to the device
package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin.
6.2
Clock Modes
One of the characteristics of a PWM amplifier is that the frequency content of out-of-band noise generated
by the modulator is dependent on the PWM switching frequency. The systems designer will specify the external filter based on this switching frequency. The obvious implementation in a digital PWM system is to
directly lock the PWM switching rate to the incoming data sample rate. However, this would require a tunable filter to attenuate the switching frequency across the range of possible sample rates. To simplify the
external filter design and to accommodate sample rates ranging from 8 kHz to 96 kHz the CS44L11 Controller uses several clock modes that keep the PWM switching frequency in a small range.
In Control Port Mode, for operation at a particular sample rate the user selects register settings (refer to
Section 4.9 and Tables 11 and 13) based on their MCLK and MCLK/LRCK parameters. When using
Stand-Alone mode, refer to Tables Tables 12 and 14 for available clock modes.
6.3
De-Emphasis
The CS44L11 includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve. The frequency
response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis
equalization as a means of noise reduction.
6.4
PWM PopGuard Transient Control
The CS44L11 uses PopGuard® technology to minimize the effects of output transients during power-up and
power-down. This technique minimizes the audio transients commonly produced by a single-ended, single-supply converter when it is implemented with external DC-blocking capacitors connected in series with
the audio outputs.
When the device is initially powered-up, the HP_x outputs are clamped to GND. Following a delay each output begins to increase the PWM duty cycle toward the quiescent voltage point. By a speed set by the
RMP_SP bit, the HP_x outputs will later reach the bias point (50% PWM duty cycle), and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient.
To prevent transients at power-down, the device must first enter its power-down state. When this occurs,
audio output ceases and the PWM duty cycle is decreased until the HP_x outputs reach GND. The time
required to reach GND is determined by the RMP_SP bits. This allows the DC-blocking capacitors to slowly
discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is
ready for the next power-on.
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before
turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur
when the audio outputs are initially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with
26
DS640PP4
CS44L11
a 220 µF capacitor and a 16 Ω load on the headphone outputs, the minimum power-down time will be approximately 0.4 seconds.
Note that ramp-up and ramp-down period can be set to zero with the RUPBYP and RDNBYP bits respectively.
6.5
6.5.1
Recommended Power-Up Sequence
Stand-Alone Mode
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control
port is reset to its default settings and the HP_x lines will remain low.
2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone power-up
sequence. The control port will be accessible at this time.
6.5.2
Control Port Mode
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control
port is reset to its default settings and the HP_x lines will remain low.
2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone power-up
sequence. The control port will be accessible at this time.
3. On the CS44L11 the control port pins are shared with stand-alone configuration pins. To enable the
control port, the user must set the CP_EN bit. This is done by performing an I²C write. Once the
control port is enabled, these pins are dedicated to control port functionality.
To prevent audible artifacts, the CP_EN bit (see Section 4.10.4) should be set prior to the completion of
the Stand-Alone power-up sequence (1024/Fs: approximately 21 ms at Fs=48 kHz). Writing this bit will
halt the Stand-Alone power-up sequence and initialize the control port to its default settings. Note, the
CP_EN bit can be set any time after RST goes high; however, setting this bit after the Stand-Alone power-up sequence has completed can cause audible artifacts.
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CS44L11
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The CS44L11 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB.
If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment
after each byte is written, allowing block reads or writes of successive registers.
7.1
I²C Format
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with a clock to
data relationship as shown in Figure 7. The receiving device should send an acknowledge (ACK) after each
byte received. The chip address is 0010011.
Note:
7.1.1
MCLK is required during all I²C transactions.
Writing in I²C Format
To communicate with the CS44L11, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address
Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be
written. To write multiple registers, continue providing a clock and data, waiting for the CS44L11 to acknowledge between each byte. To end the transaction, send a STOP condition.
7.1.2
Reading in I²C Format
To communicate with the CS44L11, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (high for a read). The contents of the register pointed to
by the MAP will be output after the chip address. To read multiple registers, continue providing a clock
and issue an ACK after each byte. To end the transaction, send a STOP condition.
7.2
Memory Address Pointer (MAP)
7
INCR
0
7.2.1
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
INCR (Auto Map Increment Enable)
Default = ‘0’
0 - Disabled
1 - Enabled
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CS44L11
7.2.2
MAP3-0 (Memory Address Pointer)
Default = ‘0000’
Note 1
SDA
R/W
0010011
ACK
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 7. Control Port Timing, I²C Format
0
-10
-10
-20
-20
-30
-30
Amplitude (dB)
Amplitude (dB)
0
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.4
1
0.42
0.44
0
0.5
-1
0.4
-2
0.3
-3
0.2
-4
-5
-6
0.5
0.52
0.54
0.56
0.58
0.6
0.1
0
-0.1
-7
-0.2
-8
-0.3
-9
-0.4
-10
-0.5
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency (norm alized to Fs)
Figure 10. Single-Speed Transition Band (Detail)
DS640PP4
0.48
Figure 9. Single-Speed Transition Band
Amplitude (dB)
Amplitude (dB)
Figure 8. Single-Speed Stopband Rejection
0.45
0.46
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (norm alized to Fs)
Figure 11. Single-Speed Passband Ripple
29
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dB)
Amplitude (dB)
CS44L11
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0.4
0.42
0.44
Frequency (norm alized to Fs)
Figure 12. Double-Speed Stopband Rejection
0
0. 50
0. 40
-2
0. 30
Amplitude (dB)
-3
0.5
0.52
0.54
0.56
0.58
0.6
0. 20
-4
0. 10
-5
0. 00
-6
-0. 10
-7
-0. 20
-8
-0. 30
-9
-0. 40
-10
-0. 50
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
Frequency (norm alized to Fs)
Figure 14. Double-Speed Transition Band (Detail)
30
0.48
Figure 13. Double-Speed Transition Band
-1
0.45
0.46
Frequency (norm alized to Fs)
0.55
0. 00
0. 05
0. 10
0. 15
0. 20
0. 25
0. 30
0. 35
0. 40
0. 45
0. 50
F re que nc y ( no rm a lize d t o F s )
Figure 15. Double-Speed Passband Ripple
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CS44L11
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 16. Left-Justified, up to 24-Bit Data
LRCK
Right Channel
Left Channel
SCLK
SDATA
0
7 6 5 4 3 2 1 0
23 22 21 20 19 18
23 22 21 20 19 18
7 6 5 4 3 2 1 0
32 clocks
Figure 17. Right-Justified, 24-Bit Data
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 18. I²S, Up to 24-Bit Data
LRCK
Right Channel
Left Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 19. Right-Justified, 16-Bit Data
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CS44L11
8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
9. REFERENCES
“The I²C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
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CS44L11
10.PACKAGE DIMENSIONS
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
SIDE VIEW
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
µ
MIN
-0.002
0.03346
0.00748
0.193
0.248
0.169
-0.020
0°
INCHES
NOM
-0.004
0.0354
0.0096
0.1969
0.2519
0.1732
0.026 BSC
0.024
4°
MAX
0.043
0.006
0.037
0.012
0.201
0.256
0.177
-0.028
8°
MIN
-0.05
0.85
0.19
4.90
6.30
4.30
-0.50
0°
MILLIMETERS
NOM
--0.90
0.245
5.00
6.40
4.40
0.065 BSC
0.60
4°
NOTE
MAX
1.10
0.15
0.95
0.30
5.10
6.50
4.50
-0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters
Notes:
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm
total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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CS44L11
11.REVISION HISTORY
Release
Date
Changes
PP1
April 2004
Initial Preliminary Release
PP2
September
2004
Added Lead-free device ordering information.
PP3
March 2005
-Corrected “Features” on page 1.
-Corrected Table 11, “Single-Speed Clock Modes - Control Port Mode,” on page 21.
-Corrected Table 12, “Single-Speed Clock Modes - Stand-Alone Mode,” on page 21.
-Corrected Table 13, “Double-Speed Clock Modes - Control Port Mode,” on page 22.
PP4
July 2005
Added last two rows to Table 13, “Double-Speed Clock Modes - Control Port Mode,” on
page 22.
Table 15. Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
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DS640PP4