Burr-Brown ADS8509IBDWRG4 16-bit 250-ksps serial cmos sampling analog-to-digital converter Datasheet

 ADS8509
SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
250-kHz Sampling Rate
4-V, 5-V, 10 V, ±3.33-V, ±5-V, and ±10-V Input
Ranges
±2.0 LSB Max INL
±1 LSB Max DNL, 16-Bit No Missing Codes
SPI Compatible Serial Output with
Daisy-Chain (TAG) Feature
Single 5-V Supply
Pin-Compatible With ADS7809 (Low Speed)
and 12-Bit ADS8508/7808
Uses Internal or External Reference
70-mW Typ Power Dissipation at 250 KSPS
20-Pin SO and 28-Pin SSOP Packages
Simple DSP Interface
The ADS8509 is specified at a 250-kHz sampling rate
over the full temperature range. Precision resistors
provide various input ranges including ±10 V and 0 V
to 5 V, while the innovative design allows operation
from a single +5-V supply with power dissipation
under 100 mW.
The ADS8509 is available in 20-pin SO and 28-pin
SSOP packages, both fully specified for operation
over the industrial -40°C to 85°C temperature range.
APPLICATIONS
•
•
•
•
•
The ADS8509 is a complete 16-bit sampling
analog-to-digital (A/D) converter using state-of-the-art
CMOS structures. It contains a complete 16-bit,
capacitor-based, successive approximation register
(SAR) A/D converter with sample-and-hold, reference, clock, and a serial data interface. Data can be
output using the internal clock or can be
synchronized to an external data clock. The ADS8509
also provides an output synchronization pulse for
ease of use with standard DSP processors.
Industrial Process Control
Data Acquisition Systems
Digital Signal Processing
Medical Equipment
Instrumentation
Successive Approximation Register
Clock
CDAC
9.8 kΩ
R1IN
BUSY
4.9 kΩ
R2IN
2.5 kΩ
R3IN
EXT/INT
10 kΩ
Comparator
CAP
Buffer
Internal
+2.5 V Ref
Serial
Data
Out
&
Control
DATACLK
DATA
R/C
SB/BTC
CS
PWRD
4 kΩ
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
ADS8509IB
NO
MISSING
CODE
±2
16
MINIMUM
SINAD
(dB)
85
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
DESIGNATOR
SO-20
DW
-40°C to 85°C
SSOP-28
SO-20
ADS8509I
±3
15
83
DW
-40°C to 85°C
SSOP-28
(1)
DB
DB
ORDERING
NUMBER
ADS8509IBDW
ADS8509IBDWR
ADS8509IBDB
ADS8509IBDBR
ADS8509IDW
ADS8509IDWR
ADS8509IDB
ADS8509IDBR
TRANSPORT
MEDIA, QTY
Tube, 25
Tape and Reel, 2000
Tube, 50
Tape and Reel, 2000
Tube, 25
Tape and Reel, 2000
Tube, 50
Tape and Reel, 2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Analog inputs
R1IN
±25 V
R2IN
±25 V
R3IN
±25 V
REF
+VANA + 0.3 V to AGND2 - 0.3 V
DGND, AGND2
Ground voltage differences
VANA
VDIG to VANA
VDIG
Digital inputs
Maximum junction temperature
Storage temperature range
Internal power dissipation
Lead temperature (soldering, 1.6 mm from case 10 seconds)
(1)
2
All voltage values are with respect to network ground terminal.
±0.3 V
6V
0.3 V
6V
-0.3 V to +VDIG + 0.3 V
165°C
–65°C to 150°C
700 mW
260°C
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS
At TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference and 0.1%, 0.25 W fixed resistors (See
Figure 29 and Figure 30) (unless otherwise specified)
PARAMETER
TEST CONDITIONS
ADS8509I
MIN
TYP
Resolution
ADS8509IB
MAX
MIN
TYP
16
MAX
16
UNIT
Bits
ANALOG INPUT
Voltage ranges (1)
Impedance (1)
Capacitance
50
50
pF
THROUGHPUT SPEED
Conversion cycle
Acquire and convert
Throughput rate
4
250
4
250
µs
kHz
DC ACCURACY
INL
Integral linearity error
-3
3
DNL
Differential linearity error
-2
2
No missing codes
15
Transition noise (3)
Full-scale
error (4) (5)
±10 V range
All other ranges
Full-scale error drift
Full-scale
error (4) (5)
±10 V range
All other ranges
Full-scale error drift
2
LSB (2)
-1
1
LSB
16
1
Int. Ref. with 0.1% external
fixed resistors
Ext. Ref. with 0.1% external
fixed resistors
Bits
1
LSB
-0.5
0.5
-0.5
0.5
-0.5
0.5
-0.5
0.5
-0.5
0.5
-0.5
0.5
-0.5
0.5
-0.5
0.5
10
-5
Int. Ref.
±7
Ext. Ref.
Bipolar zero error (4)
±7
±2
-10
Bipolar zero error drift
Unipolar zero
error (4)
-2
ppm/°C
±2
±0.4
±0.4
5
-5
5
4 V and 5 V
range
-3
3
-3
3
Power supply sensitivity
(VDIG = VANA = VD)
1-µF Capacitor to CAP
+4.75 V < VD < +5.25 V
mV
ppm/°C
-5
Recovery to rated accuracy after
power down
%FSR
ppm/°C
5
10 V range
Unipolar zero error drift
%FSR
mV
±2
±2
ppm/°C
1
1
ms
-8
8
-8
8
LSB
AC ACCURACY
SFDR
Spurious-free dynamic range
fI = 20 kHz
THD
Total harmonic distortion
fI = 20 kHz
SINAD
SNR
Signal-to-(noise+distortion)
Signal-to-noise ratio
fI = 20 kHz
90
-98
83
–60-dB Input
fI = 20 kHz
Full-power bandwidth (7)
99
95
-90
88
-98
85
30
83
88
86
500
dB (6)
99
-93
dB
88
dB
32
dB
88
dB
500
kHz
SAMPLING DYNAMICS
Aperture delay
Transient response
Overvoltage recovery (8)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
5
FS Step
5
2
150
ns
2
150
µs
ns
±10 V, 0 V to 5 V, etc. (see Table 3)
LSB means least significant bit. For the ±10-V input range, one LSB is 305 µV.
Typical rms noise at worst case transitions and temperatures.
As measured with fixed resistors shown in Figure 29 and Figure 30. Adjustable to zero with external potentiometer. Factory calibrated
with 0.1%, 0.25 W resistors.
For bipolar input ranges, full-scale error is the worst case of -full-scale or +full-scale uncalibrated deviation from ideal first and last code
transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input
ranges, full-scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset
error.
All specifications in dB are referred to a full-scale ±10-V input.
Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB.
Recovers to specified performance after 2 x FS input overvoltage.
3
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
At TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference and 0.1%, 0.25 W fixed resistors (See
Figure 29 and Figure 30) (unless otherwise specified)
PARAMETER
TEST CONDITIONS
ADS8509I
ADS8509IB
MIN
TYP
MAX
MIN
TYP
MAX
2.48
2.5
2.52
2.48
2.5
2.52
UNIT
REFERENCE
Internal reference voltage
No load
Internal reference source current
(must use external buffer)
1
1
Internal reference drift
8
8
External reference voltage range
for specified linearity
External reference current drain
2.3
2.5
Ext. 2.5-V Ref.
2.7
2.3
2.5
100
V
µA
ppm/°C
2.7
V
100
µA
V
DIGITAL INPUTS
Logic levels
VIL
Low-level input voltage
-0.3
0.8
-0.3
0.8
VIH
High-level input voltage
2.0
VDIG +0.3 V
2.0
VDIG +0.3 V
V
IIL
Low-level input current
VIL = 0 V
±10
±10
µA
IIH
High-level input current
VIH = 5 V
±10
±10
µA
DIGITAL OUTPUTS
Data format (Serial 16-bits)
Data coding (Binary 2's complement or straight binary)
Pipeline delay (Conversion results only available after completed conversion.)
Data clock (Selectable for
internal or external data clock)
Internal clock (output only when
transmitting data)
EXT/INT Low
External clock (can run continually but not recommended for
optimum performance)
EXT/INT High
VOL
Low-level output voltage
ISINK = 1.6 mA
VOH
High-level output voltage
ISOURCE = 500 µA
Leakage current
Hi-Z state,
VOUT = 0 V to VDIG
Output capacitance
Hi-Z state
9
0.1
9
26
0.1
MHz
26
MHz
0.4
0.4
V
±5
±5
µA
15
15
pF
V
4
4
V
POWER SUPPLIES
VDIG
Digital input voltage
4.75
5
5.25
4.75
5
5.25
VANA
Analog input voltage
4.75
5
5.25
4.75
5
5.25
IDIG
Digital input current
IANA
Analog input current
Must be ≤ VANA
V
4
4
mA
10
10
mA
POWER DISSIPATION
PWRD Low
fS = 250 kHz
70
PWRD High
100
70
50
100
50
mW
µW
TEMPERATURE RANGE
Specified performance
-40
85
-40
85
°C
Derated performance (9)
-55
125
-55
125
°C
Storage
-65
150
-65
150
°C
THERMAL RESISTANCE (ΘJA)
(9)
4
SSOP
62
62
°C/W
SO
46
46
°C/W
The internal reference may not be started correctly beyond the industrial temperature range (-40°C to 85°C), therefore use of an
external reference is recommended.
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
TIMING REQUIREMENTS, TA = –40°C to 85°C
PARAMETER
MIN
TYP
MAX
6
20
ns
2.2
µs
tw1
Pulse duration, convert
td1
Delay time, BUSY from R/C low
tw2
Pulse duration, BUSY low
td2
Delay time, BUSY, after end of conversion
5
td3
Delay time, aperture
5
tconv
Conversion time
tacq
Acquisition time
tconv + tacq
40
UNIT
ns
ns
ns
2.2
1.8
µs
µs
Cycle time
4
µs
td4
Delay time, R/C Low to internal DATACLK output
270
ns
tc1
Cycle time, internal DATACLK
110
ns
td5
Delay time, data valid to internal DATACLK high
15
35
ns
td6
Delay time, data valid after internal DATACLK low
20
35
ns
tc2
Cycle time, external DATACLK
35
ns
tw3
Pulse duration, external DATACLK high
15
ns
tw4
Pulse duration, external DATACLK low
15
tsu1
Setup time, R/C rise/fall to external DATACLK high
15
tsu2
Setup time, R/C transition to CS transition
10
td7
Delay time, SYNC, after external DATACLK high
3
35
ns
td8
Delay time, data valid
2
20
ns
td9
Delay time, CS to rising edge
td10
tsu3
td11
Delay time, final external DATACLK to BUSY falling edge
tsu3
Setup time, TAG valid
0
ns
th1
Hold time, TAG valid
2
ns
ns
tC2 + 5
ns
ns
10
ns
Delay time, previous data available after CS, R/C low
2
µs
Setup time, BUSY transition to first external DATACLK
5
20 VDIG
19 VANA
R1IN 1
AGND1 2
28 VDIG
27 VANA
R2IN 3
R3IN 4
18 PWRD
R2IN 3
26 PWRD
17 BUSY
25 BUSY
CAP 5
16 CS
R3IN 4
NC 5
REF 6
15 R/C
CAP 6
23 NC
AGND2 7
14 TAG
REF 7
22 NC
SB/BTC 8
13 DATA
EXT/INT 9
12 DATACLK
DGND 10
µs
DB PACKAGE
(TOP VIEW)
DW PACKAGE
(TOP VIEW)
R1IN 1
AGND1 2
ns
1
11 SYNC
NC 8
AGND2 9
24 CS
21 R/C
20 NC
NC 10
19 TAG
NC 11
18 NC
SB/BTC 12
EXT/INT 13
DGND 14
17 DATA
16 DATACLK
15 SYNC
5
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
Terminal Functions
TERMINAL
NAME
DESCRIPTION
DB NO.
DW NO.
I/O
AGND1
2
2
–
Analog ground. Used internally as ground reference point. Minimal current flow.
AGND2
9
7
–
Analog ground
BUSY
25
17
O
Busy output. Falls when a conversion is started, and remains low until the conversion is completed
and the data is latched into the output shift register.
CAP
6
5
–
Reference buffer capacitor. 2.2-µF Tantalum to ground.
CS
24
16
–
Chip select. Internally ORed with R/C.
DATA
17
13
O
Serial data output. Data is synchronized to DATACLK, with the format determined by the level of
SB/BTC. In the external clock mode, after 16 bits of data, the ADS8509 outputs the level input on
TAG as long as CS is low and R/C is high (see Figure 8 and Figure 9). If EXT/INT is low, data is
valid on both the rising and falling edges of DATACLK, and between conversions DATA stays at
the level of the TAG input when the conversion was started.
DATACLK
16
12
I/O
Either an input or an output depending on the EXT/INT level. Output data is synchronized to this
clock. If EXT/INT is low, DATACLK transmits 16 pulses after each conversion, and then remains
low between conversions.
DGND
14
10
–
Digital ground
EXT/INT
13
9
–
Selects external or internal clock for transmitting data. If high, data is output synchronized to the
clock input on DATACLK. If low, a convert command initiates the transmission of the data from the
previous conversion, along with 16-clock pulses output on DATACLK.
5, 8, 10,
11, 18,
20, 22,
23
–
–
No connect
PWRD
26
18
I
Power down input. If high, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversion are maintained in the output shift register.
R/C
21
15
I
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the
data results from the previous conversion. If EXT/INT is high, a rising edge on R/C with CS low, or
a falling edge on CS with R/C high, transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
REF
7
6
I/O
R1IN
1
1
I
Analog input. See Table 3 for input range connections.
R2IN
3
3
I
Analog input. See Table 3 for input range connections.
R3IN
4
4
I
Analog input. See Table 3 for input range connections.
SB/BTC
12
8
O
Select straight binary or binary 2's complement data output format. If high, data is output in a
straight binary format. If low, data is output in a binary 2's complement format.
SYNC
15
11
O
Sync output. This pin is used to supply a data synchronization pulse when the EXT level is high
and at least one external clock pulse has occured when not in the read mode. See the external
clock modes desciptions.
TAG
19
14
I
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
on DATA with a delay that is dependent on the external clock mode. See Figure 8 and Figure 9.
VANA
27
19
I
Analog supply input. Nominally +5 V. Connect directly to pin 20, and decouple to ground with
0.1-µF ceramic and 10-µF tantalum capacitors.
VDIG
28
20
I
Digital supply input. Nominally +5 V. Connect directly to pin 19. Must be ≤ VANA.
NC
6
Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2-µF tantalum capacitor.
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
CS
R/C
R/C
CS
tsu1
tsu1
tsu1
External
DATACLK
tsu1
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
R/C Set Low, Discontinuous Ext DATACLK
BUSY
CS
tsu2
tsu2
tsu3
1
External
DATACLK
R/C
2
CS Set Low, Discontinuous Ext DATACLK
Figure 1. Critical Timing
tw1
tw1
R/C
td1
td1
tw2
tw2
BUSY
td2
td3
STATUS
Nth Conversion
Error
Correction
tconv
td4
td2
td11
td3
td11
(N+1)th Accquisition
Error
(N+1)th Conversion Correction
tconv
tacq
tc1
(N+2)th Accquisition
tacq
td4
Internal
1
DATACLK
TAG = 0
16
1
2
16
td6
td5
DATA
2
D15
D0
(N−1)th Conversion Data
CS, EXT/INT, and TAG are tied low
TAG = 0
D15
D0
TAG = 0
Nth Conversion Data
8 starts READ
Figure 2. Basic Conversion Timing - Internal DATACLK (Read Previous Data During Conversion)
7
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION (continued)
tw1
tw1
R/C
td1
td1
tw2
tw2
BUSY
td2
td3
STATUS
Error
Correction
Nth Conversion
td2
td3
td11
td11
(N+1)th Accquisition
(N+1)th Conversion
tacq
tconv
(N+2)th Accquisition
tacq
tconv
tsu3
tsu1
Error
Correction
tsu3
tsu1
External
1
DATACLK
DATA TAG = 0
16
2
1
No more
data to
shift out
TAG = 0
1
16
Nth Data
EXT/INT tied high, CS and TAG are tied low
TAG = 0
16
2
1
No more
data to
shift out
TAG = 0
16
(N+1)th Data
TAG = 0
tw1 + tsu1 starts READ
Figure 3. Basic Conversion Timing - External DATACLK
tw1
R/C
td1
tsu1
tw2
td1
BUSY
td2
td3
STATUS
td3
td11
Nth Conversion
Error
Correction
(N+1) th Accquisition
tsu3
tconv
tacq
tc2
External
DATACLK
tsu1
tw4
tw3
0
1
2
3
4
5
10
11
12
13
14
15
16
SYNC = 0
td8
T00
EXT/INT tied high, CS tied low
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
Null
T00
Txx
T02
T03
T04
T05
T06
T11
T12
T13
T14
T15
T16
Null
T17
Tyy
th1
tsu3
TAG
td8
Nth Conversion Data
D15
DATA
T01
tw1 + tsu1 starts READ
Figure 4. Read After Conversion (Discontinuous External DATACLK)
8
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION (continued)
tw1
R/C
td1
tw2
BUSY
td10
td3
td2
Error
Correction
Nth Conversion
STATUS
tsu3
tconv
tc2
tsu1
External
tw3
td11
tw4
1
0
DATACLK
2
3
4
5
10
11
12
13
14
15
16
SYNC = 0
td8
Nth Conversion Data
D14
D15
DATA
D13
D12
D11
D10
D05
D04
D03
td8
D02
D01
D00
Rising DATACLK change DATA, tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
EXT/INT tied high, CS and TAG tied low
Figure 5. Read During Conversion (Discontinuous External DATACLK)
tw1
R/C
td1
tsu1
td1
tsu1
tw2
BUSY
td2
td3
Error
Nth Conversion Correction
STATUS
td3
td11
(N+1)th Accquisition
tconv
tacq
tc2
tsu3
tsu1
External
DATACLK
0
2
1
tsu1
tw4
tw3
3
4
5
6
7
12
13
14
15
16
17
18
tc2
td7
SYNC =0
td8
Nth Conversion Data
D15
DATA
T00
EXT/INT tied high, CS tied low
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
Null
T02
T03
T04
T05
T06
T11
T12
T13
T14
T15
T16
T17
T00
Txx
th1
tsu3
TAG
td8
D14
T01
Tyy
tw1 + tsu1 starts READ
Figure 6. Read After Conversion With SYNC (Discontinuous External DATACLK)
9
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION (continued)
tw1
R/C
td1
tw2
BUSY
td3
td10
td2
Error
Correction
Nth Conversion
STATUS
tsu3
tconv
tsu1
tsu1
External
tw3
tsu1
0
DATACLK
tc2
tw4
1
2
3
td11
4
5
6
7
12
13
14
15
16
17
18
td7
tc2
SYNC = 0
td8
EXT/INT tied high, CS and TAG tied low
td8
Nth Conversion Data
D15
DATA
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
Figure 7. Read During Conversion With SYNC (Discontinuous External DATACLK)
10
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
Tag 18
Tag 17
Tag 16
Tag 15
Tag 1
TAG
Tag 2
Bit 15 (MSB)
DATA
Tag 0
t c2
t su2
t su1
0
SYNC
BUSY
R/C
CS
External
DATACLK
t w1
t su2
t d1
t w3
t d7
1
t c2
t w4
2
t d8
3
Bit 14
4
Bit 1
17
18
Bit 0 (LSB)
Tag 0
t d9
Tag 1
Tag 19
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Conversion and Read Timing with Continuous External DATACLK (EXT/INT Tied High) Read
After Conversions (Not Recommended)
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ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
Tag 18
Tag 17
Tag 1
TAG
Tag 16
Bit 15 (MSB)
DATA
SYNC
t d1
BUSY
R/C
CS
External
DATACLK
t su2
t w3
t c2
t w1
t w4
t su1
t su1
Tag 0
t c2
t d8
t d10
Bit 0 (LSB)
Tag 0
t d8
Tag 1
Tag 19
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Conversion and Read Timing with Continous External DATACLK (EXT/INT Tied High) Read
Previous Conversion Results During Conversion (Not Recommended)
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ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS
−100
THD − Total Harmonic Distortion − dB
105
100
95
90
85
fs = 250 KSPS,
fi = 20 kHz
80
75
−40
100
SNR − Signal-to-Noise Ratio − dB
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
25
−90
−85
−80
fs = 250 KSPS,
fi = 20 kHz
−75
Figure 10.
Figure 11.
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE AND DISTORTION
vs
FREE-AIR TEMPERATURE
90
85
80
75
70
25
85
100
fs = 250 KSPS,
fi = 20 kHz
95
90
85
80
75
70
−40
TA − Free-Air Temperature − C
25
85
TA − Free-Air Temperature − C
Figure 12.
Figure 13.
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY
SINAD − Signal-To-Noise and Distortion − dB
90
SNR − Signal-to-Noise Ratio − dB
85
TA − Free-Air Temperature − C
95
85
80
75
70
65
1
25
TA − Free-Air Temperature − C
fs = 250 KSPS,
fi = 20 kHz
−40
−95
−70
−40
85
SINAD − Signal-To-Noise and Distortion − dB
SFDR − Spurious Free Dynamic Range − dB
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
10
fi − Input Frequency − kHz
Figure 14.
100
90
85
80
75
70
65
1
10
fi − Input Frequency − kHz
100
Figure 15.
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ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
105
THD − Total Harmonic Distortion − dB
−105
100
95
90
85
80
75
−100
−95
−90
−85
−80
−75
−70
70
1
Internal Reference Voltage − V
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
10
fi − Input Frequency − kHz
1
100
100
Figure 16.
Figure 17.
INTERNAL REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
BIPOLAR ZERO SCALE ERROR
vs
FREE-AIR TEMPERATURE
2.510
5
2.508
4
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2
1
0
−1
−2
−3
25
45
65
85
−5
−40 −25 −10
105
TA − Free-Air Temperature − C
20
35
50
65
Figure 18.
Figure 19.
FULL SCALE ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
80
20
External Reference,
±10 V Range
for 5 Representative
Parts
19
18
Supply Current − mA
0.10
5
TA − Free-Air Temperature − C
0.20
0.15
External Reference,
±10-V Range
3
−4
2.490
−55 −35 −15 5
Full Scale Error − %FSR
10
fi − Input Frequency − kHz
Bipolar Zero Scale Error − mV
SFDR − Spurious Free Dynamic Range − dB
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
0.05
0
−0.05
−0.10
17
16
15
14
13
12
−0.15
11
−0.20
−40 −25 −10 5
14
20
35
50
65
80
10
−40 −25 −10 5
20
35
50
65
TA − Free-Air Temperature − C
TA − Free-Air Temperature − C
Figure 20.
Figure 21.
80
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
HISTOGRAM
4000
3500
8192
Conversions
of a DC Input
100
4224
95
|THD|
90
Performance
4500
PERFORMANCE
vs
CAP PIN CAPACITOR ESR
2500
2082
2000
1484
1500
80
75
70
60
500
4
0
SINAD
85
65
1000
−3
−2
−1
0
1
2
2.2 µF Capacitor on
CAP Pin (pin 6)
55
238
149
11
3
50
0
1
2
Code
Figure 22.
3 4 5 6 7 8 9
ESR − Resistance − 10 11
Figure 23.
INTEGRAL NONLINEARITY
2.5
fs = 250 KSPS
2
1.5
INL − LSBs
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0
16384
32768
49152
65536
49152
65536
Code
Figure 24.
DIFFERENTIAL NONLINEARITY
2.5
fs = 250 KSPS
2
1.5
1
DNL − LSBs
Hits
3000
0.5
0
−0.5
−1
−1.5
−2
−2.5
0
16384
32768
Code
Figure 25.
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ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
FFT (20 kHz Input)
20
8192 Points,
fs = 250 KSPS,
fi = 20 kHz, 0 dB
SINAD = 86.0 dB,
THD = −98.7 dB
0
−20
Amplitude − dB
−40
−60
−80
−100
−120
−140
−160
−180
0
25
50
75
100
125
f − Frequency − kHz
Figure 26.
BASIC OPERATION
Two signals control conversion in the ADS8509: CS and R/C. These two signals are internally ORed together. To
start a conversion the chip must be selected, CS low, and the conversion signal must be active, R/C low. Either
signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when
conversion starts and returns high after the data from that conversion is shifted into the internal storage register.
Sampling begins when BUSY goes high.
To reduce the number of control pins CS can be tied low permanently. The R/C pin now controls conversion and
data reading exclusively. In the external clock mode this means that the ADS8509 will clock out data whenever
R/C is brought high and the external clock is active. In the internal clock mode data is clocked out every convert
cycle regardless of the states of CS and R/C. The ADS8509 provides a TAG input for cascading multiple
converters together.
READING DATA
The conversion result is available as soon as BUSY returns to high therefore, data always represents the
conversion previously completed even when it is read during a conversion. The ADS8509 outputs serial data in
either straight binary or binary two’s compliment format. The SB/BTC pin controls the format. Data is shifted out
MSB first. The first conversion immediately following a power-up will not produce a valid conversion result.
Data can be clocked out with either the internally generated clock or with an external clock. The EXT/INT pin
controls this function. If external clock is used the TAG input can be used to daisy-chain multiple ADS8509 data
pins together.
INTERNAL DATACLK
In the internal clock mode data for the previous conversion is clocked out during each conversion period. The
internal data clock is synchronized to the internal conversion clock so that is does not interfere with the
conversion process.
The DATACLK pin becomes an output when EXT/INT is low. 16 clock pulses are generated at the beginning of
each conversion after timing t8 is satisfied, i.e. you can only read previous conversion result during conversion.
DATACLK returns to low when it is inactive. The 16 bits of serial data are shifted out the DATA pin synchronous
to this clock with each bit available on a rising and then a falling edge. DATA pin returns to the state of TAG pin
input sensed at the start of transmission.
EXTERNAL DATACLK
The external clock mode offers several ways to retrieve conversion results. However, since the external clock
cannot be synchronized to the internal conversion clock care must be taken to avoid corrupting the data.
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When EXT/INT is set high, the R/C and CS signals control the read state. When the read state is initiated the
result from the previously completed conversion is shifted out the DATA pin synchronous to the external clock
that is connected to the DATACLK pin. Each bit is available on a falling and then a rising edge. The maximum
external clock speed of 28.5 MHz allows data shifted out quickly either at the beginning of conversion or the
beginning of sampling.
There are several modes of operation available when using an external clock. It is recommended that the
external clock run only while reading data. This is the discontinuous clock mode. Since the external clock is not
synchronized to the internal clock that controls conversion slight changes in the external clock can cause
conflicts that can corrupt the conversion process. Specifications with a continuously running external clock
cannot be guaranteed. It is especially important that the external clock does not run during the second half of the
conversion cycle (approximately the time period specified by td11, see timing table).
In the discontinuous clock mode data can be read during conversion or during sampling, with or without a SYNC
pulse. Data read during a conversion must meet the td11 timing specification. Data read during sampling must be
complete before starting a conversion.
Whether reading during sampling or during conversion a SYNC pulse is generated whenever at least one rising
edge of the external clock occurs while the part is not in the read state. In the discontinuous external clock with
SYNC mode a SYNC pulse follows the first rising edge after the read command. The data is shifted out after the
SYNC pulse. The first rising clock edge after the read command generates a SYNC pulse. The SYNC pulse can
be detected on the next falling edge and then the next rising edge. Successively, each bit can be read first on the
falling edge and then on the next rising edge. Thus 17 clock pulses after the read command are required to read
on the falling edge. 18 clock pulses are necessary to read on the rising edge.
Table 2. DATACLK Pulses
DESCRIPTION
DATACLK PULSES REQUIRED
WITH SYNC
WITHOUT SYNC
Read on falling edge of DATACLK
17
16
Read on rising edge of DATACLK
18
17
If the clock is entirely inactive when not in the read state no SYNC pulse is generated. In this case the first rising
clock edge shifts out the MSB. The MSB can be read on the first falling edge or on the next rising edge. In this
discontinuous external clock mode with no SYNC, 16 clocks are necessary to read the data on the falling edge
and 17 clocks for reading on the rising edge. Data always represents the conversion already completed.
TAG FEATURE
The TAG feature allows the data from multiple ADS8509 converters to be read on a single serial line. The
converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in
Figure 27. The DATA pin of the last converter drives the processor's serial data input. Data is then shifted
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal
clock cannot be used for this configuration.
The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the td11 constraint (see the EXTERNAL DATACLOCK section). The sampling
period must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in Figure 27, that a NULL bit separates the data word from each converter. The state of the DATA pin at
the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ
modes, including the internal clock mode. For example, when a single converter is used in the internal clock
mode the state of the TAG pin determines the state of the DATA pin after all 16 bits have shifted out. When
multiple converters are cascaded together this state forms the NULL bit that separates the words. Thus, with the
TAG pin of the first converter grounded as shown in Figure 27 the NULL bit becomes a zero between each data
word.
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
Processor
ADS8509A
DATA
CS
R/C
DATACLK
TAG
SCLK
ADS 8509B
TAG(A)
DATA
CS
R/C
DATACLK
TAG
TAG(B)
GPIO
GPIO
SDI
Null
D
A00
Q
D
Q
D
Null
D
A15
Q
D
Q
D
B00
DATA (A)
A16
Q
D
Q
D
B15
Q
B16
DATA (B)
Q
DATACLK
R/C
(both A & B)
BUSY
(both A & B)
SYNC
(both A & B)
External
DATACLK
1
2
3
4
16
17
DATA ( A )
A15
A14
A13
A01
A00
DATA ( B )
B15
B14
B13
B01
B00
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
18
19
20
21
Null
TAG(A) = 0
A
Nth Conversion Data
Null A15
A14 A13
B
34
A01
35
36
A00
Null
A
TAG(A) = 0
.
Figure 27. Timing of TAG Feature With Single Conversion (Using External DATACLK)
ANALOG INPUTS
The ADS8509 has six analog input ranges as shown in Table 3. The offset and gain specifications are factory
calibrated with 0.1%, ¼-W, external resistors as shown in Figure 29 and Figure 30. The external resistors can be
omitted if larger gain and offset errors are acceptable or if using software calibration. The hardware trim circuitry
shown in Figure 29 and Figure 30 can reduce the errors to zero.
The analog input pins R1IN, R2IN, and R3IN have ±25-V overvoltage protection. The input signal must be
referenced to AGND1. This will minimized the ground loop problem typical to analog designs. The analog input
should be driven by a low impedance source. A typical driving circuit using OPA627 or OPA132 is shown in
Figure 28.
The ADS8509 can operate with its internal 2.5-V reference or an external reference. An external reference
connected to pin 6 (REF) bypasses the internal reference. The external reference must drive the 4-kΩ resistor
that separates pin 6 from the internal reference (see the illustration on page 1). The load will vary with the
difference between the internal and external reference voltages. The external reference voltage can vary from
2.3 V to 2.7 V. The internal reference will be approximately 2.5 V. The reference, whether internal or external, is
buffered internally with a buffer with its output on pin 5 (CAP).
The ADS8509 is factory tested with 2.2-µF capacitors connected to pins 5 and 6 (CAP and REF). Each capacitor
should be placed as close as possible to its pin. The capacitor on pin 6 band limits the internal reference noise. A
smaller capacitor can be used but it may degrade SNR and SINAD. The capacitor on pin 5 stabilizes the
reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 µF
can cause the buffer to become unstable may not hold sufficient charge for the CDAC. The parts are tested to
specifications with 2.2 µF so larger capacitors are not necessary. The equivalent series resistor (ESR) of these
compensation capacitors is also critical. Keep the total ESR under 3 Ω. See the TYPICAL CHARACTERISTICS
section concerning how ESR affects performance.
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance. Any load on the internal reference causes a voltage drop across the 4-kΩ resistor and will affect
gain. The internal buffer is capable of driving ±2-mA loads but any load can cause perturbations of the reference
at the CDAC, degrading performance. It should be pointed out that, unlike other competitor’s parts with similar
input structure, the ADS8509 does not require a second high speed amplifier used as buffer to isolate the CAP
pin from the signal dependent current in the R3IN pin but can tolerate it if one do exist.
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ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
The external reference voltage can vary from 2.3 V to 2.7 V. The reference voltage determines the size of the
least significant bit (LSB). The larger reference voltages produce a larger LSB, which can improve SNR. Smaller
reference voltages can degrade SNR.
+15V
2.2 F
22 pF
ADS8509
200 100 nF
GND
R1IN
2 k
Pin 7
2 k
Vin
Pin 2
22 pF
Pin3
AGND1
Pin 1
100 −
OPA 627
or
OPA 132
+
R2IN
Pin 6
GND
33.2 k
R3IN
Pin4
CAP
2.2 F
GND
REF
2.2 F
100 nF
GND
DGND
2.2 F
AGND2
GND
−15 V
GND
Figure 28. Typical Driving Circuitry (±10 V, No Trim)
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ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
Table 3. Input Range Connections (see Figure 29 and Figure 30 for complete
information)
ANALOG
INPUT RANGE
CONNECT R1IN VIA
200 Ω TO
CONNECT R2IN VIA
100 Ω TO
CONNECT
R3 TO
IMPEDANCE
±10 V
VIN
AGND
CAP
11.5 kΩ
±5 V
AGND
VIN
CAP
6.7 kΩ
±3.33 V
VIN
VIN
CAP
5.4 kΩ
0 V to 10 V
AGND
VIN
AGND
6.7 kΩ
0 V to 5 V
AGND
AGND
VIN
5.0 kΩ
0 V to 4 V
VIN
AGND
VIN
5.4 kΩ
Table 4. Control Truth Table
SPECIFIC FUNCTION
CS
R/C
BUSY
EXT/INT
DATACLK
PWRD
SB/BTC
OPERATION
Initiate conversion and output data using internal clock
1>0
0
1
0
Output
0
x
0
1>0
1
0
Output
0
x
Initiates conversion n. Data from conversion n - 1
clocked out on DATA synchronized to 16 clock
pulses output on DATACLK.
Initiate conversion and output data using external clock
1>0
0
1
1
Input
0
x
Initiates conversion n.
0
1>0
1
1
Input
0
x
Initiates conversion n.
1>0
1
1
1
Input
x
x
Outputs data with or without SYNC pulse. See
section Reading Data.
1>0
1
0
1
Input
0
x
Outputs data with or without SYNC pulse. See
section Reading Data.
0
0>1
0
1
Input
0
x
No actions
0
0
0>1
x
x
0
x
This is an acceptable condition.
Power down
x
x
x
x
x
0
x
Analog circuitry powered. Conversion can proceed..
x
x
x
x
x
1
x
Analog circuitry disabled. Data from previous
conversion maintained in output registers.
x
x
x
x
x
x
0
Serial data is output in binary 2s complement
format.
x
x
x
x
x
x
1
Serial data is output in straight binary format.
Selecting output format
Table 5. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
DESCRIPTION
Full-scale
range
BINARY 2's
COMPLEMENTS
(SB/BTC LOW)
ANALOG INPUT
STRAIGHT
BINARY
(SB/BTC HIGH)
BINARY CODE
HEX CODE
BINARY CODE
HEX CODE
3.999939 V
0111 1111 1111 1111
7FFF
1111 1111 1111 1111
FFFF
±10
±5
±3.33 V
0 V to 10 V
0 V to 5 V
0 V to 4 V
Least significant bit
(LSB)
305 µV
153 µV
102 µV
153 µV
76 µV
61 µV
Full scale
(FS - 1LSB)
9.999695 V
4.999847 V
3.333231 V
9.999847 V
4.999924 V
Midscale
0V
0V
0V
5V
2.5 V
2V
0000 0000 0000 0000
0000
1000 0000 0000 0000
8000
One LSB
below
midscale
-305 µV
153 µV
±102 µV
4.999847 V
2.499924 V
1.999939 V
1111 1111 1111 1111
FFFF
0111 1111 1111 1111
7FFF
-Full scale
-10 V
-5 V
-3.333333 V
0V
0V
0V
1000 0000 0000 0000
8000
0000 0000 0000 0000
0000
20
ADS8509
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SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
Input Range
With Trim
(Adjust Offset First at 0 V, Then Adjust Gain)
Without Trim
200 Ω
200 Ω
R1IN
R1IN
AGND1
AGND1
100 Ω
100 Ω
0 V − 10 V
VIN
R2IN
33.2 kΩ
R3IN
R2IN
VIN
33.2 kΩ
2.2 µF
+5V
CAP
+
50 kΩ
2.2 µF
+
R3IN
2.2 µF
+
+5V
CAP
576 kΩ
50 kΩ
REF
REF
+
2.2 µF
AGND2
200 Ω
AGND2
200 Ω
R1IN
R1IN
AGND1
100 Ω
R2IN
33.2 kΩ
VIN
+5 V
CAP
2.2 µF
+
+5 V
50 kΩ
2.2 µF
REF
2.2 µF
R2IN
33.2 kΩ
R3IN
VIN
0V−5V
AGND1
100 Ω
+
+
R3IN
CAP
576 kΩ
50 kΩ
2.2 µF
AGND2
200 Ω
R1IN
VIN
AGND1
100 Ω
100 Ω
R2IN
R2IN
R3IN
R3IN
33.2 kΩ
+5 V
+
33.2 kΩ
+5 V
CAP
2.2 µF
AGND2
R1IN
AGND1
2.2 µF
REF
200 Ω
VIN
0V−4V
+
+
REF
2.2 µF
+
576 kΩ
50 kΩ
50 kΩ
2.2 µF
AGND2
CAP
REF
+
AGND2
Figure 29. Offset/Gain Circuits for Unipolar Input Ranges
21
ADS8509
www.ti.com
SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
Input Range
With Trim
(Adjust Offset First at 0 V, Then Adjust Gain)
Without Trim
200 Ω
VIN
200 Ω
R1IN
R1IN
VIN
AGND1
AGND1
100 Ω
100 Ω
R2IN
±10 V
R2IN
+5 V
R3IN
33.2 kΩ
+
2.2 F
+
R3IN
+5 V
50 kΩ
CAP
2.2 F
33.2 kΩ
REF
2.2 µF
576 kΩ
+
2.2 µF
+
CAP
REF
50 kΩ
AGND2
AGND2
200 Ω
200 Ω
R1IN
R1IN
AGND1
AGND1
100 Ω
VIN
33.2 kΩ
±5V
R3IN
CAP
50 kΩ
2.2 µF
+
2.2 µF
R2IN
R3IN
+
2.2 µF
+5 V
+5 V
+
100 Ω
VIN
33.2 kΩ
R2IN
CAP
576 kΩ
50 kΩ
REF
REF
+
2.2 µF
AGND2
200 Ω
AGND2
200 Ω
VIN
R1IN
100 Ω
R1IN
VIN
100 Ω
AGND1
AGND1
R2IN
R2IN
R3IN
33.2 kΩ
±3.3 V
33.2 kΩ
2.2 µF
+5 V
CAP
+
+
REF
2.2 F
AGND2
CAP
+5 V
50 kΩ
2.2 F
576 kΩ
50 kΩ
+
2.2 µF
Figure 30. Offset/Gain Circuits for Bipolar Input Ranges
22
R3IN
+
REF
AGND2
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
ADS8509IBDB
ACTIVE
SSOP
DB
28
50
TBD
Call TI
Call TI
ADS8509IBDBR
ACTIVE
SSOP
DB
28
2000
TBD
Call TI
Call TI
ADS8509IBDBRG4
ACTIVE
SSOP
DB
28
2000
TBD
Call TI
Call TI
ADS8509IBDW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8509IBDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8509IBDWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8509IDB
ACTIVE
SSOP
DB
28
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8509IDBR
ACTIVE
SSOP
DB
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8509IDBRG4
ACTIVE
SSOP
DB
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8509IDW
ACTIVE
SOIC
DW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8509IDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8509IDWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
50
25
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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