512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Features DDR2 SDRAM Unbuffered DIMM MT16HTF6464A – 512MB MT16HTF12864A – 1GB MT16HTF25664A – 2GB For component specifications, refer to the Micron’s Web site: www.micron.com/ddr2 Features Figure 1: • 240-pin, unbuffered, dual in-line memory module (UDIMM) • Fast data transfer rates: PC2-3200, PC2-4200, PC25300, or PC2-6400 • 512MB (64 Meg x 64), 1GB (128 Meg x 64), and 2GB (256 Meg x 64) • VDD = VDDQ = +1.8V • VDDSPD = +1.7V to +3.6V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Differential data strobe (DQS, DQS#) option • Four-bit prefetch architecture • DLL to align DQ and DQS transitions with CK • Multiple internal device banks for concurrent operation • Programmable CAS latency (CL) • Posted CAS additive latency (AL) • WRITE latency = READ latency - 1 tCK • Programmable burst lengths: 4 or 8 • Adjustable data-output drive strength • 64ms, 8,192-cycle refresh • On-die termination (ODT) • Serial presence-detect (SPD) with EEPROM • Gold edge contacts • Dual rank PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 240-Pin DIMM (MO-237 R/C “B”) PCB height: 29.97mm (1.18in) Options • Package 240-pin DIMM (lead-free) • Frequency/CL1 2.5ns @ CL = 5 (DDR2-800)2 3.0ns @ CL = 5 (DDR2-667)3 3.75ns @ CL = 4 (DDR2-533) 5.0ns @ CL = 3 (DDR2-400) • PCB height 29.97mm (1.18in) Marking Y -80E -667 -53E -40E Notes: 1. CL = CAS (READ) latency. 2. Not available in 512MB density. 3. Not available in 2GB density. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Features Table 1: Address Table Refresh count Row addressing Device bank addressing Device page size per bank Device configuration Column addressing Module rank addressing Table 2: 512MB 1GB 2GB 8K 8K (A0–A12) 4 (BA0, BA1) 1KB 256Mb (32 Meg x 8) 1K (A0–A9) 2 (S0#, S1#) 8K 16K (A0–A13) 4 (BA0, BA1) 1KB 512Mb (64 Meg x 8) 1K (A0–A9) 2 (S0#, S1#) 8K 16K (A0–A13) 8 (BA0, BA1, BA2) 1KB 1Gb (128 Meg x 8) 1K (A0–A9) 2 (S0#, S1#) Key Timing Parameters Data Rate (MT/s) Speed Grade CL = 3 CL = 4 CL = 5 (ns) tRP (ns) tRC (ns) -80E -667 -53E -40E – 400 400 400 533 533 533 400 800 667 – – 12.5 15 15 15 12.5 15 15 15 55 55 55 55 Table 3: tRCD Part Numbers and Timing Parameters Part Number1 MT16HTF6464AY-667__ MT16HTF6464AY-53E__ MT16HTF6464AY-40E__ MT16HTF12864AY-80E__ MT16HTF12864AY-667__ MT16HTF12864AY-53E__ MT16HTF12864AY-40E__ MT16HTF25664AY-80E__ MT16HTF25664AY-667__ MT16HTF25664AY-53E__ MT16HTF25664AY-40E__ Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 512MB 512MB 512MB 1GB 1GB 1GB 1GB 2GB 2GB 2GB 2GB 64 Meg x 64 64 Meg x 64 64 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 256 Meg x 64 256 Meg x 64 256 Meg x 64 256 Meg x 64 5.3 GB/s 4.3 GB/s 3.2 GB/s 6.4 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 6.4 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 2.5ns/800 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 2.5ns/800 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 5-5-5 5-5-5 4-4-4 3-3-3 5-5-5 5-5-5 4-4-4 3-3-3 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT16HTF12864AY-80ED4. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 4: Pin Assignment 240-pin DIMM Front 240-pin DIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS NC NC VSS NC NC VSS NC NC VSS VDDQ CKE0 VDD NC/BA2 NC VDDQ A11 A7 VDD A5 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 A4 VDDQ A2 VDD VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE# CAS# VDDQ S1# ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 CK1# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS NC NC VSS DM8 NC VSS NC NC VSS VDDQ CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 VDDQ A3 A1 VDD CK0 CK0# VDD A0 VDD BA1 VDDQ RAS# S0# VDDQ ODT0 NC/A13 VDD VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 CK2# VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 Note: Figure 2: Pin 196 is NC for 512MB, or A13 for 1GB and 2GB; pin 54 is NC for 512MB and 1GB, or BA2 for 2GB. Pin Locations Back View Front View U1 U2 U3 U6 U4 U7 U8 U10 U9 U11 U13 U12 U15 U16 U17 U18 U19 PIN 1 PIN 64 PIN 65 PIN 240 PIN 120 PIN 184 PIN 121 Indicates a VSS pin Indicates a VDD or VDDQ pin PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN PIN 185 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information Pin Numbers Symbol Type Description 77, 195 ODT0, ODT1 Input 137, 138, 185, 186, 220, 221 CK0, CK0#, CK1, CK1#, CK2, CK2# Input 52, 171 CKE0, CKE1 Input 76, 193 S0#, S1# Input 73, 74, 192 RAS#, CAS#, WE# Input 54 (2GB), 71, 190 BA0, BA1, BA2 (2GB) Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides precharge power-down and SELF REFRESH operations (all device banks idle), or ACTIVE powerdown (row ACTIVE in any device bank). CKE is synchronous for power-down entry, power-down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level when VDD is applied during first power-up. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF REFRESH operation, VREF must be maintained to this input. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LMR command. Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the precharge applies to one device bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LMR command. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. 57, 58, 60, 61, 63, 70, 176, A0–A12 (512MB) 177, 179, 180, 182, 183, 188, A0–A13 (1GB, 2GB) 196 (1GB, 2GB) Input 125, 134, 146, 155, 202, 211, 223, 232 Input PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN DM0–DM7 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information Pin Numbers Symbol Type Description 120 SCL Input 101, 239, 240 SA0–SA2 Input 3, 4, 9, 10, 12, 13, 21, 22, 24, 25, 30, 31, 33, 34, 39, 40, 80, 81, 86, 87, 89, 90, 95, 96, 98, 99, 107, 108, 110, 111, 116, 117, 122, 123, 128, 129, 131, 132, 140, 141, 143, 144, 149, 150, 152, 153, 158, 159, 199, 200, 205, 206, 208, 209, 214, 215, 217, 218, 226, 227, 229, 230, 235, 236 6, 7, 15, 16, 27, 28, 36, 37, 83, 84, 92, 93, 104, 105, 113, 114, DQ0–DQ63 I/O Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-detect address inputs: These pins are used to configure the presence-detect device. Data Input/output: Bidirectional data bus. DQS0–DQS7, DQS0#–DQS7# I/O 119 SDA 53, 59, 64, 67, 69, 172, 178, 184, 187, 189, 197, 51, 56, 62, 72, 75, 78, 170, 175, 181, 191, 194, 1 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97,100, 103, 106, 109,112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 238 18, 19, 42, 43, 45, 46, 48, 49, 54 (512MB, 1GB), 55, 68, 76, 102, 125, 126, 134, 135, 146, 147, 155, 156, 161, 162, 164, 165, 167, 168, 171, 173, 174, 196 (512MB), 202, 203, 211, 212, 223, 224, 232, 233 VDD PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN VDDQ VREF VSS VDDSPD NC Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Supply Power supply: +1.8V ±0.1V. Supply DQ Power supply: +1.8V ±0.1V. Supply SSTL_18 reference voltage. Supply Ground. Supply Serial EEPROM positive power supply: +1.7V to +3.6V. – No connect: These pins should be left unconnected. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Functional Block Diagram Functional Block Diagram Unless otherwise noted, resistor values are 22Ω. Micron module part numbers are explained in the module part numbering guide at www.micron.com/numbering.html. Modules use the following DDR2 SDRAM devices: MT47H32M8BT (512MB); MT47H64M8BT (1GB); and MT47H128M8BT (2GB). Figure 3: Functional Block Diagram S1# 25pF S0# 25pF DQS0# DQS0 DM0 DQS4# DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U1 CS# DQ DM DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U19 DQS1# DQS1 DM1 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U6 CS# DQ DQS# U14 DQS5# DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U2 CS# DQ DM DQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U18 DQS2# DQS2 DM2 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U7 CS# DQ DQS# U13 DQS6# DQS6 DM6 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U3 CS# DQ DM DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U17 DQS3# DQS3 DM3 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U8 CS# DQ DQS# U12 DQS7# DQS7 DM7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# U4 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U16 7.5Ω BA0–BA1 (512MB, 1GB) BA0–BA2 (2GB) A0–A12 (512M) A0–A13 (1GB, 2GB) RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 25pF 25pF 25pF 25pF BA0–BA1: DDR2 SDRAMs BA0–BA2: DDR2 SDRAMs A0–A12: DDR2 SDRAMs A0–A13: DDR2 SDRAMs RAS#: DDR2 SDRAMs CAS#: DDR2 SDRAMs WE#: DDR2 SDRAMs CKE0: U1–U4, U6–U9 CKE1: U11–U14, U16–U19 DM DQS# SCL U10 Serial PD WP A0 A1 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# U9 A2 DQ DQS# U11 CK0 CK0# U4, U6 U14, U16 1pF Serial PD VDD, VDDL, VDDQ DDR2 SDRAMS VREF DDR2 SDRAMS VSS CS# 67Ω SDA SA0 SA1 SA2 VDDSPD DM DQ DQ DQ DQ DQ DQ DQ DQ DDR2 SDRAMS, EEPROM 67Ω CK1 CK1# U1–U3, U17–U19 67Ω CK2 CK2# U7–U10, U11–U13 ODT0: U1–U4, U6–U9 ODT1: U11–U14, U16–U19 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM General Description General Description The MT16HTF6464A, MT16HTF12864A, and MT16HTF25664A DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 512MB, 1GB, and 2GB memory modules organized in x64 configuration. DDR2 modules use internally configured 4bank (512MB, 1GB) or 8-bank (2GB) DDR2 devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DDR2 device core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR2 modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various DDR2 organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 6: Absolute Maximum Ratings Parameter Symbol Min Max Units VDD supply voltage relative to VSS VDDQ supply voltage relative to VSS VDDL supply voltage relative to Vss Voltage on any pin relative to VSS Storage temperature DDR2 SDRAM device operating temperature (ambient) Operating temperature (ambient) Command/address, Input leakage current; Any input 0V ≤ VIN ≤ VDD; RAS#, CAS#, WE# VREF input 0V ≤ VIN ≤0.95V; (All other pins not under test = 0V) S#, CKE1 CK0, CK0# CK1, CK1#, CK2, CK2# DM Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = Valid VREF level VDD VDDQ VDDL2 VIN, VOUT TSTG Tcase TOPR II –1.0 –0.5 –0.5 –0.5 –55 0 0 2.3 2.3 2.3 2.3 100 85 55 V V V V °C °C °C –80 80 –40 –20 –30 –10 40 20 30 10 IOZ –10 10 µA – –32 32 µA Notes: µA 1. S# is defined to be S0# and S1#. CKE includes both CKE0 and CKE1. 2. VDDL is the power supply for the DDR2 devices’ DLL; however, this power supply is not brought directy to a DIMM pin. Capacitance At DDR2 data rates, Micron encourages designers to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Electrical Specifications Table 7: DDR2 IDD Specifications and Conditions – 512MB Values shown for DDR2 SDRAM components only Parameter/Condition t Operating one device bank active-precharge current; CK = CK (IDD), t RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one device bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; tCK = tCK Fast PDN exit MR[12] = 0 (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 t t Active standby current; All device banks open; CK = CK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating device bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching; See IDD7 conditions in component data sheet for detail Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN Symbol -667 -53E -40E Units IDD0a 680 680 640 mA IDD1a 760 760 720 mA IDD2Pb 80 80 80 mA IDD2Qb 560 560 400 mA IDD2Nb 640 560 480 mA 480 400 320 mA 96 96 96 mA IDD3Nb 800 640 480 mA IDD4Wa 1,560 1,320 1,040 mA IDD4Ra 1,480 1,240 960 mA IDD5b 2,880 2,720 2,640 mA IDD6b 80 80 80 mA IDD7a 2,040 1,960 1,880 mA t IDD3Pb 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW). 2. b = Value calculated reflects all module ranks in this operating condition. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Electrical Specifications Table 8: DDR2 IDD Specifications and Conditions – 1GB Values shown for DDR2 SDRAM components only Parameter/Condition Symbol t Operating one device bank active-precharge current; CK = CK (IDD), t RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between IDD0a valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one device bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = t IDD1a RAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); IDD2Pb CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; IDD2Qb Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is IDD2Nb HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; tCK Fast PDN exit = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 IDD3Pb inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid IDD3Nb commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX IDD4Wa (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS IDD4Ra MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other IDD5b control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and IDD6b address bus inputs are floating; Data bus inputs are floating Operating device bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD IDD7a (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching; See IDD7 conditions in component data sheet for detail Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN -80E -667 -53E -40E Units 856 776 696 696 mA 976 896 816 776 mA 112 112 112 112 mA 800 720 640 560 mA 880 800 720 640 mA 640 560 480 400 mA 192 192 192 192 mA 1,120 1,040 880 720 mA 1,616 1,416 1,1176 976 mA 1,696 1,496 1,216 976 mA 3,680 2,880 2,720 2,640 mA 112 112 112 112 mA 2,456 1,976 1,856 1,816 mA t 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW). 2. b = Value calculated reflects all module ranks in this operating condition. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Electrical Specifications Table 9: DDR2 IDD Specifications and Conditions – 2GB Values shown for DDR2 SDRAM components only Parameter/Condition t Operating one device bank active-precharge current; CK = CK (IDD), RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one device bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = t RAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; tCK Fast PDN exit = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open; Ccontinuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating device bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching; See IDD7 conditions in component data sheet for detail t Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN Symbol -80E -667 -53E -40E Units IDD0a 856 776 696 616 mA IDD1a 936 856 816 696 mA IDD2Pb 112 112 112 112 mA IDD2Qb 1,040 880 656 560 mA IDD2Nb 1,120 960 720 640 mA 720 640 480 400 mA 160 160 160 160 mA IDD3Nb 1,200 1,120 880 720 mA IDD4Wa 1,536 1,336 1,096 936 mA IDD4Ra 1,576 1,336 1,216 936 mA IDD5b 4,480 4,160 4,000 3,520 mA IDD6b 112 112 112 112 mA IDD7a 2,736 2,456 2,376 2,136 mA t IDD3Pb 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW). 2. b = Value calculated reflects all module ranks in this operating condition. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM AC Timing and Operating Conditions AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’s Web site: www.micron.com/ddr2. Module speed grades correlate with component speed grades as shown in the following table: Table 10: Module and Component Speed Grade Table PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN Module Speed Grade Component Speed Grade -80E -667 -53E -40E -25E -3 -37E -5E 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 4 and 5 on page 14). SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SPD Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting 8 bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the 8 bits of data (Figure 6 on page 14). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent 8-bit word. In the read mode the SPD device will transmit 8 bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Figure 4: Data Validity SCL SDA Data stable Figure 5: Data change Data stable Definition of Start and Stop SCL SDA Start bit Figure 6: Stop bit Acknowledge Response From Receiver (( )) SCL from master (( )) (( )) Data output from transmitter (( )) Data output from receiver Acknowledge PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Table 11: EEPROM Device Select Code The most significant bit (b7) is sent first Device Type Identifier Select Code Memory area select code (two arrays) Protection register select code Table 12: RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW EEPROM Operating Modes Mode RW Bit WC Bytes 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 ≥1 1 ≤ 16 Current address READ Random address READ Sequential READ Byte WRITE Page WRITE Figure 7: Chip Enable Initial Sequence Start, device select, RW = 1 Start, device select, RW = 0, address Restart, device select, RW = 1 Similar to current or random address READ Start, device select, RW = 0 Start, device select, RW = 0 SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA In t DH t AA t BUF SDA Out UNDEFINED PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Table 13: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current: Power supply current, READ: SCL clock frequency = 100 KHz Power supply current, WRITE: SCL clock frequency = 100 KHz Table 14: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 1.7 VDDSPD × 0.7 –0.6 – 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 VDDSPD × 0.3 0.4 3 3 4 1 3 V V V V µA µA µA mA mA Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN Symbol Min Max Units Notes tAA 0.2 1.3 200 – 0 0.6 0.6 – 1.3 – – 100 0.6 0.6 – 0.9 – – 300 – – – 50 – 0.3 400 – – – 10 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT tSU:STA tSU:STO t WRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Table 15: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; table notes located on page 19 Byte 0 1 2 3 4 5 6 7 8 9 Description Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on assembly Number of column addresses on assembly DIMM height and module ranks Module data width Reserved Module voltage interface levels DDR2 cycle time, tCK (CL = MAX value, see byte 18) 10 DDR2 access from clock,tAC (CL = MAX value, see byte 18) 11 12 13 Module configuration type Refresh rate/type DDR2 SDRAM device width (primary device) Error-checking DDR2 data width Reserved Burst lengths supported Number of banks on DDR2 device CAS latencies supported 14 15 16 17 18 19 20 21 22 23 Module thickness DDR2 DIMM type DDR2 module attributes DDR2 device attributes: weak driver (01) or 50Ω ODT (03) DDR2 cycle time, tCK, MAX CL - 1 24 SDRAM access from CK, tAC, MAX CL - 1 25 SDRAM cycle time, tCK, MAX CL - 2 26 SDRAM access from CK, tAC, MAX CL - 2 27 MIN row precharge time, tRP PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN Entry (Version) MT16HTF6464A MT16HTF12864A MT16HTF25664A 128 256 DDR2 SDRAM 13, 14 10 80 08 08 0D 0A 80 08 08 0E 0A 80 08 08 0E 0A 1.18in, dual rank 64 0 SSTL 1.8V -80E -667 -53E -40E -80E -667 -53E -40E 61 40 00 05 – 30 3D 50 – 45 50 60 00 82 08 61 40 00 05 25 30 3D 50 40 45 50 60 00 82 08 61 40 00 05 25 30 3D 50 40 45 50 60 00 82 08 00 00 0C 04 – 38 18 01 02 00 03 01 3D 50 50 – 45 50 60 – 50 00 – 45 00 – 3C 00 00 0C 04 30 38 18 01 02 00 03 01 3D 50 50 40 45 50 60 00 50 00 00 45 00 32 3C 00 00 0C 08 30 38 18 01 02 00 03 01 3D 50 50 40 45 50 60 00 50 00 00 45 00 32 3C 7.81µs/self 8 N/A 1 clock 4, 8 4 or 8 -80E (6, 5, 4) -667 (5, 4, 3) -53E/-40E (4, 3) Unbuffered -80E/-667 -53E/-40E -80E/-667 -53E -40E -80E -667 -53E -40E -80E -667 -53E/-40E(N/A) -80E -667 -53E/-40E(N/A) -80E -667/-53E/-40E 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Table 15: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; table notes located on page 19 Byte 28 29 Description Entry (Version) t MIN row active to row active, RRD MIN RAS#-to-CAS# delay, tRCD -80E -667/-53E/-40E -80E/-667/-53E 30 MIN RAS# pulse width, tRAS -40E 256MB, 512MB, 1GB 31 Module rank density -80E 32 Address and command setup time, tISb -667 -53E -40E tIH -80E 33 Address and command hold time, b -667 -53E -40E -80E 34 Data/data mask input setup time, tDSb -667/-53E -40E -80E 35 Data/data mask input hold time, tDHb -667 -53E -40E 36 Write recovery time, tWR -80E/-667/-53E 37 WRITE-to-READ command delay, tWTR -40E 38 READ-to-PRECHARGE command delay, tRTP 39 Mem analysis probe 40 -80E Extension for bytes 41 and 42 -667/-53E/-40E -80E 41 MIN active auto refresh time, tRC -667/-53E -40E 42 MIN AUTO REFRESH-to-ACTIVE/ AUTO REFRESH command period, tRFC 43 DDR2 device MAX cycle time, tCKMAX 44 -80E DDR2 device MAX DQS-DQ skew time, tDQSQ -667 -53E -40E -80E 45 DDR2 device MAX read data hold skew -667 factor, tQHS -53E -40E 46 PLL relock time 47–61 Optional features, not supported 62 Release 1.2 SPD revision 63 -80E Checksum for bytes 0–62 -667 -53E -40E PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 18 MT16HTF6464A MT16HTF12864A MT16HTF25664A 1E – 3C 2D 28 40 – 20 25 35 – 27 37 47 – 10 15 – 17 22 27 3C 1E 28 1E 1E 32 3C 2D 28 80 17 20 25 35 25 27 37 47 05 10 15 12 17 22 27 3C 1E 28 1E 1E 32 3C 2D 28 01 17 20 25 35 25 27 37 47 05 10 15 12 17 22 27 3C 1E 28 1E 00 – 00 – 3C 37 69 00 30 00 39 3C 37 69 00 36 06 39 3C 37 7F 80 – 18 1E 23 – 22 28 2D 00 00 12 – ED 98 FF 80 14 18 1E 23 1E 22 28 2D 00 00 12 90 4C F7 5E 80 14 18 1E 23 1E 22 28 2D 00 00 12 31 ED 98 FF Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Table 15: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; table notes located on page 19 Byte 64 65-71 72 73-90 91 92 93 94 95-98 99-127 Description Manufacturer’s JEDEC ID code Manufacturer’s JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Manufacturer-specific data (RSVD) Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN Entry (Version) MICRON (Continued) 01–12 1–9 0 MT16HTF6464A MT16HTF12864A MT16HTF25664A 2C FF 01–0C Variable data 01–09 00 Variable data Variable data Variable data – 2C FF 01–0C Variable data 01–09 00 Variable data Variable data Variable data – 2C FF 01–0C Variable data 01–09 00 Variable data Variable data Variable data – 1. The tRAS SPD value shown is based on the JEDEC standard value of 45ns; the actual device specification is tRAS = 40ns. 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Module Dimensions Module Dimensions Figure 8: 240-pin DIMM DDR2 Module Dimensions 4.0 (0.157) MAX FRONT VIEW 133.50 (5.256) 133.20 (5.244) 2.00 (0.079) R (4X) U1 U2 U3 U4 U6 2.50 (0.098) D (2X) U7 U8 U9 30.50 (1.200) 29.85 (1.175) 17.78 (0.700) TYP. U10 2.30 (0.091) TYP. 0.76 (0.030) R PIN 1 1.0 (0.039) TYP. 10.00 (0.394) TYP. 0.80 (0.031) TYP. 1.37 (0.054) 1.17 (0.046) PIN 120 123.0 (4.840) TYP. BACK VIEW U11 U12 U13 PIN 240 U14 U16 U18 U19 PIN 121 5.0 (0.197) TYP. 55.0 (2.165) TYP. Notes: U17 63.0 (2.48) TYP. 1. All dimensions are in millimeters (inches); MAX or typical where noted. MIN 2. The dimensional diagram is for reference only. Refer to the MO document for complete design dimensions. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Revision History Revision History Rev. D, Released (No Mark). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/06 • Added -80E speed grade to 1GB and 2GB densities • Removed component data • Updated format, style Rev. C, Released (No Mark) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/05 • Corrected 1GB -53E SPD Rev. C, Released (No Mark) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/05 • Added -667 speed grade • Updated Initialization process • Updated Idds Rev. B, Released (No Mark) (MT16HTF6464A), Preliminary (MT16HTF12864A, MT16HTF25664A) . . . . . . . . . . 8/04 • Updated features list • Updated part numbers • Removed OCD, updated General Description • Updated Initialization diagram, EMR diagrams • Updated Table 15, AC Operating Conditions • Updated SPD Rev. A, Pub. 11/03, Preliminary (MT16HTF6464A), Advance (MT16HTF12864A and MT16HTF25664A) . . . . .11/03 • New Datasheet, lvg’d from HTF8C32_64_128x72AG PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved.