Vishay IRFU020PBF Power mosfet Datasheet

IRFR020, IRFU020, SiHFR020, SiHFU020
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Halogen-free According to IEC 61249-2-21
Definition
• Dynamic dV/dt Rating
• Surface Mount (IRFR020, SiHFR020)
• Available in Tape and Reel
• Fast Switching
• Ease of Paralleling
• Simple Drive Requirements
• Compliant to RoHS Directive 2002/95/EC
60
RDS(on) (Ω)
VGS = 10 V
0.10
Qg (Max.) (nC)
25
Qgs (nC)
5.8
Qgd (nC)
11
Configuration
Single
D
DPAK
(TO-252)
IPAK
(TO-251)
DESCRIPTION
D
D
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques.
G
G
S
G
D S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
DPAK (TO-252)
IPAK (TO-251)
Lead (Pb)-free and Halogen-free
SiHFR020-GE3
SiHFR020TR-GE3
SiHFU020-GE3
IRFR020PbF
IRFR020TRPbFa
IRFU020PbF
SiHFR020-E3
SiHFR020T-E3a
SiHFU020-E3
IRFR020
IRFR020TRa
IRFU020
SiHFR020
SiHFR020Ta
SiHFU020
Lead (Pb)-free
SnPb
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
60
Gate-Source Voltage
VGS
± 20
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
IDM
0.33
0.020
EAS
TC = 25 °C
Maximum Power Dissipation (PCB Mount)e
TA = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
PD
A
56
Linear Derating Factor
Maximum Power Dissipation
V
14
9.0
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
UNIT
91
42
2.5
dV/dt
5.5
TJ, Tstg
- 55 to + 150
260d
W/°C
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 541 μH, Rg = 25 Ω, IAS = 14 A (see fig. 12).
c. ISD ≤ 17 A, dI/dt ≤ 110 A/μs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 90335
S10-1122-Rev. B, 10-May-10
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IRFR020, IRFU020, SiHFR020, SiHFU020
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
-
-
50
Maximum Junction-to-Case (Drain)
RthJC
-
-
3.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = 250 μA
60
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.073
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
nA
IGSS
IDSS
RDS(on)
gfs
VGS = ± 20 V
-
-
± 100
VDS = 60 V, VGS = 0 V
-
-
25
VDS = 48 V, VGS = 0 V, TJ = 125 °C
-
-
250
ID = 8.4 Ab
VGS = 10 V
VDS = 25 V, ID = 8.4 A
μA
-
-
0.10
Ω
6.2
-
-
S
-
640
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
360
-
79
-
-
-
25
Gate-Source Charge
Qgs
-
-
5.8
Gate-Drain Charge
Qgd
-
-
11
Turn-On Delay Time
td(on)
-
13
-
tr
-
58
-
-
25
-
-
42
-
-
4.5
-
-
7.5
-
-
-
14
-
-
56
-
-
1.5
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 10 V
ID = 17 A, VDS = 48 V,
see fig. 6 and 13b
-
VDD = 30 V, ID = 17 A,
RG = 18 Ω, RD = 1.7 Ω, see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contactc
pF
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 14 A, VGS = 0 Vb
TJ = 25 °C, IF = 17 A, dI/dt = 100 A/μsb
V
-
88
180
ns
-
0.29
0.64
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.
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Document Number: 90335
S10-1122-Rev. B, 10-May-10
IRFR020, IRFU020, SiHFR020, SiHFU020
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Document Number: 90335
S10-1122-Rev. B, 10-May-10
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFR020, IRFU020, SiHFR020, SiHFU020
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 90335
S10-1122-Rev. B, 10-May-10
IRFR020, IRFU020, SiHFR020, SiHFU020
Vishay Siliconix
VDS
VGS
RD
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
tr
td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 90335
S10-1122-Rev. B, 10-May-10
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IRFR020, IRFU020, SiHFR020, SiHFU020
Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T.
RG
+
-
I AS
V DD
VDS
10 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 90335
S10-1122-Rev. B, 10-May-10
IRFR020, IRFU020, SiHFR020, SiHFU020
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90335.
Document Number: 90335
S10-1122-Rev. B, 10-May-10
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Package Information
Vishay Siliconix
TO-252AA (HIGH VOLTAGE)
E
b3
E1
L3
D1
D
H
L4
b2
b
A
c2
e
A1
L1
L
c
θ
L2
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
E
6.40
6.73
0.252
0.265
L
1.40
1.77
0.055
L1
2.743 REF
L2
0.070
0.108 REF
0.508 BSC
0.020 BSC
L3
0.89
1.27
0.035
0.050
L4
0.64
1.01
0.025
0.040
D
6.00
6.22
0.236
0.245
H
9.40
10.40
0.370
0.409
b
0.64
0.88
0.025
0.035
b2
0.77
1.14
0.030
0.045
b3
5.21
5.46
0.205
e
2.286 BSC
0.215
0.090 BSC
A
2.20
2.38
0.087
A1
0.00
0.13
0.000
0.094
0.005
c
0.45
0.60
0.018
0.024
c2
0.45
0.58
0.018
0.023
D1
5.30
-
0.209
-
E1
4.40
-
0.173
-
θ
0'
10'
0'
10'
ECN: S-81965-Rev. A, 15-Sep-08
DWG: 5973
Notes
1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side.
2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
3. The package top may be smaller than the package bottom.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum
material condition. The dambar cannot be located on the lower radius of the foot.
Document Number: 91344
Revision: 15-Sep-08
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Package Information
Vishay Siliconix
TO-251AA (HIGH VOLTAGE)
4
3
E1
E
Thermal PAD
4
b4
θ2
4
A
0.010 0.25 M C A B
L2 4
c2
A
θ1
B
D
D1
A
C
3
Seating
plane
5
C
L1 L3
(Datum A)
C
L
B
B
A
A1
3 x b2
View A - A
2xe
c
3xb
0.010 0.25 M C A B
Plating
5
b1, b3
Base
metal
Lead tip
c1
(c)
5
(b, b2)
Section B - B and C - C
MILLIMETERS
DIM.
MIN.
MAX.
INCHES
MIN.
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
2.18
2.39
0.086
0.094
D1
5.21
-
0.205
-
A1
0.89
1.14
0.035
0.045
E
6.35
6.73
0.250
0.265
4.32
-
0.170
-
b
0.64
0.89
0.025
0.035
E1
b1
0.65
0.79
0.026
0.031
e
b2
0.76
1.14
0.030
0.045
L
8.89
9.65
0.350
0.380
b3
0.76
1.04
0.030
0.041
L1
1.91
2.29
0.075
0.090
b4
4.95
5.46
0.195
0.215
L2
0.89
1.27
0.035
0.050
2.29 BSC
2.29 BSC
c
0.46
0.61
0.018
0.024
L3
1.14
1.52
0.045
0.060
c1
0.41
0.56
0.016
0.022
θ1
0'
15'
0'
15'
c2
0.46
0.86
0.018
0.034
θ2
25'
35'
25'
35'
D
5.97
6.22
0.235
0.245
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
Document Number: 91362
Revision: 15-Sep-08
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Document Number: 91000
Revision: 11-Mar-11
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