Intersil ISL6551 Zvs full bridge pwm controller Datasheet

ISL6551
®
Data Sheet
July 8, 2005
FN9066.4
ZVS Full Bridge PWM Controller
Features
The ISL6551 is a zero voltage switching (ZVS) full-bridge
PWM controller designed for isolated power systems. This
part implements a unique control algorithm for fixedfrequency ZVS current mode control, yielding high efficiency
with low EMI. The two lower drivers are PWM-controlled on
the trailing edge and employ resonant delay while the two
upper drivers are driven at a fixed 50% duty cycle.
• High Speed PWM (up to 1MHz) for ZVS Full Bridge
Control
This IC integrates many features in both 6x6 mm2 QFN and
28-lead SOIC packages to yield a complete and
sophisticated power supply solution. Control features include
programmable soft-start for controlled start-up,
programmable resonant delay for zero voltage switching,
programmable leading edge blanking to prevent false
triggering of the PWM comparator due to the leading edge
spike of the current ramp, adjustable ramp for slope
compensation, drive signals for implementing synchronous
rectification in high output current, ultra high efficiency
applications, and current share support for paralleling up to
10 units, which helps achieve higher reliability and
availability as well as better thermal management. Protective
features include adjustable cycle-by-cycle peak current
limiting for overcurrent protection, fast short-circuit protection
(in hiccup mode), a latching shutdown input to turn off the IC
completely on output overvoltage conditions or other
extreme and undesirable faults, a non-latching enable input
to accept an enable command when monitoring the input
voltage and thermal condition of a converter, and VDD under
voltage lockout with hysteresis. Additionally, the ISL6551
includes high current high-side and low-side totem-pole
drivers to avoid additional external drivers for moderate gate
capacitance (up to 1.6nF at 1MHz) applications, an
uncommitted high bandwidth (10MHz) error amplifier for
feedback loop compensation, a precision bandgap reference
with ±1.5% (ISL6551AB) or ±1% (ISL6551IB) tolerance over
recommended operating conditions, and a ±5% “in
regulation” monitor.
In addition to the ISL6551, other external elements such as
transformers, pulse transformers, capacitors, inductors and
Schottky or synchronous rectifiers are required for a
complete power supply solution. A detailed 200W telecom
power supply reference design using the ISL6551 with
companion Intersil ICs, Supervisor And Monitor ISL6550 and
Half-bridge Driver HIP2100, is presented in Application Note
AN1002.
• Current Mode Control Compatible
• High Current High-Side and Low-Side Totem-Pole Drivers
• Adjustable Resonant Delay for ZVS
• 10MHz Error Amplifier Bandwidth
• Programmable Soft-Start
• Precision Bandgap Reference
• Latching Shutdown Input
• Non-latching Enable Input
• Adjustable Leading Edge Blanking
• Adjustable Dead Time Control
• Adjustable Ramp for Slope Compensation
• Fast Short-Circuit Protection (Hiccup Mode)
• Adjustable Cycle-by-Cycle Peak Current Limiting
• Drive Signals to Implement Synchronous Rectification
• VDD Under-voltage Lockout
• Current Share Support
• ±5% “In Regulation” Indication
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Full-Bridge and Push-Pull Converters
• Power Supplies for Off-line and Telecom/Datacom
• Power Supplies for High End Microprocessors and
Servers
In addition, the ISL6551 can also be designed in push-pull
converters using all of the features except the two upper
drivers and adjustable resonant delay features.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6551
Ordering Information
PART
NUMBER
Ordering Information (Continued)
TEMP
RANGE (°C)
PKG.
DWG. #
PACKAGE
ISL6551IB
0 to 85
28 Ld SOIC
M28.3
ISL6551IB-T
0 to 85
Tape & Reel
M28.3
ISL6551IBZ (Note)
0 to 85
28 Ld SOIC (Pb-free) M28.3
ISL6551IBZ-T
(Note)
0 to 85
Tape & Reel (Pb-free) M28.3
ISL6551IR
0 to 85
28 Ld 6x6 QFN
L28.6x6
ISL6551IR-T
0 to 85
Tape & Reel
L28.6x6
ISL6551ABZ (Note)
-40 to 105
28 Ld SOIC (Pb-free) M28.3
ISL6551ABZ-T
(Note)
-40 to 105
Tape & Reel (Pb-free) M28.3
PART
NUMBER
TEMP
RANGE (°C)
ISL6551ARZ (Note)
-40 to 105
28 Ld 6x6 QFN
(Pb-free)
ISL6551ARZ-T
(Note)
-40 to 105
Tape & Reel (Pb-free) L28.6x6
ISL6551EVAL1
PKG.
DWG. #
PACKAGE
L28.6x6
Evaluation Platform (ISL6551IR only)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinouts
CT
2
27
VDDP1
CT
VSS
VDD
VDDP1
VDDP2
PGND
28 PIN (QFN)
TOP VIEW
RD
28 PIN WIDE BODY (SOIC)
TOP VIEW
RD
3
26
VDDP2
28
27
26
25
24
23
22
R_RESDLY
4
25
PGND
R_RA
5
24
UPPER1
ISENSE
6
23
UPPER2
VSS
1
28
VDD
R_RESDLY
1
21
UPPER1
R_RA
2
20
UPPER2
LOWER1
PKILIM
4
18
LOWER2
R_LEB
9
20
SYNC1
CS_COMP
10
19
SYNC2
BGREF
5
17
SYNC1
CSS
R_LEB
6
16
SYNC2
CS_COMP
7
15
ON/OFF
11
18
ON/OFF
EANI 12
17
DCOK
EAI 13
16
LATSD
14
15
SHARE
EAO
8
9
10
11
12
13
14
DCOK
19
LATSD
3
SHARE
ISENSE
LOWER2
EAO
LOWER1
21
EAI
22
8
EANI
7
CSS
PKILIM
BGREF
Functional Pin Description
PACKAGE PIN #
SOIC
QFN
PIN SYMBOL
1
26
VSS
2
27
CT
Set the oscillator frequency, up to 1MHz.
3
28
RD
Adjust the clock dead time from 50ns to 1000ns.
4
1
R_RESDLY
Program the resonant delay from 50ns to 500ns.
5
2
R_RA
6
3
ISENSE
The pin receives the current information via a current sense transformer or a power resistor.
7
4
PKILIM
Set the over current limit with the bandgap reference as the trip threshold.
8
5
BGREF
Precision bandgap reference, 1.263V ±2% overall recommended operating conditions.
2
FUNCTION
Reference ground. All control circuits are referenced to this pin.
Adjust the ramp for slope compensation (from 50mV to 250mV).
FN9066.4
July 8, 2005
ISL6551
Functional Pin Description (Continued)
PACKAGE PIN #
SOIC
QFN
PIN SYMBOL
9
6
R_LEB
10
7
CS_COMP
11
8
CSS
Program the rise time and the clamping voltage with a capacitor and a resistor, respectively.
12
9
EANI
Non-inverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).
13
10
EAI
Inverting input of Error Amp. It receives the feedback voltage.
14
11
EAO
Output of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).
15
12
SHARE
This pin is the SHARE BUS connecting with other unit(s) for current share operation.
16
13
LATSD
The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD.
17
14
DCOK
Power Good indication with a ±5% window.
18
15
ON/OFF
19, 20
16, 17
SYNC2, SYNC1
21, 22
18, 19
LOWER2, LOWER1
Both lower drivers are PWM-controlled on the trailing edge.
23, 24
20, 21
UPPER2, UPPER1
Both upper drivers are driven at a fixed 50% duty cycle.
25
22
PGND
26, 27
23, 24
VDDP2, VDDP1
Power is delivered to both the upper and the lower drivers through these pins.
28
25
VDD
Power is delivered to all control circuits including SYNC1 & SYNC2 via this pin.
3
FUNCTION
Program the leading edge blanking from 50ns to 300ns.
Set a low current sharing loop bandwidth with a capacitor.
This is an Enable pin that controls the states of all drive signals and the soft-start.
These are the gate control signals for the output synchronous rectifiers.
Power Ground. High current return paths for both the upper and the lower drivers.
FN9066.4
July 8, 2005
ISL6551
BANDGAP
REFERENCE
BGREF
11 CSS
16 LATSD
28 VDD
18 ON/OFF
Functional Block Diagram
SHUTDOWN
SHUTDOWN
LATCH
LATCH
UVLO
SOFT
SOFTSTART
START
8
PKILIM 7
SHUTDOWN
SHUTDOWN
27 VDDP1
UPPER1
DRIVER
24 UPPER1
R_LEB 9
R_RESDLY 4
RESODLY
UPPER2
DRIVER
LEB
ISENSE 6
R_RA 5
CT 2
RD 3
EAO 14
RAMP
ADJUST
26 VDDP2
CLOCK
GENERATOR
PWM
LOGIC
ERROR AMP
(See Fig. 4)
EAI 13
EANI 12
23 UPPER2
22 LOWER1
LOWER2
DRIVER
21 LOWER2
CURRENT
SHARE
DC OK
25 PGND
20 SYNC1
19 SYNC2
15 SHARE
VSS
10 CS_COMP
1
17 DCOK
CIRCUITS REFERENCED TO VSS
LOWER1
DRIVER
CIRCUITS REFERENCED TO PGND
EXTERNAL SINGLE POINT CONNECTION REQUIRED
4
FN9066.4
July 8, 2005
ISL6551
Absolute Maximum Ratings
Thermal Information
Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . . -0.3 to 16V
Enable Inputs (ON/OFF, LATSD) . . . . . . . . . . . . . . . . . . . . . . . . VDD
Power Good Sink Current (IDCOK) . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .250V
Thermal Resistance
θJA (°C/W)
θJC (°C/W)
QFN Package (Notes 1, 3). . . . . . . . . .
30
2.5
SOIC Package (Note 2) . . . . . . . . . . . .
55
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range
ISL6551IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
ISL6551AB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C
Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . 10.8V to 13.2V
Supply Voltage Range, VDDP1 & VDDP2 . . . . . . . . . . . . . . . <13.2V
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379 for details.
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for VDD = VDDP = 12V and TA = 0°C to 85°C (ISL6551IB) or -40°C to 105°C
(ISL6551AB), Unless Otherwise Stated
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY (VDD, VDDP1, VDDP2)
Supply Voltage
VDD
10.8
12.0
13.2
V
Bias Current from VDD (ISL6551IB)
IDD
VDD = 12V (not including drivers current at VDDP)
5
13
18
mA
Bias Current from VDD (ISL6551AB)
IDD
VDD = 12V (not including drivers current at VDDP)
3
20
mA
Total Current from VDD and VDDP
ICC
VDD = VDDP = 12V, F = 1MHz, 1.6nF Load
60
mA
UNDER VOLTAGE LOCKOUT (UVLO)
Start Threshold (ISL6551IB)
VDDON
9.2
Start Threshold (ISL6551AB)
VDDON
9.16
Stop Threshold (ISL6551IB)
VDDOFF
8.03
Stop Threshold (ISL6551AB)
VDDOFF
7.98
Hysteresis (ISL6551IB)
VDDHYS
0.3
Hysteresis (ISL6551AB)
VDDHYS
9.6
9.9
V
9.94
V
8.87
V
8.92
V
1.9
V
0.27
1.93
V
8.6
1
CLOCK GENERATOR (CT, RD)
Frequency Range
Dead Time Pulse Width (Note 4)
F
VDD = 12V (Figure 2)
100
1000
kHz
DT
VDD = 12V (Figure 3)
50
1000
ns
BANDGAP REFERENCE (BGREF)
Bandgap Reference Voltage
(ISL6551IB)
VREF
VDD = 12V, 399kΩ pull-up, 0.1µF, after trimming
1.250
1.263
1.280
V
Bandgap Reference Voltage
(ISL6551AB)
VREF
VDD = 12V, 399kΩ pull-up, 0.1µF, after trimming
1.244
1.263
1.287
V
Bandgap Reference Output Current
IREF
VDD = 12V, see Block/Pin Functional Descriptions
for details
100
µA
5
FN9066.4
July 8, 2005
ISL6551
Electrical Specifications
These specifications apply for VDD = VDDP = 12V and TA = 0°C to 85°C (ISL6551IB) or -40°C to 105°C
(ISL6551AB), Unless Otherwise Stated (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM DELAYS (Note 4)
LOW1,2 delay “Rising”
LOWR
With respect to RESDLY rising
5
ns
LOW1,2 delay “Falling”
LOWF
Compare Delay @ Verror = Vramp
44
ns
SYNC1,2 delay “Falling”
SYNCF
With respect to RESDLY falling and with 20pF load
18
ns
SYNC1,2 delay “Rising”
SYNCR
With respect to CLK rising and with 20pF load
20
ns
UGBW
10
MHz
DC Gain
DCG
79
dB
Maximum Offset Error Voltage
Vos
ERROR AMPLIFIER (EANI, EAI, EAO) (Note 4)
Unity Gain Bandwidth
Input Common Mode Range
Vcm
Common Mode Rejection Ratio
CMMR
Power Supply Rejection Ratio
PSSR
Maximum Output Source Current
ISRC
Maximum Lower Saturation Voltage
Vsatlow
3.1
VDD = 12V
0.4
1mA load
9
mV
V
82
dB
95
dB
2
mA
Sinking 0.27mA
125
mV
1000
kHz
RAMP ADJUST (R_RA) (Note 4)
Ramp Frequency
F
Linear Voltage Ramp, Minimum
100
LVR
50
mV
Linear Voltage Ramp, Maximum
250
mV
Overall Variation
25
%
PEAK CURRENT LIMIT (PKILIM)
Peak Current Shutdown Threshold
IpkThr
Peak Current Shutdown Delay
(Note 4)
IpkDel
BGREF = 0.1µF, 399kΩ pull-up
1.25
1.263
1.31
75
V
ns
SOFT-START (CSS)
8
12
µA
Idis
1.6
5.2
mA
Cycle-by-Cycle Current Limit
(ISL6551IB)
Vclamp
2
8
V
Cycle-by-Cycle Current Limit
(ISL6551AB)
Vclamp
1.9
8.1
V
Charge Current
Iss
Discharge Current
Vcss = 0.6V
DRIVERS (UPPER1, UPPER2, LOWER1, LOWER2)
Maximum Capacitive Load (each)
CL
VDD = VDDP = 12V, F = 1MHz,
Thermal Dependence
Turn On Rise Time (ISL6551IB)
Tr
1.0nF Capacitive load
8.9
16
ns
Turn On Rise Time (ISL6551AB)
Tr
1.0nF Capacitive load
9.2
17
ns
Turn Off Fall Time (ISL6551IB)
Tf
1.0nF Capacitive load
6.4
10
ns
Turn Off Fall Time (ISL6551AB)
Tf
1.0nF Capacitive load
12
ns
Shutdown Delay (Note 4)
TSD
1.0nF Capacitive load
14.5
ns
Rising Edge Delay (Note 4)
TRD
1.0nF Capacitive load
16.4
ns
Falling Edge Delay (Note 4)
TFD
1.0nF Capacitive load
13.7
ns
Vsat_sourcing
Vsat_high
6
1600
pF
Sourcing 20mA
1.00
V
Sourcing 200mA
1.35
V
FN9066.4
July 8, 2005
ISL6551
Electrical Specifications
These specifications apply for VDD = VDDP = 12V and TA = 0°C to 85°C (ISL6551IB) or -40°C to 105°C
(ISL6551AB), Unless Otherwise Stated (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Vsat_sinking (ISL6551IB)
Vsat_low
Sinking 20mA
0.035
V
Sinking 200mA
0.31
V
Vsat_sinking (ISL6551AB)
Vsat_low
Sinking 20mA
0.04
V
Sinking 200mA
0.5
V
SYNCHRONOUS SIGNALS (SYNC1, SYNC2)
Maximum capacitive load (each)
VDD = 12, F = 1MHz
20
pF
PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 4)
Resonant Delay Adjust Range
(Figure 7)
Resonant Delay
tRESDLY
50
R_RESDLY = 10K
55
R_RESDLY = 120K
Leading Edge Blanking Adjust
Range
(Figure 8)
Leading Edge Blanking
tLEB
500
ns
488
50
ns
ns
300
ns
R_LEB = 20K
64
ns
R_LEB = 140K
302
ns
R_LEB = 12V
0
ns
LATCHING SHUTDOWN (LATSD)
Fault Threshold
VIN
Fault_NOT Threshold
VINN
Time to Set latch (Note 4)
TSET
3
V
1.9
415
V
ns
ON/OFF (ONOFF)
Turn-off Threshold
OFF
Turn-on Threshold
ON
0.8
2
V
V
CURRENT SHARE (SHARE, CS_COMP) (Note 4)
Voltage Offset Between Error Amp
Voltage of Master and Slave
Vcs_offset
SHARE = 30K
30
mV
Maximum Source Current To
External Reference
Ics_source
SHARE = 30K
190
µA
SHARE = 30K, Rsource = 1K,
OUTPUT REFERENCE = 1 to 5V,
(See Figure 10)
190
mV
CS_COMP = 0.1µF
500
Hz
Maximum Correctable Deviation In
Reference Voltage Between Master
and Slave
Share/Adjust Loop Bandwidth
CS BW
DC OK (DCOK)
Sink Current
IDCOK
VSATDCOK IDCOK = 5mA
Saturation Voltage
Input Reference
Vref_in
1
5
mA
0.4
V
5
V
Threshold (relative to Vref_in)
OV
(Figure 11)
5
%
Recovery (relative to Vref_in)
OV
(Figure 11)
3
%
Threshold (relative to Vref_in)
UV
(Figure 11)
-5
%
Recovery (relative to Vref_in)
UV
(Figure 11)
-3
%
Transient Rejection (Note 4)
TRej
250
µs
100mV transient on Vout (system implicit rejection
and feedback network dependence (Figure 12)
NOTE:
4. Guaranteed by design. Not 100% tested in production.
7
FN9066.4
July 8, 2005
ISL6551
Drive Signals Timing Diagrams
CLOCK
UPPER1
UPPER2
SYNC1
SYNC2
LOWER1
EAO
ILOWER1
LOWER2
EAO
ILOWER2
EAO
RAMP ADJUST
OUTPUT TO
PWM
LOGIC
T2
T1
T3
T4
T5
NOTES:
T1 = Leading edge blanking
T2 = T4 = Resonant delay
T3 = T5 = dead time
In the above figure, the values for T1 through T5 are exaggerated for demonstration purposes.
Timing Diagram Descriptions
The two upper drivers (UPPER1 and UPPER2) are driven at
a fixed 50% duty cycle and the two lower drivers (LOWER1
and LOWER2) are PWM-controlled on the trailing edge,
while the leading edge employs resonant delay (T2 and T4).
In current mode control, the sensed switch (FET) current
(ILOWER1 and ILOWER2) is processed in the Ramp Adjust
and Leading Edge Blanking (LEB) circuits and then compared
to a control signal (EAO). Spikes, due to parasitic elements in
the bridge circuit, would falsely trigger the comparator
generating the PWM signal. To prevent false triggering, the
leading edge of the sensed current signal is blanked out by
T1, which can be programmed at the R_LEB pin with a
resistor. Internal switches gate the analog input to the PWM
comparator, implementing the blanking function that
eliminates response degrading delays which would be caused
8
if filtering of the current feedback was incorporated. The dead
time (T3 and T5) is the delay to turn on the upper FET
(UPPER1/UPPER2) after its corresponding lower FET
(LOWER1/LOWER2) is turned off when the bridge is
operating at maximum duty cycle in normal conditions, or is
responding to load transients or input line dipping conditions.
Therefore, the upper and lower FETs that are located at the
same side of the bridge can never be turned on together, which
eliminates shoot-through currents. SYNC1 and SYNC2 are the
gate control signals for the output synchronous rectifiers. They
are biased by VDD and are capable of driving capacitive loads
up to 20pF at 1MHz clock frequency (500kHz switching
frequency). External drivers with high current capabilities are
required to drive the synchronous rectifiers, cascading with
both synchronous signals (SYNC1 and SYNC2).
FN9066.4
July 8, 2005
ISL6551
Shutdown Timing Diagrams
LATCH CANNOT BE RESET BY ON/OFF
C
LATSD
D
ON/OFF
A
E
VDDON
VDD
LATCH RESET BY
REMOVING VDD
PKILIM > BGREF
B
F
VDDOFF
PKILIM < BGREF
ILIM_OUT
SOFT
START
DRIVER
ENABLE
SOFT-START
SHUTDOWN
FAULT
FAULT
OFF
OVER
CURRENT
LATCHED
OFF/ON
LATCH
RESET
UNDER VOLTAGE
LOCKOUT
Shutdown Timing Descriptions
A (ON/OFF) - When the ON/OFF is pulled low, the soft-start
capacitor is discharged and all the drivers are disabled.
When the ON/OFF is released without a fault condition, a
soft-start is initiated.
B (OVERCURRENT) - If the output of the converter is over
loaded, i.e., the PKILIM is above the bandgap reference
voltage (BGREF), the soft-start capacitor is discharged very
quickly and all the drivers are turned off. Thereafter, the softstart capacitor is charged slowly, and discharged quickly if
the output is overloaded again. The soft-start will remain in
hiccup mode as long as the overload conditions persist.
Once the overload is removed, the soft-start capacitor is
charged up and the converter is then back to normal
operation.
E (LATCH RESET) - The latch is reset by removing the
VDD. The soft-start capacitor starts to be charged after VDD
increases above the turn-on threshold VDDON.
F (VDD UVLO) - The IC is turned off when the VDD is below
the turn-off threshold VDDOFF. Hysteresis VDDHYS is
incorporated in the undervoltage lockout (UVLO) circuit.
C (LATCHING SHUTDOWN) - The IC is latched off
completely as the LATSD pin is pulled high, and the soft-start
capacitor is reset.
D (ON/OFF) - The latch cannot be reset by the ON/OFF.
9
FN9066.4
July 8, 2005
ISL6551
Block/Pin Functional Descriptions
Detailed descriptions of each individual block in the functional
block diagram on page 3 are included in this section.
Application information and design considerations for each pin
and/or each block are also included.
• IC Bias Power (VDD, VDDP1, VDDP2)
- The IC is powered from a 12V ± 10% supply.
- VDD supplies power to both the digital and analog circuits
and should be bypassed directly to the VSS pin with an
0.1µF low ESR ceramic capacitor.
- VDDP1 and VDDP2 are the bias supplies for the upper
drivers and the lower drivers, respectively. They should be
decoupled with ceramic capacitors to the PGND pin.
- Heavy copper should be attached to these pins for a better
heat spreading.
• IC GNDs (VSS, PGND)
- VSS is the reference ground, the return of VDD, of all
control circuits and must be kept away from nodes with
switching noises. It should be connected to the PGND in
only one location as close to the IC as practical. For a
secondary side control system, it should be connected to
the net after the output capacitors, i.e., the output return
pinout(s). For a primary side control system, it should be
connected to the net before the input capacitors, i.e., the
input return pinout(s).
- PGND is the power return, the high-current return path of
both VDDP1 and VDDP2. It should be connected to the
SOURCE pins of two lower power switches or the
RETURNs of external drivers as close as possible with
heavy copper traces.
- Copper planes should be attached to both pins.
RD
• Undervoltage Lockout (UVLO)
- UVLO establishes an orderly start-up and verifies that VDD
is above the turn-on threshold voltage (VDDON). All the
drivers are held low during the lockout. UVLO incorporates
hysteresis VDDHYS to prevent multiple startup/shutdowns
while powering up.
- UVLO limits are not applicable to VDDP1 and VDDP2.
• Bandgap Reference (BGREF)
- The reference voltage VREF is generated by a precision
bandgap circuit.
- This pin must be pulled up to VDD with a resistance of
approximately 399kΩ for proper operation. For additional
reference loads (no more than 1mA), this pull-up resistor
should be scaled accordingly.
- This pin must also be decoupled with an 0.1µF low ESR
ceramic capacitor.
• Clock Generator (CT, RD)
- This free-running oscillator is set by two external
components as shown in Figure 1. A capacitor at CT is
charged and discharged with two equal constant current
sources and fed into a window comparator to set the clock
frequency. A resistor at RD sets the clock dead time. RD
and CT should be tied to the VSS pin on their other ends
as close as possible. The corresponding CT for a particular
frequency can be selected from Figure 2.
- The switching frequency (Fsw) of the power train is half of
the clock frequency (Fclock), as shown in Equation 1.
Fclock
Fsw = ------------------2
(EQ. 1)
SET CLOCK
DEAD TIME (DT)
RD
VDD-
I_CT
VMAX
+
OUT
CT
CLK
S
CT
VMIN
- OUT
+
R
Q
Q
Q
Q
I_CT
CLK
DT
DT
FIGURE 1. SIMPLIFIED CLOCK GENERATOR CIRCUIT
10
FN9066.4
July 8, 2005
ISL6551
2
3,000
DEAD TIME (µs)
0°C
60°C
2,500
120°C
F (kHz)
2,000
1,500
1,000
1.6
1.2
0.8
0.4
0
0
20
40
500
60
80
100
120
140
160
RD (kΩ)
FIGURE 3. RD vs DEAD TIME (VDD = 12V)
0
10
100
CT (pF)
1,000
10,000
RECOMMENDED RANGE
FIGURE 2. CT vs FREQUENCY
- Note that the capacitance of a scope probe (~12pF for
single ended) would induce a smaller frequency at the
CT pin. It can be easily seen at a higher frequency. An
accurate operating frequency can be measured at the
outputs of the bridge/synchronous drivers.
- The dead time is the delay to turn on the upper FET
(UPPER1/UPPER2) after its corresponding lower FET
(LOWER1/LOWER2) is turned off when the bridge is
operating at maximum duty cycle in normal conditions,
or is responding to load transients or input line dipping
conditions. This helps to prevent shoot through between
the upper FET and the lower FET that are located at the
same side of the bridge. The dead time can be
estimated using Equation 2:
M × RD
DT = -------------------kΩ
(EQ. 2)
(ns)
where M=11.4(VDD=12V), 11.1(VDD=14V), and
12(VDD=10V), and RD is in kΩ. This relationship is
shown in Figure 3.
• Error Amplifier (EAI, EANI, EAO)
- This amplifier compares the feedback signal received at
the EAI pin to a reference signal set at the EANI pin and
provides an error signal (EAO) to the PWM Logic. The
feedback loop compensation can be programmed via
these pins.
- Both EANI and EAO are clamped by the voltage
(Vclamp) set at the CSS pin, as shown in Figure 4. Note
that the diodes in the functional block diagram represent
the clamp function of the CSS in a simplified way.
• Soft-Start (CSS)
- The voltage on an external capacitor charged by an
internal current source ISS is fed into a control pin on
the error amplifier. This causes the Error Amplifier to: 1)
limit the EAO to the soft-start voltage level; and 2) override the reference signal at the EANI with the soft-start
voltage, when the EANI voltage is higher than the softstart voltage. Thus, both the output voltage and current
of the power supply can be controlled by the soft-start.
- The clamping voltage determines the cycle-by-cycle
peak current limiting of the power supply. It should be
set above the EANI and EAO voltages and can be
programmed by an external resistor as shown in
Figure 4 using Equation 3.
Vclamp = Rcss • Iss
400mV
VDD
CSS
+
-
(See Fig. 9)
SSL
(TO
BLANKING
CIRCUIT)
(EQ. 3)
(V)
EAI
(–)
Iss
EANI
(+)
RCSS
SHUTDOWN
ERROR AMP
EAO
FIGURE 4. SIMPLIFIED CLAMP/SOFT-START
11
FN9066.4
July 8, 2005
ISL6551
- Per Equation 3, the clamping voltage is a function of the
charge current Iss. For a more predictable clamping
voltage, the CSS pin can be connected to a referencebased clamp circuit as shown in Figure 5. To make the
Vclamp less dependent on the soft-start current (Iss),
the currents flowing through R1 and R2 should be
scaled much greater than Iss. The relationship of this
circuit can be found in Equation 4.
in a short-circuit condition. The limit can be set with a
resistor divider from the ISENSE pin. The resistor divider
relationship is defined in Equation 7.
- In general, the trip point is a little smaller than the BGREF
due to the noise and/or ripple at the BGREF.
RUP
ISENSE
PKILIM
VREF
RDOWN
R1
CSS
FIGURE 6. PEAK CURRENT LIMIT SET CIRCUIT
R2
Rdown
BGREF
-------------------------------------- = ----------------------------------------Rdown + Rup
ISENSE ( max )
FIGURE 5. REFERENCE-BASED CLAMP CIRCUIT
R1 × R2
R2
Vclamp ≈ Iss • ---------------------- + Vref • ---------------------R1 + R2
R1 + R2
(EQ. 4)
- The soft-start rise time (Tss) can be calculated with
Equation 5. The rise time (Trise) of the output voltage is
approximated with Equation 6.
Vclamp × Css
T ss = --------------------------------------Iss
(s)
EANI × Css
T rise = -------------------------------Iss
(s)
(EQ. 5)
(EQ. 6)
• Drivers (Upper1, Upper2, Lower1, Lower2)
- The two upper drivers are driven at a fixed 50% duty
cycle and the two lower drivers are PWM-controlled on
the trailing edge while the leading edge employs resonant
delay. They are biased by VDDP1 and VDDP2,
respectively.
- Each driver is capable of driving capacitive loads up to CL
at 1MHz clock frequency and higher loads at lower
frequencies on a layout with high effective thermal
conductivity.
- The UVLO holds all the drivers low until the VDD has
reached the turn-on threshold VDDON.
- The upper drivers require assistance of external levelshifting circuits such as Intersil’s HIP2100 or pulse
transformers to drive the upper power switches of a bridge
converter.
• Peak Current Limit (PKILIM)
- When the voltage at PKILIM exceeds the BGREF voltage,
the gate pulses are terminated and held low until the next
clock cycle. The peak current limit circuit has a high-speed
loop with propagation delay IpkDel. Peak current
shutdown initiates a soft-start sequence.
- The peak current shutdown threshold is usually set slightly
higher than the normal cycle-by-cycle PWM peak current
limit (Vclamp) and therefore will normally only be activated
12
(EQ. 7)
• Latching Shutdown (LATSD)
- A high TTL level on LATSD latches the IC off. The IC goes
into a low power mode and is reset only after the power at
the VDD pin is removed completely. The ON/OFF cannot
reset the latch.
- This pin can be used to latch the power supply off on
output overvoltage or other undesired conditions.
• ON/OFF (ON/OFF)
- A high standard TTL input (safe also for VDD level) signals
the controller to turn on. A low TTL input turns off the
controller and terminates all drive signals including the
SYNC outputs. The soft-start is reset.
- This pin is a non-latching input and can accept an enable
command when monitoring the input voltage and the
thermal condition of a converter.
• Resonant Delay (R_RESDLY)
- A resistor tied between R_RESDLY and VSS determines
the delay that is required to turn on a lower FET after its
corresponding upper FET is turned off. This is the resonant
delay, which can be estimated with Equation 8.
tRESDLY = 4.01 x R_RESDLY/kΩ + 13 (ns)
(EQ. 8)
- Figure 7 illustrates the relationship of the value of the
resistor (R_RESDLY) and the resonant delay (tRESDLY).
The percentages in the figure are the tolerances at the two
end points of the curve.
FN9066.4
July 8, 2005
ISL6551
500
incorporated. The current ramp is blanked out during the
resonant delay period because no switching occurs in the
lower FETs. The leading edge blanking function will not be
activated until the soft-start (CSS) reaches over 400mV, as
illustrated in Figures 4 and 9. The leading edge blanking
(LEB) function can be disabled by tying the R_LEB pin to
VDD, i.e., LEB=1. Never leave the pin floating.
- The blanking time can be estimated with Equation 9,
whose relationship can be seen in Figure 8. The
percentages in the figure are the tolerances at the two
endpoints of the curve.
+18%
450
-24%
tRESDLY (ns)
400
350
300
250
200
150
+37%
100
+4%
50
0
20
40
60
80
100
tLEB = 2 x R_LEB / kΩ + 15 (ns)
120
(EQ. 9)
R_RESDLY (kΩ)
FIGURE 7. R_RESDLY vs RESDLY
300
• Leading Edge Blanking (R_LEB)
- In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent
false triggering, the leading edge of the sensed current
signal is blanked out by a period that can be programmed
with the R_LEB resistor. Internal switches gate the analog
input to the PWM comparator, implementing the blanking
function that eliminates response degrading delays which
would be caused if filtering of the current feedback was
250
0.1µ
+20%
-18%
tLEB (ns)
200
150
100
50
+51%
-11%
0
20
40
60
80
100
120
140
R_LEB (kΩ)
FIGURE 8. R_LEB vs tLEB
VDD
ADJ_RAMP
ADJ_RAMP
399K
200mV
RAMP_OUT
(TO PWM
COMPARATOR)
BGREF
R_RA
ISENSE
0
RAMP_OUT
200mV
R_RA
BLANK
ADD RAMP
+
ISENSE
200mV
R_LEB
SET
BLANKING
TIME
R_LEB
RESDLY
LEB
SSL
(See Fig. 4)
RESDLY
LEB
SSL
RAMP_OUT
0
X
X
BLANK
X
0
0
BLANK
1
1
X
NO BLANK
1
X
1
NO BLANK
FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
13
FN9066.4
July 8, 2005
ISL6551
synchronous rectifiers. When using these drive
schemes, the user should understand the issues that
might occur in his/her applications, especially the
impacts on current share operation and light load
operation. Refer to application note AN1002 for more
details.
- External high current drivers controlled by the
synchronous signals are required to drive the
synchronous rectifiers. A pulse transformer is required
to pass the drive signals to the secondary side if the IC
is used in a primary control system.
• Ramp Adjust (R_RA, ISENSE)
- The ramp adjust block adds an offset component
(200mV) and a slope adjust component to the ISENSE
signal before processing it at the PWM Logic block, as
shown in Figure 9. This ensures that the ramp voltage is
always higher than the OAGS (ground sensing opamp)
minimum voltage to achieve a “zero” state.
- It is critical that the input signal to ISENSE decays to
zero prior to or during the clock dead time. The levelshifting and capacitive summing circuits in the RAMP
ADJUST block are reset during the dead time. Any input
signal transitions that occur after the rising edge of CLK
and prior to the rising edge of RESDLY can cause
severe errors in the signal reaching the PWM
comparator.
- Typical ramp values are hundreds of mV over the period
on a 3V full scale current. Too much ramp makes the
controller look like a voltage mode PWM, and too little
ramp leads to noise issues (jitter). The amount of ramp
(Vramp), as shown in Figure 9, is programmed with the
R_RA resistor and can be calculated with Equation 10.
Vramp = BGREF x dt /(R_RA x 500E-12) (V)
• Share Support (SHARE, CS_COMP)
- The unit with the highest reference is the master. Other
units, as slaves, adjust their references via a source
resistor to match the master reference sharing the load
current. The source resistor is typically 1kΩ connecting
the EANI pin and the OUTPUT REFERENCE (external
reference or BGREF), as shown in Figure 10. The share
bus represents a 30kΩ resistive load per unit, up to 10
units.
- The output (ADJ) of “Operational Transconductance
Amplifier (OTA)” can only pull high and it is floating while
in master mode. This ensures that no current is sourced
to the OUTPUT REFERENCE when the IC is working
by itself.
- The slave units attempt to drive their error amplifier
voltage to be within a pre-determined offset (30mV
typical) of the master error voltage (the share bus). The
current-share error is nominally (30mV/EAO)*100%
assuming no other source of error. With a 2.5V full load
error amp voltage, the current-share error at full load
would be -1.2% (slaves relative to master).
- The bandwidth of the current sharing loop should be
much lower than that of the voltage loop to eliminate
noise pick-up and interactions between the voltage
regulation loop and the current loop. A 0.1µF capacitor
is recommended between CS_COMP and VSS pins to
achieve a low current sharing loop bandwidth (100Hz to
500Hz).
(EQ. 10)
where dt = Duty Cycle / Fsw - tLEB (s). Duty cycle is
discussed in detail in application note AN1002.
- The voltage representation of the current flowing
through the power train at ISENSE pin is normally
scaled such that the desired peak current is less than or
equal to Vclamp-200mV-Vramp, where the clamping
voltage is set at the CSS pin.
• SYNC Outputs (SYNC1, SYNC2)
- SYNC1 and SYNC2 are the gate control signals for the
output synchronous rectifiers. They are biased by VDD
and are capable of driving capacitive loads up to 20pF
at 1MHz clock frequency (500kHz switching frequency).
These outputs are turned off sooner than the turn-off at
UPPER1 and UPPER2 by the clock dead time, DT.
- Inverting both SYNC signals or both LOWER signals is
another possible way to control the drivers of the
CS_COMP
0.1µF
30mV
+
-
+
-
EAO
+
OTA
1K
ADJ
EANI
(+)
OUTPUT
REFERENCE
SHARE
30K
FIGURE 10. SIMPLIFIED CURRENT SHARE CIRCUIT
14
FN9066.4
July 8, 2005
ISL6551
• Power Good (DCOK)
- DCOK pin is an open drain output capable of sinking
5mA. It is low when the output voltage is within the
UVOV window. The static regulation limit is ±3%, while
the ±5% is the dynamic regulation limit. It indicates
power good when the EAI is within -3% to +5% on the
rising edge and within +3% to -5% on the falling edge, as
shown in Figure 11.
18K
EAI
VOUT
1K
EANI
R
15N
C
+
EAO
1.10V
EAI
VOUT
+5%
1.00V
+3%
EANI
0.90V
-3%
1.05V
-5%
1.00V
EAI
0.95V
FIGURE 12. OUTPUT TRANSIENT REJECTION
DCOK
FAULT
FIGURE 11. UNDERVOLTAGE-OVERVOLTAGE WINDOW
- The DCOK comparator might not be triggered even
though the output voltage exceeds ± 5% limits at load
transients. This is because the feedback network of the
error amplifier filters out part of the transients and the EAI
only sees the remaining portion that is still within the limits,
as illustrated in Figure 12. The lower the “zero (1/RC)” of
the error amplifier, the larger the portion of the transient is
filtered out.
15
• Thermal Pad (in QFN only)
- In the QFN package, the pad underneath the center of
the IC is a “floating” thermal substrate. The PCB
“thermal land” design for this exposed die pad should
include thermal vias that drop down and connect to
one or more buried copper plane(s). This combination
of vias for vertical heat escape and buried planes for
heat spreading allows the QFN to achieve its full
thermal potential. This pad should be connected to a
low noise copper plane such as Vss.
- Refer to TB389 for design guidelines.
FN9066.4
July 8, 2005
ISL6551
Additional Applications Information
Table 1 highlights parameter setting for the ISL6551.
Designers can use this table as a design checklist. For
detailed operation of the ISL6551, see Block/Pin Functional
Descriptions.
TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST
VDD = 12V at room temperature, unless otherwise stated.
PARAMETER
PIN NAME
FORMULA OR SETTING HIGHLIGHT
UNIT
FIGURE #
kHz
1, 2
Frequency
CT
Set 50% Duty Cycle Pulses with a fixed frequency
Dead Time
RD
DT = M x RD/kΩ, where M = 11.4
ns
3
tRESDLY = 4.01 x R_RESDLY/kΩ + 13
ns
7
Vramp = BGREF/(R_RA x 500E-12) x dt
V
-
Resonant Delay
R_RESDLY
Ramp Adjust
R_RA
Current Sense
ISENSE
<Vclamp-200mV-Vramp
V
-
Peak Current
PKILIM
<BGREF and slightly higher than Vclamp
V
6
Bandgap Reference
BGREF
1.263V ±2%, 399kΩ pull-up, No more than 100µA load
V
-
Leading Edge Blanking
R_LEB
tLEB = 2 x R_LEB/kΩ + 15, never leave it floating
ns
8, 9
0.1µ for a low current loop bandwidth (100 - 500Hz)
Hz
10
Current Share Compensation
CS_COMP
Soft-Start & Output Rise Time
CSS
tss = Vclamp x Css/Iss, trise = EANI x CSS / Iss, Iss = 10µA ±20%
S
4
Clamp Voltage (Vclamp)
CSS
Vclamp = Iss x Rcss, or Reference-based clamp
V
4, 5
EANI, EAO < Vclamp
V
-
Error Amplifier
EANI, EAI, EAO
Share Support
SHARE
30K load & a resistor (1K, typ.) between EANI and OUTPUT REF.
-
-
Latching Shutdown
LATSD
Latch IC off at > 3V
V
-
Power Good
DCOK
±5% with hysteresis, Sink up to 5mA, transient rejection
V
11, 12
Turn on/off at TTL level
V
-
Connect to PGND in only one single point
-
-
Single point to VSS plane
-
-
IC Enable
ON/OFF
Reference Ground
VSS
Power Ground
PGND
Upper Drivers
UPPER1, UPPER2 Capacitive load up to 1.6nF at Fsw = 500kHz
-
-
Lower Drivers
LOWER1, LOWER2 Capacitive load up to 1.6nF at Fsw = 500kHz
-
-
Capacitive load up to 20pF at Fsw = 500kHz
-
-
12V ±10%, 0.1µF decoupling capacitor
V
-
Need decoupling capacitors
V
-
Synchronous Drive Signals
SYNC1, SYNC2
Bias for Control Circuits
VDD
Biases for Bridge Drivers
VDDP1, VDDP2
16
FN9066.4
July 8, 2005
ISL6551
reference design, which can be found in the Application Note
AN1002. To meet the specifications of the power supply,
minor modifications of each block are required. To take full
advantage of the integrated features of the ISL6551,
“secondary side control” is recommended.
Figure 13 shows the block diagram of a power supply
system employing the ISL6551 full bridge controller. The
ISL6551 not only is a full bridge PWM controller but also can
be used as a push-pull PWM controller. Users can design a
power supply by selecting appropriate blocks in the “System
Blocks Chart” based on the power system requirements.
Figures 13A, 14A, 15A, 16A, 17A, 18A, 19, 20A, 21, 22A,
and 24A have been used in the 200W telecom power supply
PRIMARY BIAS
BIASES
SECONDARY BIAS
VIN
INPUT
FILTER
PRIMARY
FETs
CURRENT
SENSE
PRIMARY FET
DRIVERS
MAIN
TRANSFORMER
ISL6551
CONTROLLER
SUPERVISOR
CIRCUITS
RECTIFIERS
OUTPUT
FILTER
VOUT
SECONDARY
DRIVERS
FEEDBACK
FIGURE 13. BLOCK DIAGRAM OF A POWER SUPPLY SYSTEM USING ISL6551 CONTROLLER
System Blocks Chart
Input Filters
VIN
General - Input capacitors are required to absorb the
power switch (FET) pulsating currents.
VINF
CIN
FIGURE 13A. GENERAL
VIN
LIN
VINF
EMI - For good EMI performance, the ripple current that is
reflected back to the input line can be reduced by an input
L-C filter, which filters the differential-mode noises and
operates at two times the switching frequency, i.e., the
clock frequency (Fclock). In some cases, an additional
common-mode choke might be required to filter the
common-mode noises.
CIN
FIGURE 13B. EMI
17
FN9066.4
July 8, 2005
ISL6551
Current Sense
Primary FETs
ISENSE
T_CURRENT
VINF
or CURRENT_SEN_P
Q3_S
Q1
Q1_G
P–
Q2
Q2_G
P+
Q4_S
Q3
Q3_G
FIGURE 14A. TWO-LEG SENSE
Q4
Q4_G
Q3_S
Q4_S
FIGURE 15A. FULL BRIDGE
ISENSE
VINF
P1–
P2–
CURRENT_SEN_P
FIGURE 14B. TOP SENSE
Q3
Q3_G
Q4
Q4_G
ISENSE
Q3_S & Q4_S
Q3_S
Q4_S
FIGURE 15B. PUSH-PULL
RSENSE
FIGURE 14C. RESISTOR SENSE (PRIMARY CONTROL)
Two-Leg Sense - Senses the current that flows through both
lower primary FETs. Operates at the switching frequency.
Full Bridge - Four MOSFETs are required for full bridge
converters. The drain to source voltage rating of the
MOSFETs is Vin.
Push-Pull - Only the two lower MOSFETs are required for
push-pull converters. The two upper drivers are not used.
The VDS of the MOSFETs is 2xVin.
Top Sense - Senses the sum of the current that flows through
both upper primary FETs. Operates at the clock frequency.
Resistor Sense - This simple scheme is used in a primary side
control system. The sum of the current that flows through both
lower primary FETs is sensed with a low impedance power
resistor. The sources of Q3 and Q4 and ISENSE should be tied
at the same point as close as possible.
BIASES
Linear Regulator - In a primary side control system, a
linear regulator derived from the input line can be used for
the start-up purpose, and an extra winding coupled with the
main transformer can provide the controller power after the
start up.
DCM Flyback - Use a PWM controller to develop both
primary and secondary biases with discontinuous current
mode flyback topology.
18
FN9066.4
July 8, 2005
ISL6551
Feedback
Rectifiers
SYNCHRONOUS FETs
SCHOTTKY
S+
S+
SYNP
EAO
EAI
VOPOUT
SYNN
S–
S–
FIGURE 17A. CURRENT DOUBLER RECTIFIERS
FIGURE 16A. SECONDARY CONTROL
SYNCHRONOUS FETs
S+
SCHOTTKY
S+
VREF = 5V
VOPOUT
IL207
SYNN
EAO
EAI
TL431
SYNP
S–
S–
FIGURE 17B. CONVENTIONAL RECTIFIERS
FIGURE 16B. PRIMARY CONTROL
S+
Secondary Control - In secondary side control systems,
only a few resistors and capacitors are required to complete
the feedback loop.
Primary Control - This feedback loop configuration for
primary side control systems requires an optocoupler for
isolation. The bandwidth is limited by the optocoupler.
S–
FIGURE 17C. SELF-DRIVEN RECTIFIERS
Current Doubler Rectifiers 1. Synchronous FETs are used for low output voltage, high
output current and/or high efficiency applications.
2. Schottky diodes are used for lower current applications.
Pins S+ and S- are connected to the output filter and the
main transformer with current doubler configurations.
Conventional Rectifiers 1. Synchronous FETs are used for low output voltage, high
output current and/or high efficiency applications.
2. Schottky diodes are used for lower current applications.
Pins S+ and S- are connected to the main transformer
with conventional configurations.
Self-Driven Rectifiers - For low output voltage applications,
both FETs can be driven by the voltage across the
secondary winding. This can work with all kinds of main
transformer configurations as shown in Figures 18A-D.
19
FN9066.4
July 8, 2005
ISL6551
Main Transformers
Supervisor Circuits
S+
P+
(1) INTEGRATED SOLUTION
• Intersil ISL6550 Supervisor And Monitor (SAM). Its QFN
package requires less space than the SOIC package.
P–
S–
FIGURE 18A. FULL BRIDGE AND CURRENT DOUBLER
P+
S+
VOUTF
P–
S–
FIGURE 18B. CONVENTIONAL FULL BRIDGE
P1–
VOPOUT
VREF5
BDAC
VCC
1
20 UVDLY
VOPP
2
VOPM
3
VOPOUT
4
19 OVUVSEN
18 PGOOD
PGOOD
17 START
START
VREF5
5
16 PEN
GND
6
15 VID0
BDAC
7
14 VID1
OVUVTH
8
13 VID2
DACHI
9
12 VID3
DACLO 10
11 VID4
PEN
S+
VINF
or CURRENT_SEN_P
FIGURE 19. ISL6550 SOIC
S–
P2–
FIGURE 18C. PUSH-PULL AND CURRENT DOUBLER
• Over-temperature protection (discrete)
• Input UV lockout (discrete)
(2) DISCRETE SOLUTION
P1–
S+
VINF
or CURRENT_SEN_P
VOUTF
S–
P2–
FIGURE 18D. CONVENTIONAL PUSH-PULL
Full Bridge and Current Doubler - No center tap is
required. The secondary winding carries half of the load, i.e.,
only half of the load is reflected to the primary.
Conventional Full Bridge - Center tap is required on the
secondary side, and no center tap is required on the primary
side. The secondary winding carries all the load. i.e., all the
load is reflected to the primary.
Push-Pull and Current Doubler - Center tap is required on
the primary side, and no center tap is required on the
secondary side. The secondary winding carries half of the
load, i.e., only half of the load is reflected to the primary.
• Differential Amplifier
• VCC undervoltage lockout
• Programmable output OV and UV
• Programmable output
• Status indicators (PGOOD and START)
• Precision Reference
• Ove- temperature protection
• Input UV lockout
The Integrated Solution is much simpler than a discrete
solution. Over-temperature protection and input under
voltage lockout can be added for better system protection
and performance.
The Discrete Solution requires a significant number of
components to implement the features that the ISL6550 can
provide.
Conventional Push-Pull - Both primary and secondary
sides require center taps. The secondary winding carries all
the load, i.e., all the load is reflected to the primary.
20
FN9066.4
July 8, 2005
ISL6551
Output Filter
Secondary Drivers
LOUT
S+
MIC4421BM
VOUT
COUT
SYNC2
IN OUT
/LOWER1
MIC4421BM
SYNP
SYNC1
/LOWER2
IN OUT
GND
GND
S–
SYNN
FIGURE 20A. CURRENT DOUBLER FILTER
FIGURE 22A. INVERTING DRIVERS
LOUT
MIC4422BM
VOUT
VOUTF
FCLOCK
MIC4422BM
COUT
SYNC1
IN OUT
FIGURE 20B. CONVENTIONAL FILTER
SYNP
FIGURE 22B. NON-INVERTING DRIVERS
Conventional Filter - One inductor is needed. The inductor
carries all the load operating at two times the switching
frequency.
IN OUT
T_SYN
Controller
CT 2
27 VDDP1
26 VDDP2
R_RA 5
24 UPPER1
ISENSE 6
23 UPPER2
PKILIM 7
BGREF 8
ICL6551
SOIC
R_LEB 9
22 LOWER1
IN OUT
FSW
SYNN
GND
INPUT
UV & OV
INVERTING
20 SYNC1
19 SYNC2
EAI 13
16 LSTSD
EAO 14
15 SHARE
EAO
SYN2
21 LOWER2
CS_COMP 10
OUTPUT
REFERENCE CSS 11
(BDAC)
EANI 12
EAI
GND
25 PGND
R_RESDLY 4
SYNP
SYN1
28 VDD
RD 3
SYNN
GND
GND
Current Doubler Filter - Two inductors are needed, but they
can be integrated and coupled into one core. Each inductor
carries half of the load operating at the switching frequency.
VSS 1
IN OUT
SYNC2
18 ON / OFF
17 DCOK
LED
NON INVERTING
SYN1
SYNC2/LOWER1
SYNC1
SYN2
SYNC1/LOWER2
SYNC2
IC
MIC4421BM
MIC4422BM
FIGURE 22C. PRIMARY CONTROL
LSTSD
SHARE
BUS
FIGURE 21. ISL6551 CONTROLLER
ISL6551 Controller - It can be used as a full bridge or pushpull PWM controller. The QFN package requires less space
than the SOIC package.
Inverting Drivers - Inverting the SYNC signals or the
LOWER signals with external high current drivers to drive
the synchronous FETs.
Non-inverting Drivers - Cascading SYNC signals with noninverting high current drivers to drive the synchronous FETs.
There is a dead time between SYNC1 and SYNC2. For a
higher efficiency, schottky diodes are normally in parallel
with the synchronous FETs to reduce the conduction losses
during the dead time in high output current applications.
Primary Control - This requires a pulse transformer,
operating at the switching frequency, for isolation. There are
three options to drive the synchronous FETs, as described in
previous lines.
21
FN9066.4
July 8, 2005
ISL6551
Primary FET Drivers
(1) PUSH-PULL DRIVERS
HIP2100IB
Q3_G
HO
Q3_G
HS
LI
VSS LO
Q3_S
HI
LOWER1
Q3_S
Q4_G
LOWER1
Q4_S
Q4_S
LOWER2
LOWER2
Q4_G
FIGURE 23B. PUSH-PULL HIGH CURRENT DRIVERS
FIGURE 23A. PUSH-PULL MEDIUM CURRENT DRIVERS
HIP2100IB
LOWER1
LOWER2
PGND
HO
Q3_G
HS
Q3_S
VSS LO
Q4_G
HI
LI
Q4_S
FIGURE 23C. PUSH-PULL PRIMARY CONTROL
Push-Pull Medium Current Drivers - Upper drivers are not
used. No external drivers are required. Secondary control.
Operate at the switching frequency.
Push-Pull High Current Drivers - Upper drivers are not
used. External high current drivers are required and less
power is dissipated in the ISL6551 controller. Secondary
control. Operate at the switching frequency.
Push-Pull Primary Control - Upper drivers are not used.
Both lower drivers can directly drive the power switches.
External drivers are required in high gate capacitance
applications.
22
FN9066.4
July 8, 2005
ISL6551
(2) FULL BRIDGE DRIVERS
HIP2100IB
HI
Q1_G
Q1_G
P–
HO
HS
LI
VSS LO
Q3_G
UPPER1
P–
UPPER1
Q3_S
UPPER2
P+
UPPER2
HIP2100IB
Q2_G
HI
HO
HS
LI
VSS LO
Q2_G
P+
Q3_G
Q4_G
LOWER1
Q4_S
Q3_S
LOWER1
LOWER2
Q4_S
LOWER2
Q4_G
FIGURE 24B. FULL BRIDGE MEDIUM CURRENT DRIVERS
FIGURE 24A. FULL BRIDGE HIGH CURRENT DRIVERS
HIP2100IB
UPPER1
LOWER1
HI
HO
HS
LI
VSS LO
PGND
Q1G
P–
Q3_G
Q3_S
HIP2100IB
UPPER2
HI
LOWER2
LI
VSS LO
PGND
HO
HS
Q2_G
P+
Q4_G
Q4_S
FIGURE 24C. FULL BRIDGE PRIMARY CONTROL
Full Bridge High Current Drivers - External high current
drivers are required and less power is dissipated in the
ISL6551 controller. Secondary control. Operate at the
switching frequency.
Full Bridge Medium Current Drivers - No external drivers
are required. Secondary control. Operate at the switching
frequency.
Full Bridge Primary Control - Lower drivers can directly
drive the power switches, while upper drivers require the
assistance of level-shifting circuits such as a pulse
transformer or Intersil’s HIP2100 half-bridge driver. External
high current drivers are not required in medium power
applications, but level-shifting circuits are still required for
upper drivers. Operate at the switching frequency.
23
FN9066.4
July 8, 2005
Simplified Typical Application Schematics
SB+48V
SB+12V
SA+12V
LOWER1
VDD
HB
HO
HS
UPPER1
VS VS
OUT IN
OUT NC
GND GND
LO
VSS
LI
HI
SYNC2
3.3Vout
MIC4421
HIP2100
UPPER2
24
SA+12V
LOWER2
VS VS
OUT IN
OUT NC
GND GND
LOWER1
SB+12V
VDD
HB
HO
HS
LOWER2
SYNC1
MIC4421
LO
VSS
LI
HI
+
HIP2100
SA+12V
-
20
19
18
17
16
15
14
13
12
11
V+
+
V-
SA+12V
-
OUT
UVDLY
VCC
OVU VSEN VOPP
PGOOD
VOPM
START VOPOUT
PEN
VREF5
VID0
G ND
BDAC
VID1
OVUVTH
VID2
DACHI
VID3
DACLO
VID4
ISL6550
1.263V
PGND
UPPER1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
UPPER2
LOWER1
LOWER2
SYNC1
SYNC2
LED
VDD
VSS
VDDP1
CT
RD
VDDP2
PGND R_RESDLY
R_RA
UPPER1
ISENSE
UPPER2
PKILIM
LOWER1
BGREF
LOWER2
R_LEB
SYNC1
SYNC2 CS_COMP
ON/OFF
CSS
DCOK
EANI
LATSD
EAI
SHARE
EAO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ISL6551
SHARE BUS
FN9066.4
July 8, 2005
200W TELECOMMUNICATION POWER SUPPLY (SEE AN1002 FOR DETAILS)
1
2
3
4
5
6
7
8
9
10
ISL6551
PGOOD
ISL6551
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
10.00
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
28
0o
10.65
-
0.394
N
0.419
1.27 BSC
H
α
NOTES:
MAX
A1
e
α
MIN
28
-
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
25
FN9066.4
July 8, 2005
ISL6551
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L28.6x6
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.23
D
0.28
9
0.35
5, 8
6.00 BSC
D1
D2
9
0.20 REF
-
5.75 BSC
3.95
4.10
9
4.25
7, 8
E
6.00 BSC
-
E1
5.75 BSC
9
E2
3.95
e
4.10
4.25
7, 8
0.65 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
28
2
Nd
7
3
Ne
7
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
26
FN9066.4
July 8, 2005