MC74HC138A 1-of-8 Decoder/ Demultiplexer High−Performance Silicon−Gate CMOS The MC74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC138A decodes a three−bit Address to one−of−eight active−low outputs. This device features three Chip Select inputs, two active−low and one active−high to facilitate the demultiplexing, cascading, and chip−selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states. http://onsemi.com MARKING DIAGRAMS 16 PDIP−16 N SUFFIX CASE 648 16 1 1 16 Features • • • • • • • • • MC74HC138AN AWLYYWWG Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: 100 FETs or 29 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant SOIC−16 D SUFFIX CASE 751B 16 1 HC138AG AWLYWW 1 16 TSSOP−16 DT SUFFIX CASE 948F 16 1 HC 138A ALYWG G 1 A L, WL Y, YY W, WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2012 July, 2012 − Rev. 12 1 Publication Order Number: MC74HC138A/D MC74HC138A 1 A0 A0 1 16 VCC A1 2 15 Y0 A2 3 14 Y1 CS2 4 13 Y2 CS3 5 12 Y3 CS1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 ADDRESS INPUTS A1 3 ACTIVE-LOW OUTPUTS 6 CS1 PIN 16 = VCC PIN 8 = GND 4 CS2 5 CS3 Figure 1. Pin Assignment Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7 2 A2 CHIPSELECT INPUTS 15 Figure 2. Logic Diagram FUNCTION TABLE Inputs Outputs CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L X H X H X X X X X X X X X X X H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L H H L H L H L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H L L H H L H L H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L H = high level (steady state); L = low level (steady state); X = don’t care ORDERING INFORMATION Package Shipping† MC74HC138ANG PDIP−16 (Pb−Free) 500 Units / Rail MC74HC138ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HC138ADR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC74HC138ADTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel NLV74HC138ADR2G* SOIC−16 (Pb−Free) 2500 / Tape & Reel NLV74HC138ADTR2G* TSSOP−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable http://onsemi.com 2 MC74HC138A MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air, 750 500 450 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) Plastic DIP† SOIC Package† TSSOP Package† _C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating − Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 .W/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 2) 0 VCC V – 55 + 125 _C 0 0 0 1000 500 400 ns VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V http://onsemi.com 3 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HC138A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC V Guaranteed Limit −55_C to 25_C v 85_C v 125_C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin = VIH or VIL |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 Vin = VIH or VIL |Iout| v 20 mA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Symbol VOL Parameter Test Conditions Maximum Low−Level Output Voltage V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4 40 160 mA VCC V −55_C to 25_C v 85_C v 125_C Unit AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol Parameter Guaranteed Limit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 4) 2.0 3.0 4.5 6.0 135 90 27 23 170 125 34 29 205 165 41 35 ns tPLH, tPHL Maximum Propagation Delay, CS1 to Output Y (Figures 2 and 4) 2.0 3.0 4.5 6.0 110 85 22 19 140 100 28 24 165 125 33 28 ns tPLH, tPHL Maximum Propagation Delay, CS2 or CS3 to Output Y (Figures 3 and 4) 2.0 3.0 4.5 6.0 120 90 24 20 150 120 30 26 180 150 36 31 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 2 and 4) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns − 10 10 10 pF Cin Maximum Input Capacitance Typical @ 25°C, VCC = 5.0 V CPD 55 Power Dissipation Capacitance (Per Package)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC http://onsemi.com 4 2f + ICC VCC . pF MC74HC138A SWITCHING WAVEFORMS VALID INPUT A VCC 50% OUTPUT Y VCC 90% 50% 10% INPUT CS1 GND GND tPLH tPHL tPHL tPLH tf tr VALID 50% 90% 50% 10% OUTPUT Y tTHL tTLH Figure 2. Figure 1. TEST POINT tr tf INPUT CS2, CS3 VCC 90% 50% 10% GND tPHL OUTPUT Y OUTPUT DEVICE UNDER TEST tPLH CL* 90% 50% 10% tTHL tTLH *Includes all probe and jig capacitance Figure 3. Figure 4. Test Circuit PIN DESCRIPTIONS ADDRESS INPUTS A0, A1, A2 (Pins 1, 2, 3) Address inputs. For any other combination of CS1, CS2, and CS3, the outputs are at a logic high. Address inputs. These inputs, when the chip is selected, determine which of the eight outputs is active−low. OUTPUTS Y0 − Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7) CONTROL INPUTS CS1, CS2, CS3 (Pins 6, 4, 5) Active−low Decoded outputs. These outputs assume a low level when addressed and the chip is selected. These outputs remain high when not addressed or the chip is not selected. Chip select inputs. For CS1 at a high level and CS2, CS3 at a low level, the chip is selected and the outputs follow the http://onsemi.com 5 MC74HC138A EXPANDED LOGIC DIAGRAM 15 14 A0 A1 13 1 12 2 11 A2 3 10 CS3 CS2 Y1 Y2 Y3 Y4 Y5 5 4 9 7 CS1 Y0 6 http://onsemi.com 6 Y6 Y7 MC74HC138A PACKAGE DIMENSIONS PDIP−16 CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 9 1 8 B F C L S −T− H SEATING PLANE K G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 7 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC74HC138A PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC74HC138A PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC138A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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