LINER LTC1665CN Micropower octal 8-bit and 10-bit dac Datasheet

LTC1665/LTC1660
Micropower Octal
8-Bit and 10-Bit DACs
DESCRIPTIO
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FEATURES
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The 8-bit LTC®1665 and 10-bit LTC1660 integrate eight
accurate, serially addressable digital-to-analog converters (DACs) in tiny 16-pin narrow SSOP packages. Each
buffered DAC draws just 56µA total supply current, yet is
capable of supplying DC output currents in excess of
5mA and reliably driving capacitive loads to 1000pF.
Sleep mode further reduces total supply current to 1µA.
Tiny: 8 DACs in the Board Space of an SO-8
Micropower: 56µA per DAC Plus
1µA Sleep Mode for Extended Battery Life
Pin Compatible 8-Bit LTC1665 and 10-Bit LTC1660
Wide 2.7V to 5.5V Supply Range
Rail-to-Rail Voltage Outputs Drive 1000pF
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
Reference Input Impedance is Constant—
Eliminates External Buffer
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external
form factor.
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APPLICATIO S
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Mobile Communications
Remote Industrial Devices
Automatic Calibration for Manufacturing
Portable Battery-Powered Instruments
Trim/Adjust Applications
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Ultralow supply current, power-saving Sleep mode and
extremely compact size make the LTC1665 and LTC1660
ideal for battery-powered applications, while their ease of
use, high performance and wide supply range make them
excellent choices as general purpose converters.
BLOCK DIAGRA
LTC1665 Differential Nonlinearity (DNL)
0.5
GND
1
VOUT A
2
VCC = 5V
VREF = 4.096V
0.4
16 VCC
0.3
0.2
DAC H
15 VOUT H
0.1
LSB
DAC A
0
–0.1
–0.2
VOUT B
3
DAC B
DAC G
14 VOUT G
–0.3
–0.4
–0.5
0
VOUT C
4
DAC C
DAC F
64
128
CODE
192
13 VOUT F
255
1665/60 G09
LTC1660 Differential Nonlinearity (DNL)
1
VOUT D
5
DAC D
DAC E
VCC = 5V
VREF = 4.096V
0.8
12 VOUT E
0.6
0.4
6
CS/LD
7
SCK
8
CONTROL
LOGIC
ADDRESS
DECODER
11
CLR
10
DOUT
9
DIN
0.2
LSB
REF
0
–0.2
–0.4
SHIFT REGISTER
1665/60 BD
–0.6
–0.8
–1
0
256
512
CODE
768
1023
1665/60 G13
1
LTC1665/LTC1660
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RATI GS
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AXI U
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
(Note 1)
VCC to GND .............................................. – 0.2V to 7.5V
Logic Inputs to GND ................................ – 0.2V to 7.5V
VOUT A, VOUT B…VOUT H,
REF to GND ................................. – 0.2V to (VCC + 0.2V)
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LTC1665C/LTC1660C ............................ 0°C to 70°C
LTC1665I/LTC1660I .......................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
ORDER PART
NUMBER
TOP VIEW
GND
1
16 VCC
VOUT A
2
15 VOUT H
VOUT B
3
14 VOUT G
VOUT C
4
13 VOUT F
VOUT D
5
12 VOUT E
REF
6
11 CLR
CS/LD
7
10 DOUT
SCK
8
9
GN PACKAGE
16-LEAD PLASTIC SSOP
LTC1665CGN
LTC1665CN
LTC1665IGN
LTC1665IN
LTC1660CGN
LTC1660CN
LTC1660IGN
LTC1660IN
DIN
N PACKAGE
16-LEAD PDIP
GN PART MARKING
TJMAX = 125°C, θJA = 150°C/W (GN)
TJMAX = 125°C, θJA = 100°C/W (N)
1665
1665I
1660
1660I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC1665
TYP
MAX
LTC1660
TYP
MAX
MIN
UNITS
Accuracy
Resolution
●
8
8
10
Bits
Monotonicity
VREF ≤ VCC – 0.1V (Note 2)
●
Differential Nonlinearity
VREF ≤ VCC – 0.1V (Note 2)
●
±0.1
±0.5
±0.2
±0.75
LSB
INL
Integral Nonlinearity
VREF ≤ VCC – 0.1V (Note 2)
●
±0.2
±1.0
±0.6
±2.5
LSB
VOS
Offset Error
(Note 7)
●
±10
±30
±10
±30
●
±15
DNL
VOS Temperature Coefficient
FSE
Full-Scale Error
VCC = 5V, VREF = 4.096V
Full-Scale Error Temperature Coefficient
PSR
Power Supply Rejection
VREF = 2.5V
10
Bits
±15
±4
±3
mV
µV/°C
●
±1
●
±30
±30
±15
µV/°C
0.045
0.18
LSB/V
LSB
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITONS
MIN
TYP
MAX
UNITS
Reference Input
Input Voltage Range
IREF
●
0
●
35
Resistance
Not in Sleep Mode
Capacitance
(Note 6)
Reference Current
Sleep Mode
●
VCC
65
15
0.001
V
kΩ
pF
1
µA
5.5
V
730
550
3
µA
µA
µA
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
●
ICC
Supply Current
VCC = 5V (Note 3)
VCC = 3V (Note 3)
Sleep Mode (Note 3)
●
●
●
2
2.7
450
340
1
LTC1665/LTC1660
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Performance
Short-Circuit Current Low
VOUT = 0V, VCC = 5.5V, VREF = 5.1V, Code = Full Scale
●
10
30
100
mA
Short-Circuit Current High
VOUT = VCC = 5.5V, VREF = 5.1V, Code = 0
●
10
27
120
mA
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
Voltage Output Settling Time
To ±0.5LSB (Notes 4, 5)
0.60
0.25
Capacitive Load Driving
V/µs
V/µs
30
µs
1000
pF
Digital I/O
VIH
Digital Input High Voltage
VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
●
●
2.4
2.0
V
V
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
●
●
VOH
Digital Output High Voltage
IOUT = – 1mA, DOUT Only
●
VOL
Digital Output Low Voltage
IOUT = 1mA, DOUT Only
●
0.4
V
ILK
Digital Input Leakage
VIN = GND to VCC
●
±10
µA
CIN
Digital Input Capacitance
(Note 6)
●
10
pF
0.8
0.6
V
V
VCC – 1
V
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
40
15
ns
VCC = 4.5V to 5.5V
t1
DIN Valid to SCK Setup
t2
DIN Valid to SCK Hold
●
0
–11
ns
t3
SCK High Time
(Note 6)
●
30
5
ns
t4
SCK Low Time
(Note 6)
●
30
7
ns
t5
CS/LD Pulse Width
(Note 6)
●
80
30
ns
t6
LSB SCK High to CS/LD High
(Note 6)
●
30
4
ns
t7
CS/LD Low to SCK High
(Note 6)
●
80
26
t8
DOUT Propagation Delay
CLOAD = 15pF (Note 6)
●
5
26
t9
SCK Low to CS/LD Low
(Note 6)
●
20
0
ns
t10
CLR Pulse Width
(Note 6)
●
100
37
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
●
30
0
ns
SCK Frequency
Continuous Square Wave (Note 6)
Continuous 23% Duty Cycle Pulse (Note 6)
Gated Square Wave (Note 6)
●
●
●
●
ns
80
5.00
7.69
16.7
ns
MHz
MHz
MHz
VCC = 2.7V to 5.5V
t1
DIN Valid to SCK Setup
(Note 6)
●
60
20
ns
t2
DIN Valid to SCK Hold
(Note 6)
●
0
–14
ns
t3
SCK High Time
(Note 6)
●
50
8
ns
t4
SCK Low Time
(Note 6)
●
50
12
ns
t5
CS/LD Pulse Width
(Note 6)
●
100
30
ns
3
LTC1665/LTC1660
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
t6
LSB SCK High to CS/LD High
(Note 6)
t7
CS/LD Low to SCK High
t8
DOUT Propagation Delay
t9
t10
t11
●
50
5
(Note 6)
●
100
27
CLOAD = 15pF (Note 6)
●
5
47
SCK Low to CS/LD Low
(Note 6)
●
30
0
ns
CLR Pulse Width
(Note 6)
●
120
41
ns
CS/LD High to SCK Positive Edge
(Note 6)
●
30
0
ns
SCK Frequency
Continuous Square Wave (Note 6)
Continuous 28% Duty Cycle Pulse
Gated Square Wave
●
●
●
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined from code 4 to code
255 for the LTC1665 and from code 20 to code 1023 for the LTC1660.
See Applications Information.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
U W
Midscale Output Voltage
vs Load Current
3
2
1.9
2.8
VOUT (V)
VOUT (V)
2.4
2.3
VCC = 3.6V
1.6
1.5
VCC = 3V
1.4
VCC = 2.7V
1.3
VCC = 4.5V
2.2
1.2
2.1
1.1
SOURCE
2
–20
–10
SINK
0
10
IOUT (mA)
SOURCE
1
20
30
1665/60 G01
4
VREF = VCC
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
1.7
VCC = 5V
2.5
–30
(LTC1665/LTC1660)
1.8
VCC = 5.5V
2.6
ns
ns
150
3.85
5.55
10
Midscale Output Voltage
vs Load Current
VREF = VCC
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
2.7
UNITS
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS,
i.e., codes 26 and 230 for the LTC1665 or codes 102 and 922 for the
LTC1660.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured at code 4 for the LTC1665 and code 20 for the
LTC1660.
TYPICAL PERFOR A CE CHARACTERISTICS
2.9
MAX
–15 –12
–8
SINK
–4
0
4
IOUT (mA)
8
12 15
1665/60 G02
ns
MHz
MHz
MHz
LTC1665/LTC1660
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TYPICAL PERFOR A CE CHARACTERISTICS (LTC1665/LTC1660)
Minimum VOUT vs
Load Current (Output Sinking)
Minimum Supply Headroom vs
Load Current (Output Sourcing)
1400
1400
VREF = 4.096V
∆VOUT < 1LSB
CODE = 255 (LTC1665)
CODE = 1023 (LTC1660)
1200
1000
800
125°C
1000
125°C
VOUT (mV)
VCC – VOUT (mV)
VCC = 5V
CODE = 0
1200
25°C
600
800
25°C
600
–55°C
–55°C
400
400
200
200
0
0
0
2
4
6
IOUT (mA) (Sourcing)
|
|
8
0
10
2
4
6
|IOUT| (mA) (Sinking)
8
1665/60 G03
460
VCC = 5.5V
440
VCC = 4.5V
420
VCC = 3.6V
400
380
360
VCC = 2.7V
340
1
ALL DIGITAL INPUTS
SHORTED TOGETHER
1.6
SUPPLY CURRENT (mA)
SUPPLY CURRENT (µA)
VOUT (V)
2
2
480
10% TO
90% STEP
3
Supply Current vs Logic Input Voltage
500
VCC = VREF = 5V
4
1665/60 G04
Supply Current vs Temperature
Large-Signal Step Response
5
10
1.2
0.8
0.4
320
0
0
20
40
60
TIME (µs)
80
100
300
–55 –35 –15
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
1665/60 G05
0
1
2
3
4
LOGIC INPUT VOLTAGE (V)
1665/60 G06
5
1665/60 G07
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TYPICAL PERFOR A CE CHARACTERISTICS (LTC1665)
Integral Nonlinearity (INL)
1
VCC = 5V
VREF = 4.096V
0.8
VCC = 5V
VREF = 4.096V
0.4
0.6
0.3
0.4
0.2
0.2
0.1
LSB
LSB
Differential Nonlinearity (DNL)
0.5
0
0
–0.2
–0.1
–0.4
–0.2
–0.6
–0.3
–0.8
–0.4
–1
–0.5
0
64
128
CODE
192
255
1665/60 G08
0
64
128
CODE
192
255
1665/60 G09
5
LTC1665/LTC1660
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TYPICAL PERFOR A CE CHARACTERISTICS (LTC1665)
Load Regulation vs Output Current
Load Regulation vs Output Current
0.25
∆VOUT (LSB)
0.25
∆VOUT (LSB)
VCC = VREF = 3V
CODE = 128
0.5
VCC = VREF = 5V
CODE = 128
0.5
0
0
–0.25
–0.25
SOURCE
–0.5
–2
–1
SINK
0
IOUT (mA)
SOURCE
–0.5
1
–500
2
SINK
0
IOUT (µA)
500
1665/60 G11
1665/60 G10
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TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
2.5
1
VCC = 5V
VREF = 4.096V
2.0
VCC = 5V
VREF = 4.096V
0.8
1.5
0.6
1.0
0.4
0.5
0.2
LSB
LSB
(LTC1660)
0
0
– 0.5
–0.2
–1.0
–0.4
–1.5
–0.6
– 2.0
–0.8
– 2.5
–1
0
256
512
CODE
768
1023
0
256
512
CODE
768
1023
1665/60 G13
1665/60 G12
Load Regulation vs Output Current
Load Regulation vs Output Current
VCC = VREF = 5V
CODE = 512
2
1.5
1.5
1
1
∆VOUT (LSB)
∆VOUT (LSB)
2
0.5
0
–0.5
–1
0.5
0
–0.5
–1
–1.5
–1.5
SOURCE
–2
–2
–1
0
IOUT (mA)
SINK
–2
1
2
1665/60 G14
6
VCC = VREF = 3V
CODE = 512
–500
SOURCE
0
IOUT (µA)
SINK
500
1665/60 G15
LTC1665/LTC1660
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PIN FUNCTIONS
(LTC1665/LTC1660)
GND (Pin 1): System Ground.
VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog
Voltage Outputs. The output range is
 255 
0 to 
 V for the LTC1665
 256  REF
 1023 
0 to 
 V for the LTC1660
 1024  REF
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on DIN
into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin
is shifted into the 16-bit register on the rising edge of SCK.
CMOS and TTL compatible.
DOUT (Pin 10): Serial Interface Data Output. Data appears
on DOUT 16 positive SCK edges after being applied to DIN.
May be tied to DIN of another LTC1665/LTC1660 for daisychain operaton. CMOS and TTL compatible.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
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BLOCK DIAGRA
16 VCC
GND
1
VOUT A
2
DAC A
DAC H
15 VOUT H
VOUT B
3
DAC B
DAC G
14 VOUT G
VOUT C
4
DAC C
DAC F
13 VOUT F
VOUT D
5
DAC D
DAC E
12 VOUT E
REF
6
CS/LD
7
SCK
8
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
11
CLR
10
DOUT
9
DIN
1665/60 BD
7
LTC1665/LTC1660
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TI I G DIAGRA
t1
t2
t3
t6
t4
SCK
t9
t11
DIN
A3
t5
A1
A2
X1
X0
t7
CS/LD
t8
DOUT
A3
A2
A1
X1
X0
A3
1665/60 F01
Figure 1
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OPERATIO
Transfer Function
Serial Interface
The transfer function is
Referring to Figure 2a (2b): With CS/LD held low, data on
the DIN input is shifted into the 16-bit shift register on the
positive edge of SCK. The 4-bit DAC address, A3-A0, is
loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.
When the full 16-bit input word has been shifted in, CS/LD
is pulled high, loading the DAC register with the word and
causing the addressed DAC output(s) to update. The
clock is disabled internally when CS/LD is high. Note: SCK
must be low before CS/LD is pulled low.
 k 
VOUT(IDEAL) = 
 V for the LTC1665
 256  REF
 k 
VOUT(IDEAL) = 
 V for the LTC1660
 1024  REF
where k is the decimal equivalent of the binary DAC input
code and VREF is the voltage at REF (Pin 6).
Power-On Reset
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent and
repeatable.
The buffered serial output of the shift register is available
on the DOUT pin, which swings from GND to VCC. Data
appears on DOUT 16 positive SCK edges after being applied
to DIN.
Power Supply Sequencing
Multiple LTC1665/LTC1660’s can be controlled from a
single 3-wire serial port (i.e., SCK, DIN and CS/LD) by
using the included “daisy-chain” facility. A series of m
chips is configured by connecting each DOUT (except the
last) to DIN of the next chip, forming a single 16m-bit shift
register. The SCK and CS/LD signals are common to all
The voltage at REF (Pin 6) should be kept within the range
– 0.2V ≤ VREF ≤ VCC + 0.2V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
8
LTC1665/LTC1660
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OPERATIO
SCK
1
A3
DIN
2
3
A1
A2
4
A0
5
D7
6
D6
7
8
D5
D4
ADDRESS/CONTROL
9
10
D3
D2
11
D1
12
D0
13
X3
INPUT CODE
14
X2
15
X1
16
X0
DON’T CARE
INPUT WORD W0
CS/LD
(ENABLE CLK)
DOUT
(UPDATE OUTPUT)
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X3
X2
X1
X0
A3
INPUT WORD W–1
INPUT WORD W0
1665/60 F02a
Figure 2a. LTC1665 Register Loading Sequence
SCK
1
A3
DIN
2
3
A1
A2
4
A0
5
D9
6
D8
7
8
D7
D6
ADDRESS/CONTROL
9
10
D5
D4
11
D3
12
D2
13
D1
14
D0
INPUT CODE
15
X1
16
X0
DON’T CARE
INPUT WORD W0
CS/LD
(ENABLE CLK)
DOUT
(UPDATE OUTPUT)
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
INPUT WORD W–1
D1
D0
X1
X0
A3
INPUT WORD W0
1665/60 F02b
Figure 2b. LTC1660 Register Loading Sequence
Table 1a. LTC1665 Input Word
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0
Address/Control
Input Code
chips in the chain. In use, CS/LD is held low while m
16-bit words are clocked to DIN of the first chip; CS/LD is
then pulled high, updating all of them simultaneously.
Don’t Care
Sleep Mode
Table 1b. LTC1660 Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
Address/Control
Input Code
Don’t
Care
DAC address 1110b is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital interface
stays active while the analog circuits are disabled; static
power consumption is thus virtually eliminated. The reference input and analog outputs are set in a high impedance
9
LTC1665/LTC1660
U
OPERATIO
Table 2. DAC Address/Control Functions
Voltage Outputs
ADDRESS/CONTROL
A3
A2
A1
A0
DAC STATUS
SLEEP STATUS
0
0
0
0
No Change
Wake
0
0
0
1
Load DAC A
Wake
0
0
1
0
Load DAC B
Wake
0
0
1
1
Load DAC C
Wake
0
1
0
0
Load DAC D
Wake
0
1
0
1
Load DAC E
Wake
0
1
1
0
Load DAC F
Wake
0
1
1
1
Load DAC G
Wake
1
0
0
0
Load DAC H
Wake
1
0
0
1
No Change
Wake
1
0
1
0
No Change
Wake
1
0
1
1
No Change
Wake
1
1
0
0
No Change
Wake
1
1
0
1
No Change
Wake
1
1
1
0
No Change
Sleep
1
1
1
1
Load ALL DACs
with Same
8/10-Bit Code
Wake
state and all DAC settings are retained in memory so that
when Sleep mode is exited, the outputs of DACs not
updated by the Wake command are restored to their last
active state.
Sleep mode is initiated by performing a load sequence to
address 1110b (the DAC input word D7-D0 [D9-D0] is
ignored). Once in Sleep mode, a load sequence to any
other address (including “No Change” addresses 0000b
and 1001-1101b) causes the LTC1665/LTC1660 to Wake.
It is possible to keep one or more chips of a daisy chain in
continuous Sleep mode by giving the Sleep instruction to
these chips each time the active chips in the chain are
updated.
10
Each of the eight rail-to-rail output amplifiers contained in
these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloaded and have an equivalent output resistance of 85Ω
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1µF
load can be successfully driven by inserting a 20Ω resistor; a 2.2µF load needs only a 10Ω resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
Rail-to-Rail Output Considerations
In any rail-to-rail output voltage DAC, the output is limited
to voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits at
VCC as shown in Figure 3c. No full-scale limiting can occur
if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
LTC1665/LTC1660
U
OPERATIO
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(c)
VREF = VCC
OUTPUT
VOLTAGE
0
128
INPUT CODE
(a)
255
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1665/60 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
11
LTC1665/LTC1660
U
TYPICAL APPLICATIONS
A Low Power Quad Trim Circuit with Coarse/Fine Adjustment
3.3V
3.3V
R1
R2
0.1µF
0.1µF
R2
4
–
1
U2A
LT®1491
VOUT1
GND
2
R1
COARSE V
OUT A
3
U1
LTC1665
1
2
DAC A
16
DAC H
15
VCC
VOUT H
R1
COARSE
VOUT G
R2
FINE
R1
13
–
12
+LT1491
14
U2D
VOUT4
+
11
0.1µF
0.1µF
R1
R2
–
7
U2B
LT1491
VOUT2
R2
FINE
VOUT B
3
DAC B
DAC G
14
R1
9
6
R1
COARSE VOUT C
5
4
DAC C
DAC F
13
VOUT F
R1
COARSE
VOUT E
R2
FINE
+
0.1µF
3.3V
R2
0.1µF
–
U2C
10
+LT1491
8
VOUT3
0.1µF
R2
FINE
VOUT D
5
DAC D
DAC E
12
2
LTC1258-2.5
1
REF
6
4
CS/LD
3-WIRE
SERIAL
INTERFACE
SCK
7
8
11
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
10
9
CLR
DOUT
TO OTHER
LTC1665s
DIN
1665/60 TA01
) )
R2 >> R1
VOUT 1 = VOUT A + R1 VOUT B
R2
Similarly VOUT 2, VOUT 3, VOUT 4
Example: For R1 = 110Ω and R2 = 11k,
VOUT 1 = VOUT A + 0.01 VOUT B
12
LTC1665/LTC1660
U
TYPICAL APPLICATIONS
An 8-Channel Bipolar Output Voltage Circuit Configuration
5V
R
R
R
R
0.1µF
0.1µF
VS+
–
1
U2A
LT1491
± 5V
+
VOUT A ′
0.1µF 11
+
U2C
LT1491
± 5V
+
DAC H
15
VOUT H
2
–
3
+LT1491
R
VOUT H ′
1
± 5V
11 0.1µF
U2D
LT1491
R
6
–
5
+LT1491
7
U3B
VOUT B
5
3
DAC B
DAC G
14
VOUT G
R
± 5V
–
8
U3C
VOUT C
10
4
DAC C
DAC F
13
VOUT F
10
R
13
–
12
+LT1491
U3D
12
VOUT D
+
REF
CS/LD
3-WIRE
SERIAL
INTERFACE
CLK
5
DAC D
DAC E
6
7
8
12
11
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
10
9
VOUT E
VOUT F ′
± 5V
+LT1491
R
13
VOUT G ′
R
9
9
R
–
± 5V
14
DAC A
6
R
VOUT D ′
2
R
–
8
16
4
U3A
VOUT A
3
R
VOUT C ′
1
VCC
VS–
U2B
LT1491
± 5V
U1
LTC1660
R
–
7
GND
2
VS–
R
VOUT B ′
0.1µF
VS+
4
14
VOUT E ′
± 5V
CLR
DOUT
DIN
CODE VOUT X
– 5V
0
0V
512
1023 +4.99V
1665/60 TA01
13
LTC1665/LTC1660
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
2 3
4
5 6
7
8
0.004 – 0.0098
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
14
0.009
(0.229)
REF
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
GN16 (SSOP) 1098
LTC1665/LTC1660
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.255 ± 0.015*
(6.477 ± 0.381)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.125
(3.175)
MIN
0.100
(2.54)
BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0.018 ± 0.003
(0.457 ± 0.076)
N16 1098
15
LTC1665/LTC1660
U
TYPICAL APPLICATION
A Pin Driver VH and VL Adjustment Circuit for ATE Applications
5V
11
16
6
CLR
VCC
REF
0.1µF
VH
(FROM MAIN DAC)
U1 LTC1660
DAC H
DAC A
2
RG
VA 50k
10V
RF
5k
3
2
DAC G
DAC B
3
+ U2A
LT1369
QUAD
– 5V
VL
(FROM MAIN DAC)
DAC F
DAC C
4
CS/LD
7
DIN
9
SCK
8
DAC D
5
VH′
VH′ = VH + ∆VH
VL′
0.1µF
0.1µF
RF
5k
VH
VL
RF
5k
5
6
DAC E
1
–
RG
VB 50k
RG
VC 50k
0.1µF
+ U2B
LT1369
QUAD
7
VL′ = VL + ∆VL
VOUT
0.1µF
–
RG
VD 50k
PIN DRIVER
(1 OF 2)
LOGIC
DRIVE
RF
5k
1665/60 TA03
VA = VC = 2.5V
GND
1
Note: DACs E Through H Can Be
Configured for a Second Pin Driver
With U2C and U2D of the LT1369
CODE A CODE B ∆VH, ∆VL
512
1023 – 250mV
512
0
512
512
+ 250mV
0
VH′ = VH + RF (V – V )
B
RG A
VL′ = VL + RF (V – V )
D
RG C
For Resistor Values Shown:
Adjustment Range = ± 250mV
Adjustment Step Size = 500µV
RELATED PARTS
PART NUMBER
LTC1661
LTC1663
LTC1446/LTC1446L
DESCRIPTION
Dual 10-Bit VOUT DAC in 8-Lead MSOP Package
Single 10-Bit VOUT DAC in SOT-23 Package
Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference
LTC1448
LTC1454/LTC1454L
Dual 12-Bit VOUT DAC in SO-8 Package
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1590
LTC1659
Dual 12-Bit IOUT DAC in SO-16 Package
Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package
VCC: 2.7V to 5.5V
Micropower Precision Series Reference, 2.5V, 5V, 10V Versions
LT1460
16
Linear Technology Corporation
COMMENTS
VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output
VCC = 2.7V to 5.5V, Internal Reference, 60µA
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
VCC = 4.5V to 5.5V, 4-Quadrant Multiplication
Low Power Multiplying VOUT DAC. Output Swings from
GND to REF. REF Input Can Be Tied to VCC
0.075% Max, 10ppm/°C Max, Only 130µA Supply Current
166560f LT/TP 0999 4K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1999