256Kb EEPROM MYXX28HC256 32K x 8 EEPROM - 5 Volt, Byte Alterable Features • Access Time (ns): 70, 90, 120, 150 • Simple Byte and Page Write Description Single 5V Supply No External High Voltages or VPP Control Circuits E2PROM. The MYXX28HC256 is a high performance CMOS 32K x 8 It is fabricated with a textured poly floating gate technology, providing a highly reliable 5 Volt only nonvolatile memory. The MYXX28HC256 supports a 128-byte page write operation, effectively providing a 24ms/byte write cycle and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The MYXX28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The MYXX28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Self-Timed No Erase Before Write No Complex Programming Algorithms No Overerase Problem • Low Power CMOS: Active: 60mA Standby: 500mA • Software Data Protection Protects Data Against System Level Inadvertent Writes • High Speed Page Write Capability • Highly Reliable Direct Write™ Cell Endurance for the MYXX28HC256 is specified as a minimum 100,000 write cycles per byte and an inherent data retention of 100 years. Endurance: 100,000 Write Cycles Data Retention: 100 Years • Early End of Write Detection 2 2 26 27 A 27 4A7A7 3 3 25 4 4 24 26 A 26 A4 6A5A5 5 5 23 66 24 A 24 A2 AA 8 33 A0 AA 10 1 1 A5 A1 I/O0 I/O1 I/O2 VSS 7A4A4 A2A2 9 A0A0 11 I/OI/O 00 12 I/OI/O 11 13 I/OI/O 22 V14 VSS SS 77 88 99 1010 1111 1212 1313 13 8 25 A 25 9 22 11 2323 OE# 21 A10 MYX28C32K8 MYX28C32K8 A3 5A6A6 20 19 18 17 16 1414 15 A12 A A12 3 12 A6 VCC 2222 2121 CE# 2020 I/O 19197 I/O6 1818 I/O 17175 I/0 4 1616 I/O 15 153 VCC VCC WE# WE# A6 A13 A13 4 3 2 29 A8A8A5 A66A6 55 A3 A11 A11 A84A4 77 A9A9A4 OE# OE# A2 A10 A10 A 1 CE# CE# A 0 I/OI/O 7 7NC I/OI/O 6 60 I/O I/OI/O 55 I/0I/0 44 I/OI/O 33 1 32 31 30 66 A3A3 8MYX28C32K8 8 25 MYX28C32K8 MYX28C32K8 99 9 A2A2 10 A1A1 11 A0A0 12 NC NC 1010 1111 A8 28 2929 A9 A8A8 27 2828 A11 A9A9 A75A5 26 24 23 2727 A11 NC A11 2626 NC NC OE# 2525 A10 OE# OE# 2424 AA CE# 1010 2323 I/O1 I/O2 I/O3 I/O5 12 I/OI/O 13I/OI/O 15I/OI/O 17I/OI/O 1 1 2 2 3 3 5 5 1515 1717 I/O6 18 I/OI/O I/O0 A0 VSS 11 I/OI/O 10 A0A0 14VSSVSS 0 0 I/O4 16I/OI/O 4 4 I/O7 19 I/OI/O 7 7 A1 A2 9 A1A1 8 A2A2 CE 20CECE A10 A10A10 21 A3 A4 7 A3A3 6 A4A4 OE 22OEOE A11 A11A11 23 VCC A5 A12 A9 5 A5A5 2 A12A12 28VCCVCC 24A9A9 A8 25A8A8 A14A A WE WEWE 14 14 1 1 1 272727 AA13A 13 13 26 2626 1212 4 4 3 3 2 2 1 1323231313030 5 CE# CE# 22 I/O 2222 7I/OI/O 1212 77 21 13 I/O6 21 21 13 13 I/OI/O I/OI/O 014 0 15 16 17 18 19 20 66 1414151516161717181819192020 1111 99 77 55 1313 1010 1414 88 22 2222 2828 A6 A A A7 A A 6 6 7 7 4 44 3 33 1 1616 2020 66 Figure 1 - Pin Configuration MYXX28HC256 Revision 1.4 - 02/13 Toggle Bit Polling CerPGA CerPGA I/O1 VSS I/O I/O1 2 I/ONC 2 VSS VI/O SS3 NC NC I/O I/O34 I/O I/O35 I/O 4 I/O4 I/O5 I/O5 28 28 WE# A7 28 A7 1 1 27 CerLCC CerLCC I/O1 I/O2 2 A14 A14 MYX28C32K8 1 A12 CerPGA A7 A7 A14 A12 A12 NC A14 A14 V NC CC NC WE# VCC VCCA WE# 13 WE# A13 A13 Flat FlatPack Pack A14 DATA Polling CerSOJ or CerLCC CerSOJ CerSOJoror CerDIP or Flat Pack CerDIP CerDIPoror 2424 Options Markings 6 6 1818 1919 2121 2323 2525 Timing 70 ns access 90 ns access 120 ns access 150 ns access -7 -9 -12 -15 Packages Ceramic flat pack CerDIP, 600 mil CerLCC CerPGA CerSOJ F CW ECA P ECJ Operating Military (-55°C to +125°C) Industrial (-40°C to +85°C) Temp. XT IT 256Kb EEPROM MYXX28HC256 Pin Descriptions Functional Diagram.pdf 1 11/19/2012 8:59:32 AM Addresses (A0–A14) Table 1 - Pin Names Parameter Symbol A0-A14 Address Inputs I/O0-I/07 Data Input/Output Chip Enable (CE#) WE# Write Enable The Chip Enable input must be LOW to enable all read/write operations. When CE# is HIGH, power consumption is reduced. CE# Chip Enable OE# Output Enable Output Enable (OE#) VCC +5V The Output Enable input controls the data output buffers and is used to initiate read operations. VSS Ground NC No Connect The Address inputs select an 8-bit memory location during a read or write operation. Data In/Data Out (I/O0–I/O7) Data is written to or read from the MYXX28HC256 through the I/O pins. Figure 2 - Functional Diagram Write Enable (WE#) X BUFFERS LATCHES AND DECODER The Write Enable input controls the writing of data to the MYXX28HC256. 256K-BIT EEPROM ARRAY A0–A14 ADDRESS INPUTS C M Y Y BUFFERS LATCHES AND DECODER CM MY I/O BUFFERS AND LATCHES CY I/O0–I/O7 DATA INPUTS/OUTPUTS CMY K CE# OE# WE# VCC VSS MYXX28HC256 Revision 1.4 - 02/13 2 CONTROL LOGIC AND TIMING 256Kb EEPROM MYXX28HC256 Device Operation Write Operation Status Bits Read The MYXX28HC256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 3. Read operations are initiated by both OE# and CE# LOW. The read operation is terminated by either CE# or OE# returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE# or CE# is HIGH. Figure 3 - Status Bit Assignment C M I/O Y Write DP TB 5 4 3 2 1 0 CM RESERVED Write operations are initiated when both CE# and WE# are LOW and OE# is HIGH. The MYXX28HC256 supports both a CE# and WE# controlled write cycle. That is, the address is latched by the falling edge of either CE# or WE#, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE# or WE#, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3ms. MY TOGGLE BIT CY DATA POLLING CMY DATA Polling (I/O7) K The MYXX28HC256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the MYXX28HC256, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Page Write Operation The page write feature of the MYXX28HC256 allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the MYXX28HC256 prior to the commencement of the internal programming Toggle Bit (I/O6) cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The MYXX28HC256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read and write operations. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE# HIGH to LOW transition, must begin within 100ms of the falling edge of the preceding WE#. If a subsequent WE# HIGH to LOW transition is not detected within 100ms, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100ms. MYXX28HC256 Revision 1.4 - 02/13 3 256Kb EEPROM MYXX28HC256 DATA Polling I/O7 Figure 4 - Data Polling Bus Sequence WE# LAST WRITE LAST WE# CE# CE# WRITE OE# VIH VOL VIH I/O A 7–A 0 A0–A14 14 VOH HIGH Z OE# I/O7 HIGH Z An An An An An VOL An An An An An An An VOH MYXX28HC256 READY An MYXX28HC256 READY An Figure 5 - Data Polling Software Flow DATA Polling can effectively halve the time for writing to the MYXX28HC256. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates one method of implementing the routine. WRITE DATA WRITE DATA NO WRITES COMPLETE?NO WRITES COMPLETE? YES YES SAVE LAST DATA SAVE LAST ANDDATA ADDRESS AND ADDRESS READ READ LAST LAST ADDRESS ADDRESS IO7 IO NO COMPARE? 7 COMPARE? YES NO YES MYXX28HC256 READY MYXX28HC256 READY MYXX28HC256 Revision 1.4 - 02/13 4 256Kb EEPROM MYXX28HC256 The Toggle Bit I/O6 Figure 6 - Toggle Bit Bus Sequence WE# WE# LAST WRITE LAST WRITE CE# CE# OE# OE# I/O6 I/O6 * VOH VOH HIGH Z VOL HIGH Z * VOL * I/O6 beginning and ending state of I/O6 will vary. * * MYXX28HC256 READY MYXX28HC256 READY * I/O6 beginning and ending state of I/O6 will vary. Figure 7 - Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple MYXX28HC256 memories that is frequently updated. The timing diagram in Figure 6 illustrates the sequence of events on the bus. The software flow diagram in Figure 7 illustrates a method for polling the Toggle Bit. LAST WRITE LAST WRITE YES YES LOAD ACCUM FROM ADDR n LOAD ACCUM FROM ADDR n COMPARE COMPARE ACCUM WITH ACCUM WITH ADDR n ADDR n COMPARE NO COMPARE OK? OK? YES NO YES MYXX28HC256 MYXX28HC256 READY READY MYXX28HC256 Revision 1.4 - 02/13 5 256Kb EEPROM MYXX28HC256 Hardware Data Protection can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. The MYXX28HC256 provides two hardware features that protect nonvolatile data from inadvertent writes. • Default VCC Sense - All write functions are inhibited when VCC is ≤ 3.5V Typically. Once the software protection is enabled, the MYXX28HC256 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. • Write Inhibit - Holding either OE# LOW, WE# HIGH, or CE# HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Software Data Protection Software Algorithm The MYXX28HC256 offers a software controlled data protection feature. The MYXX28HC256 is shipped from Micross with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The MYXX28HC256 Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 9 and 10 for the sequence. The three-byte sequence opens the page write window enabling the host to write from one to one hundred twentyeight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. MYXX28HC256 Revision 1.4 - 02/13 6 Software Data Protection.pdf 1 11/19/2012 11:58:45 AM Software Data Protection.pdf 1 11/19/2012 11:58:45 AM 256Kb EEPROM MYXX28HC256 Software Data Protection Figure 8 - Timing Sequence - Byte or Page Write VCC VCC 0V 0V (VCC) DATA CE# AA ADDRESS DATA 5555 ADDRESS AA 5555 55 552AAA 2AAA A0 A0 5555 5555 WRITEStWC WRITESOK OK CE# ≤tBLC MAX ≤tBLC MAX WE# WE# tWC (VCC) WRITE WRITE PROTECTED PROTECTED BYTE BYTE OR OR PAGE PAGE Figure 9 - Write Sequence for Software Data Protection Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the MYXX28HC256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the MYXX28HC256 will be write protected during power-down and after any subsequent power-up. WRITE AAAA WRITEDATA DATA TO TOADDRESS ADDRESS 5555 5555 WRITE DATA 55 WRITE DATA 55 TO ADDRESS TO2AAA ADDRESS 2AAA WRITE DATA A0 TO ADDRESS WRITE DATA A0 TO 5555 ADDRESS 5555 WRITE DATA XX TO ANY WRITE DATA XX ADDRESS TO ANY ADDRESS WRITE LAST BYTE TO WRITE LAST LAST ADDRESS Note: Once initiated, the sequence of write operations should not be interrupted. BYTE/PAGE LOAD ENABLED BYTE/PAGE LOAD ENABLED OPTIONAL BYTE OR OPTIONAL PAGE WRITE BYTE OR ALLOWED PAGE WRITE ALLOWED BYTE TO LAST ADDRESS AFTER tWC RE-ENTERS DATA PROTECTED AFTER STATE t WC RE-ENTERS DATA PROTECTED STATE MYXX28HC256 Revision 1.4 - 02/13 7 ResettingSoftware Software Data Protection.pdf 1 11/19/2012 12:07:04 Resetting Data Protection.pdf 1 11/19/2012 12:07:04 PM PM 256Kb EEPROM MYXX28HC256 Resetting Software Data Protection Figure 10 - Reset Software Data Protection Timing Sequence VCC VCC DATA AA ADDRESS DATA AA ADDRESS 5555 5555 CE# CE# 55 2AAA 55 2AAA 80 555580 5555 AA 5555AA 5555 55 2AAA55 2AAA 20 5555 20 5555 tWC tWC STANDARD OPERATING STANDARD MODEOPERATING MODE WE# WE# Figure 11 - Write Sequence for Resetting Software Data Protection In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the MYXX28HC256 will be in standard operating mode. WRITE DATA AA TO ADDRESS WRITE 5555DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS WRITE 2AAADATA 55 TO ADDRESS 2AAA Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA 80 TO ADDRESS 5555DATA 80 WRITE TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555DATA AA WRITE TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 20 TO ADDRESS 5555 WRITE DATA 20 TO ADDRESS AFTER5555 tWC, RE-ENTERS UNPROTECTED AFTER STATE tWC, RE-ENTERS UNPROTECTED STATE MYXX28HC256 Revision 1.4 - 02/13 8 256Kb EEPROM MYXX28HC256 System Considerations these spikes is dependent on the output capacitive loading of the l/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. Because the MYXX28HC256 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit it is recommended that CE# be decoded from the address bus and be used as the primary device selection input. Both OE# and WE# would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. Because the MYXX28HC256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE# will cause transient current spikes. The magnitude of MYXX28HC256 Revision 1.4 - 02/13 9 256Kb EEPROM MYXX28HC256 Table 2 - Absolute Maximum Ratings* *Note Temperature under bias Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage temperature Voltage on any pin with respect to VSS DC output current Lead temperature (soldering, 10 sec.) Supply voltage -10°C to +85°C -65°C to +135°C -65°C to +150°C -1V to +7V 10mA 300°C 5V ±10% Table 3 - Recommended Operating Conditions Temperature Commerical Industrial Military Min. Max. 0°C -40°C -55°C +70°C +85°C +125°C Table 4 - DC Operating Characteristics Over the recommended operating conditions unless otherwise specified. Symbol Parameter ICC Limits Units Test Conditions Typ.1 Max. VCC Active Current (TTL Inputs) 30 60 ISB1 VCC Standby Current (TTL Inputs) 1 2 CE# = VIH; OE# = VIL; All I/O’s = Open; Other Inputs = VIH ISB2 VCC Standby Current (CMOS Inputs) 200 500 CE# = VCC - 0.3V; OE# = GND; All I/O’s = Open; Other Inputs = VCC - 0.3V ILI Input Leakage Current 10 ILO Output Leakage Current 10 VIL2 Input LOW Voltage -1 0.8 VIH2 Input HIGH Voltage 2 VCC +1 VOL Output LOW Voltage VOH Output HIGH Voltage Min. mA µA VIN = VSS to VCC; CE# = VIH VOUT = VSS to VCC; CE# = VIH V 0.4 IOL = 6mA 2.4 IOH = -4mA 1. Typical values are for TA = 25°C and nominal supply voltage. 2. VIL min. and VIH max. are for reference only and are not tested. MYXX28HC256 Revision 1.4 - 02/13 CE# = OE# = VIL; WE# = VIH All I/O’s = Open; Address Inputs = .4V/2.4V Levels @ f = 10MHz 10 256Kb EEPROM MYXX28HC256 Table 5 - Power-Up Timing Symbol Parameter Max. Units tPUR1 Power-Up to Read 100 µs tPUW1 Power-Up to Write 5 ms 1. This parameter is periodically sampled and not 100% tested. Table 6 - Capacitance TA = +25°C; f = 1MHz; VCC = 5V Symbol Test Max. CI/O Input/Output Capacitance 10 CIN Input Capacitance 6 Units Conditions VI/O = OV pF VIN = OV Table 7 - Endurance and Data Retention Parameter Min. Max. Endurance 100,000 Cycles Data Retention 100 Years Table 8 - AC Conditions of Test Input Pulse Levels Table 9 - Mode Selection CE# 0V to 3V L Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V MYXX28HC256 Revision 1.4 - 02/13 Units H X 11 OE# WE# Mode I/O L H Read DOUT H L Write DIN X X Standby & Write Inhibit High Z L X X H Write Inhibit Power Active Standby 256Kb EEPROM MYXX28HC256 Figure 12 - Equivalent AC Load Circuit Figure 13 - Symbol Table WAVEFORM WAVEFORM 5V OUTPUTS INPUTS Must be OUTPUTS steady Will be steady Must be steady Will be to HIGH HIGH Maytochange Will change from HIGH to LOW Don’t Care: Changing: Changes State Not Known Allowed Line N/ACenter is High Changing: State Not Known Center Line is High Impedance Maysteady change from LOW May change to HIGH Will change from LOW from LOW 5V 1.92KΩ 1.92KΩ OUTPUT May change from Will change HIGH from HIGH to LOW from HIGH to LOW to LOW OUTPUT 1.37K1.37K Ω Ω INPUTS 30pF 30pF Don’t Care: Changes Allowed N/A Impedance MYXX28HC256 Revision 1.4 - 02/13 12 Will change from LOW to HIGH 256Kb EEPROM MYXX28HC256 AC Characteristics Over the recommended operating conditions unless otherwise specified. Table 10 - Read Cycle Limits MYXX28HC256-70 Symbol Parameter tRC Read Cycle Time tCE Chip Enable Access Time tAA Address Access Time tOE Output Enable Access Time tLZ1 CE# LOW to Output Active tOLZ1 OE# LOW to Output Active tHZ1 CE# HIGH to High Z Output tOHZ1 OE# HIGH to High Z Output tOH Output Hold from Address Change Min. Max. 70 MYXX28HC256-90 Min. Max. 90 MYXX28HC256-12 Min. Max. 120 MYXX28HC256-15 Min. Max 150 70 90 120 150 35 40 50 50 ns 0 0 0 35 0 40 0 50 0 50 0 0 1. tLZ min., tHZ, tOLZ min. and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured, with CL = 5pF, from the point when CE#, OE# return HIGH (whichever occurs first) to the time when the outputs are no longer driven. Figure 14 - Read Cycle tRC ADDRESS tCE CE# tOE OE# WE# VIH tOLZ tOHZ tLZ DATA I/O HIGH Z tOH DATA VALID 13 tHZ DATA VALID tAA MYXX28HC256 Revision 1.4 - 02/13 Units 256Kb EEPROM MYXX28HC256 Table 11 - Write Cycle Limits Symbol Parameter Min. tWC2 Write Cycle Time tAS Address Setup Time 0 tAH Address Hold Time 50 tCS Write Setup Time 0 tCH Write Hold Time 0 tCW CE# Pulse Width 50 tOES OE# HIGH Setup Time 0 tOEH OE# HIGH Hold Time 0 tWP WE# Pulse Width 50 tWPH3 WE# High Recovery (page write only) 50 tDV Data Valid tDS Data Setup 50 tDH Data Hold 0 tDW3 Delay to next Write after polling is true 10 tBLC Byte Load Cycle 0.15 Units 3 5 ms 1 tWC ADDRESS tAS tCS tAH tCH CE# tOES tOEH tWP WE# DATA IN DATA VALID tDS DATA OUT tDH HIGH Z 14 µs ns Figure 15 - WE# Controlled Write Cycle MYXX28HC256 Revision 1.4 - 02/13 Max. ns 1. Typical values are for TA = 25°C and nominal supply voltage. 2. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 3. tWPH and tDW are periodically sampled and not 100% tested. OE# Typ.1 100 µs 256Kb EEPROM MYXX28HC256 Figure 16 - CE# Controlled Write Cycle tWC ADDRESS tAS tAH CE# tCW tOES tOEH OE# tCS tCH WE# DATA IN DATA VALID tDS tDH HIGH Z DATA OUT Figure 17 - Page Write Cycle 1 OE# CE# tWP WE# tBLC tWPH 2 ADDRESS I/O LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2 tWC *For each successive write within the page write operation, A7–A14 should be the same or writes to an unknown address could occur. 1. Between successive byte writes within a page write operation, OE# can be strobed LOW: e.g. this can be done with CE# and WE# HIGH to fetch data from another memory device within the system for the next write; or with WE# HIGH and CE# LOW effectively performing a polling operation. 2. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE# or WE# controlled write cycle timing. MYXX28HC256 Revision 1.4 - 02/13 15 256Kb EEPROM MYXX28HC256 Figure 18 - DATA Polling Diagram1 ADDRESS AN AN AN CE# WE# tOEH tOES OE# tDW DIN=X I/O7 DOUT=X DOUT=X tWC Figure 19 - Toggle Bit Timing Diagram1 CE# WE# tOES tOEH OE# I/O6 HIGH Z tDW * * tWC *I/O6 beginning and ending state will vary, depending upon actual tWC. 1. Polling operations are by definition read cycles and are therefore subject to read cycle timings. MYXX28HC256 Revision 1.4 - 02/13 16 256Kb EEPROM MYXX28HC256 Packaging Information Figure 20 - 28-Lead Hermetic Dual In-line Package Type CW 1.460 (37.08) 1.400 (35.56) 0.550 (13.97) 0.510 (12.95) PIN 1 INDEX PIN 1 0.085 (2.16) 0.040 (1.02) 1.300 (33.02) REF. 0.160 (4.06) 0.125 (3.17) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.150 (3.81) 0.125 (3.17) 0.110 (2.79) 0.090 (2.29) 0.062 (1.57) 0.050 (1.27) 0.020 (0.51) 0.016 (0.41) 0.610 (15.49) 0.590 (14.99) 0° 15° TYP. 0.010 (0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) MYXX28HC256 Revision 1.4 - 02/13 17 256Kb EEPROM MYXX28HC256 Packaging Information (continued) Figure 21 - 32-Pad Ceramic Leadless Chip Carrier Package Type ECA 0.150 (3.81) BSC 0.015 (0.38) 0.003 (0.08) 0.020 (0.51) x 45° REF. 0.095 (2.41) 0.075 (1.91) PIN 1 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS. 0.200 (5.08) BSC 0.028 (0.71) 0.022 (0.56) (32) PLCS. 0.050 (1.27) BSC 0.040 (1.02) x 45° REF. TYP. (3) PLCS. 0.458 (11.63) 0.442 (11.22) 0.458 (11.63) –– 0.300 (7.62) BSC 0.120 (3.05) 0.060 (1.52) 0.088 (2.24) 0.050 (1.27) 0.560 (14.22) 0.540 (13.71) 0.400 (10.16) BSC 0.558 (14.17) –– 3926 FHD F14 32 1 PIN 1 INDEX CORDER NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NTL ±0.005 (0.127) MYXX28HC256 Revision 1.4 - 02/13 18 3926 Fhd F14 256Kb EEPROM MYXX28HC256 Packaging Information (continued) Figure 22 - 28-Lead Ceramic Pin Grid Array Package Type P 12 13 15 17 18 11 10 14 16 19 A 9 8 20 21 7 6 22 23 0.008 0.050 A 5 2 28 24 25 4 3 1 27 26 0.080 0.070 TYP. 0.100 ALL LEADS NOTE: LEADS 4,12,18 & 26 0.080 4 CORNERS 0.070 0.100 0.080 0.072 0.061 PIN 1 INDEX 0.020 0.016 0.660 (16.76) 0.640 (16.26) A A 0.185 (4.70) 0.175 (4.44) 0.561 (14.25) 0.541 (13.75) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) MYXX28HC256 Revision 1.4 - 02/13 19 256Kb EEPROM MYXX28HC256 Packaging Information (continued) Figure 23 - 28-Lead Ceramic Flat Pack Type F 0.019 (0.48) 0.015 (0.38) PIN 1 INDEX 1 28 0.050 (1.27) BSC 0.740 (18.80) MAX. 0.045 (1.14) MAX. 0.440 (11.18) MAX. 0.006 (0.15) 0.003 (0.08) 0.370 (9.40) 0.250 (6.35) TYP. 0.300 2 PLCS. 0.180 (4.57) MIN. 0.130 (3.30) 0.090 (2.29) 0.045 (1.14) 0.025 (0.66) 0.030 (0.76) MIN. NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) MYXX28HC256 Revision 1.4 - 02/13 20 256Kb EEPROM MYXX28HC256 Packaging Information (continued) Figure 24 - 32-Lead Ceramic SOJ Type ECJ 32 1 MYXX28HC256 Revision 1.4 - 02/13 21 256Kb EEPROM MYXX28HC256 Ordering Information Table 12 - Device Numbering Device Number Package Type Speed Temperature -7 = 70ns MYXX28HC256CW CerDIP -9 = 90ns -12 = 120ns IT/XT -15 = 150ns -7 = 70ns MYXX28HC256ECA- CerLCC -9 = 90ns -12 = 120ns IT/XT -15 = 150ns -7 = 70ns MYXX28HC256F- CerFP -9 = 90ns -12 = 120ns IT/XT -15 = 150ns -7 = 70ns MYXX28HC256P- CerPGA -9 = 90ns -12 = 120ns IT/XT -15 = 150ns -7 = 70ns MYXX28HC256ECJ CerSOJ -9 = 90ns -12 = 120ns -15 = 150ns IT = Industrial Temperature Range -40°C to +85°C XT = Extended Temperature Range -55°C to +125°C MYXX28HC256 Revision 1.4 - 02/13 22 IT/XT 256Kb EEPROM MYXX28HC256 Document Title 32K x 8 EEPROM - 5 Volt, Byte Alterable Revision History Revision # History Release Date Status 1.3 Initial Release November 2012 Preliminary 1.4 Added ceramic SOJ package drawing and option Changed status to “Released” Corrected part number Corrected figure designations February 2013 Released MYXX28HC256 Revision 1.4 - 02/13 23