AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 Integrated Analog Front-End for Pulse Oximeters Check for Samples: AFE4490 FEATURES 1 • • Package: Compact QFN-40 (6 mm × 6 mm) Specified Temperature Range: –40°C to +85°C APPLICATIONS • • Medical Pulse Oximeter Applications Industrial Photometry Applications DESCRIPTION The AFE4490 is a fully-integrated analog front-end (AFE) that is ideally suited for pulse-oximeter applications. The device consists of a low-noise receiver channel with a 22-bit analog-to-digital converter (ADC), an LED transmit section, and diagnostics for sensor and LED fault detection. The AFE4490 is a very configurable timing controller. This flexibility enables the user to have complete control of the device timing characteristics. To ease clocking requirements and provide a low-jitter clock to the AFE4490, an oscillator is also integrated that functions from an external crystal. The device communicates to an external microcontroller or host processor using an SPI™ interface. The AFE4490 is a complete AFE solution packaged in a single, compact QFN-40 package (6 mm × 6 mm) and is specified over the operating temperature range of –40°C to +85°C. 2.2-V Supply Rx LED2 Data LED2 + CPD + TIA Stage 2 Gain AMBLED2 + û ADC Buffer LED1 AMBLED1 Amb (LED2) Data (LED2 t Amb) Data LED1 Data AFE SPI SPI Interface Amb (LED1) Data (LED1 t Amb) Data Photodiode Diagnostic PD Open or Short Cable Off LED Open or Short LED LED Driver Timing Controller Diagnostic Signals • • • Digital Filter • Fully-Integrated Analog Front-End for Pulse Oximeter Applications: – Flexible Pulse Sequencing and Timing Control Transmit: – Integrated LED Driver (H-Bridge or Push/Pull) – 110-dB Dynamic Range Across Full Range (Enables Low Noise at Low LED Current) – LED Current: – Programmable Ranges of 50 mA, 75 mA, 100 mA, 150 mA, and 200 mA, Each with 8-Bit Current Resolution – Low Power: – 100 µA + Average LED Current – LED On-Time Programmability from (50 µs + Settle Time) to 4 ms – Independent LED2 and LED1 Current Reference Receive Channel with High Dynamic Range: – Input-Referred Noise: 13 pARMS (0.1-Hz to 5-Hz Bandwidth) – 13.5 Noise-Free Bits (0.1 Hz to 5 Hz) – Analog Ambient Cancellation Scheme with Selectable 1-µA to 10-µA Ambient Current – Low Power: < 2.3 mA at 3.0-V Supply – Rx Sample Time: 50 µs to 250 µs – I-V Amplifier with Seven Separate LED2 and LED1 Programmable Feedback R and C Settings – Integrated Digital Ambient Estimation and Subtraction Integrated Fault Diagnostics: – Photodiode and LED Open and Short Detection – Cable On/Off Detection Supplies: – Rx = 2.0 V to 3.6 V – Tx = 3.0 V or 5.25 V Filter • 23 LED Current Control DAC OSC AFE Tx Driver Supply 5-V Supply 8 MHz 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FAMILY AND ORDERING INFORMATION LED DRIVE CURRENT (mA, max) POWER SUPPLY (V) OPERATING TEMPERATURE RANGE PRODUCT PACKAGE-LEAD LED DRIVE CONFIGURATION AFE4490 QFN-40 Bridge, push-pull 50, 75, 100, 150, and 200 3 to 5.25 –40°C to +85°C AFE4400 QFN-40 Bridge, push-pull 50 3 to 3.6 0°C to +70°C ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE UNIT AVDD to AVSS –0.3 to +7 V DVDD to DGND –0.3 to +7 V AGND to DGND –0.3 to +0.3 V Analog input to AVSS AVSS – 0.3 to AVDD + 0.3 V Digital input to DVDD DVSS – 0.3 to DVDD + 0.3 V ±7 mA Momentary ±50 mA Continuous ±7 mA Operating temperature range –40 to +85 °C Storage temperature range, Tstg –60 to +150 °C +125 °C Human body model (HBM) JEDEC standard 22, test method A114-C.01, all pins ±1000 V Charged device model (CDM) JEDEC standard 22, test method C101, all pins ±500 V Input current to any pin except supply pins (2) Input current Maximum junction temperature, TJ Electrostatic discharge (ESD) ratings (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current-limited to 10 mA or less. THERMAL INFORMATION AFE4490 THERMAL METRIC (1) RHA (QFN) UNITS 40 PINS θJA Junction-to-ambient thermal resistance 35 θJCtop Junction-to-case (top) thermal resistance 31 θJB Junction-to-board thermal resistance 26 ψJT Junction-to-top characterization parameter 0.1 ψJB Junction-to-board characterization parameter N/A θJCbot Junction-to-case (bottom) thermal resistance N/A (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range, unless otherwise noted. PARAMETER VALUE UNIT SUPPLIES RX_ANA_SUP AFE analog supply 2.0 to 3.6 V RX_DIG_SUP AFE digital supply 2.0 to 3.6 V TX_CTRL_SUP Transmit controller supply 3.0 to 5.25 V (1) (2) H-bridge configuration LED_DRV_SUP Transmit LED driver supply Common anode configuration [3.0 or (1.4 + VLED + VCABLE) , whichever is greater] to 5.25 V (1) (2) [3.0 or (1.3 + VLED + VCABLE) , whichever is greater] to 5.25 V Difference between LED_DRV_SUP and TX_CTRL_SUP –0.3 to +0.3 V Specified temperature range –40 to +85 °C Storage temperature range –60 to +150 °C TEMPERATURE (1) (2) VLED refers to the voltage drop across the external LED connected between the TXP and TXM pins (in H-bridge mode) and from the TXP and TXM pins to LED_DRV_SUP (in the common anode configuration). VCABLE refers to voltage drop across any cable, connector, or any other component in series with the LED. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 3 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS Minimum and maximum specifications are at TA = –40°C to +85°C. Typical specifications are at +25°C. All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PERFORMANCE (Full-Signal Chain) IIN_FS Full-scale input current RF = 10 kΩ 50 µA RF = 25 kΩ 20 µA RF = 50 kΩ 10 µA RF = 100 kΩ 5 µA RF = 250 kΩ 2 µA RF = 500 kΩ 1 µA RF = 1 MΩ PRF Pulse repetition frequency DCPRF PRF duty cycle 0.5 61 µA 5000 SPS 25% RF = 10 kΩ 50 µA RF = 1 MΩ 0.5 µA IIN_FS Full-scale input current PSRRLED PSRR, transmit LED driver With respect to ripple on LED_DRV_SUP 75 dB PSRRTx PSRR, transmit control With respect to ripple on TX_CTRL_SUP 60 dB PSRR, receiver With respect to ripple on RX_ANA_SUP and RX_DIG_SUP 60 dB Total integrated noise current, input-referred (receiver with transmitter loop back, 0.1-Hz to 5-Hz bandwidth) RF = 100 kΩ, PRF = 625 Hz, duty cycle = 5% 36 pARMS RF = 500 kΩ, PRF = 625 Hz, duty cycle = 5% 13 pARMS Noise-free bits (receiver with transmitter loop back, 0.1-Hz to 5-Hz bandwidth) (1) RF = 100 kΩ, PRF = 625 Hz, duty cycle = 5% 14.3 Bits RF = 500 kΩ, PRF = 625 Hz, duty cycle = 5% 13.5 Bits 1.4 pARMS 5 pARMS PSRRRx NFB RECEIVER FUNCTIONAL BLOCK LEVEL SPECIFICATION RF = 500 kΩ, ambient cancellation enabled, stage 2 gain = 4, PRF = 1300 Hz, LED duty cycle = 25% Total integrated noise current, input-referred (receiver alone) over 0.1-Hz to 5-Hz bandwidth RF = 500 kΩ, ambient cancellation enabled, stage 2 gain = 4, PRF = 1300 Hz, LED duty cycle = 5% I-V TRANSIMPEDANCE AMPLIFIER G Gain See the Receiver Channel section for details RF = 10 kΩ to RF = 1 MΩ Gain accuracy VOD(fs) VO(shield) (1) V/µA ±7% Feedback resistance RF Feedback resistor tolerance RF Feedback capacitance CF Feedback capacitor tolerance CF 10k, 25k, 50k, 100k, 250k, 500k, and 1M Ω ±7% 5, 10, 25, 50, 100, and 250 pF ±20% Full-scale differential output voltage Common-mode voltage on input pins Set internally External differential input capacitance Includes equivalent capacitance of photodiode, cables, EMI filter, and so forth Shield output voltage, VCM With a 1-kΩ series resistor and a 10-nF decoupling capacitor to ground 1 V 0.9 V 10 1000 0.9 pF V Noise-free bits (NFB) are defined as: NFB = log 2 IPD 6.6 ´ INOISE Where: IPD is the photodiode current, and INOISE is the input-referred RMS noise current. 4 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications are at TA = –40°C to +85°C. Typical specifications are at +25°C. All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AMBIENT CANCELLATION STAGE G Gain 1, 1.5, 2, 3, and 4 Current DAC range 0 Current DAC step size V/V 10 µA 1 µA LOW-PASS FILTER Low-pass corner frequency Pass-band attenuation, 2 Hz to 10 Hz 3-dB attenuation 0.5 and 1 kHz Duty cycle = 25% 0.004 dB Duty cycle = 10% 0.041 dB ANALOG-TO-DIGITAL CONVERTER Resolution Sample rate 22 See the ADC Operation and Averaging Module section 4 × PRF ADC full-scale voltage ADC conversion time SPS ±1.2 See the ADC Operation and Averaging Module section ADC reset time 50 Bits V PRF / 4 2 µs tCLK TRANSMITTER 0, 50, 75, 100, 150, and 200 (see the LEDCNTRL: LED Control Register for details) Output current range LED current DAC error ±5% Output current resolution Transmitter noise dynamic range, over 0.1-Hz to 5-Hz bandwidth 8 Bits At 25-mA output current 110 dB At 100-mA output current 110 dB 50 µs LED_ON = 0 1 µA LED_ON = 1 50 µA Minimum sample time of LED1 and LED2 pulses LED current DAC leakage current mA LED current DAC linearity Percent of full-scale current 0.5% Output current settling time (with resistive load) From zero current to 150 mA 7 µs From 150 mA to zero current 7 µs EN_SLOW_DIAG = 0 Start of diagnostics after the DIAG_EN register bit is set. End of diagnostic indicated by DIAG_END going high. 8 ms EN_SLOW_DIAG = 1 Start of diagnostics after the DIAG_EN register bit is set. End of diagnostic indicated by DIAG_END going high. 16 ms Open fault resistance > 100 kΩ Short fault resistance < 10 kΩ DIAGNOSTICS Duration of diagnostics state machine Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 5 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications are at TA = –40°C to +85°C. Typical specifications are at +25°C. All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL OSCILLATOR fCLKOUT CLKOUT frequency DCCLKOUT CLKOUT duty cycle Crystal oscillator start-up time With an 8-MHz crystal connected to the XIN and XOUT pins 4 MHz 50% With an 8-MHz crystal connected to the XIN and XOUT pins 200 µs EXTERNAL CLOCK Maximum allowable external clock jitter 50 ps TIMING Wake-up time from complete power-down tRESET Active low RESET pulse duration 1000 ms 1 µs tDIAGEND DIAG_END pulse duration at diagnostics completion 4 CLKOUT cycles tADCRDY ADC_RDY pulse duration 1 CLKOUT cycles DIGITAL SIGNAL CHARACTERISTICS VIH Logic high input voltage AFE_PDN, SPI CLK, SPI SIMO, SPI STE, RESET VIL Logic low input voltage AFE_PDN, SPI CLK, SPI SIMO, SPI STE, RESET IIN Logic input current Digital inputs at VIH or VIL VOH Logic high output voltage DIAG_END, LED_ALM, PD_ALM, SPI SOMI, RX_DIG_SUP – 0.1 ADC_RDY, CLKOUT VOL Logic low output voltage DIAG_END, LED_ALM, PD_ALM, SPI SOMI, ADC_RDY, CLKOUT 0.75 × RX_DIG_SUP V 0.25 × RX_DIG_SUP 0.1 V µA V 0.1 V SUPPLY CURRENT Receiver analog supply current RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 disabled 0.6 mA RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 enabled 0.7 mA 0.27 mA 55 µA 15 µA Receiver current only (RX_ANA_SUP + RX_DIG_SUP) 5 µA Transmitter current only (LED_DRV_SUP + TX_CTRL_SUP) 2 µA 220 µA 2 µA Receiver digital supply current RX_DIG_SUP = 3.0 V LED_DRV _SUP LED driver supply current With zero LED current setting TX_CTRL _SUP Transmitter control supply current Complete power-down (using the AFE_PDN pin) 6 Power-down Rx alone Receiver current only (RX_ANA_SUP + RX_DIG_SUP) Power-down Tx alone Transmitter current only (LED_DRV_SUP + TX_CTRL_SUP) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications are at TA = –40°C to +85°C. Typical specifications are at +25°C. All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER DISSIPATION PD(q) 1.54 mW 0.1 µW 1 µA TX_CTRL_SUP 1 µA RX_ANA_SUP 5 µA RX_DIG_SUP 0.1 µA 1 µA TX_CTRL_SUP 1 µA RX_ANA_SUP 15 µA RX_DIG_SUP 20 µA 50 µA TX_CTRL_SUP 15 µA RX_ANA_SUP 220 µA RX_DIG_SUP 220 µA 2 µA Quiescent power dissipation LED_DRV_SUP Power-down with the AFE_PDN pin LED_DRV_SUP Power-down with the PDNAFE register bit LED_DRV_SUP Power-down Rx LED_DRV_SUP Power-down Tx LED_DRV_SUP current value. Does not include LED current. LED_DRV_SUP current value. Does not include LED current. LED_DRV_SUP current value. Does not include LED current. LED_DRV_SUP current value. Does not include LED current. 2 µA RX_ANA_SUP 600 µA RX_DIG_SUP 230 µA 50 µA TX_CTRL_SUP 15 µA RX_ANA_SUP 600 µA RX_DIG_SUP 230 µA 0.28 µA TX_CTRL_SUP 0.1 µA RX_ANA_SUP 700 µA RX_DIG_SUP 0.8 µA LED_DRV_SUP With stage 2 mode enabled and 8-MHz clock running Power-down TX_CTRL_SUP LED_DRV_SUP After reset, with 8-MHz clock running Normal operation (excluding LEDs) LED_DRV_SUP current value. Does not include LED current. LED_DRV_SUP current value. Does not include LED current. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 7 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com PARAMETRIC MEASUREMENT INFORMATION SERIAL INTERFACE TIMING tCLK ~ ~ ~ ~ ~ ~ CLK tDATA SPISTE tDECODE A7 A6 A1 A0 SPISIMO D23 SPISOMI D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0 tDOHD tSCLK SCLK 'RQ¶W FDUH, can be high or low. (1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE. (2) Specify the register address whose contents must be read back on A[7:0]. (3) The AFE outputs the contents of the specified register on the SOMI pin. Figure 1. Serial Interface Timing Diagram(1)(2)(3) Table 1. Timing Requirements for Figure 1 2.0 V ≤ RX_DIG_SUP ≤ 3.6 V PARAMETER MIN TYP MAX fSPICLK SPI CLK frequency tSPI_SU SPISIMO input data setup time with respect to SCLK rising edge 62.5 ns tSPI_HO SPISIMO input data hold time with respect to SCLK rising edge 62.5 ns tSOMI_VAL SPISOMI output data setup time tSPICLK / 4 ns tSOMI_HO SPISOMI output data hold time tSPICLK / 2 tRISE Rise time from 20% to 80% 5 ns tFALL Fall time from 80% to 20% 5 ns 8 8 UNIT Submit Documentation Feedback MHz ns Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 PIN CONFIGURATION RX_ANA_GND RX_ANA_SUP XIN XOUT RX_ANA_GND RXOUTP RXOUTN RX_ANA_SUP RX_DIG_GND RX_DIG_GND RHA PACKAGE QFN-40 (Top View) 40 39 38 37 36 35 34 33 32 31 ADC_RDY VCM 4 27 SPISTE (1) 5 26 SPISIMO DNC 6 25 SPISOMI BG 7 24 SCLK VSS 8 23 PD_ALM/ADC Reset TX_REF 9 22 LED_ALM DNC 10 21 DIAD_END DNC 11 12 13 14 15 16 17 18 19 20 AFE_PDN 28 RX_DIG_GND 3 LED_DRV_SUP RESET RX_ANA_GND LED_DRV_SUP 29 LED_DRV_GND 2 TXP INP TXN CLKOUT LED_DRV_GND 30 LED_DRV_GND 1 TX_CTRL_SUP INN (4) DNC = Do not connect. PIN DESCRIPTIONS NAME (1) NO. FUNCTION DESCRIPTION ADC_RDY 28 Digital Output signal that indicates ADC conversion completion. Can be connected to the interrupt input pin of an external microcontroller. AFE_PDN 20 Digital AFE-only power-down input; active low. Can be connected to the port pin of an external microcontroller. BG 7 Reference CLKOUT 30 Digital Buffered 4-MHz output clock output. Can be connected to the clock input pin of an external microcontroller. DIAG_END 21 Digital Output signal that indicates completion of diagnostics. Can be connected to the port pin of an external microcontroller. DNC (1) 5, 6, 10 — Do not connect these pins. Leave as open-circuit. INN 1 Analog Receiver input pin. Connect to photodiode anode. INP 2 Analog Receiver input pin. Connect to photodiode cathode. LED_DRV_GND 12, 13, 16 Supply LED driver ground pin, H-bridge. Connect to common board ground. LED_DRV_SUP 17, 18 Supply LED driver supply pin, H-bridge. Connect to an external power supply capable of supplying the large LED current, which is drawn by this supply pin. LED_ALM 22 Digital Output signal that indicates an LED cable fault. Can be connected to the port pin of an external microcontroller. Decoupling capacitor for internal band-gap voltage to ground. (2.2-µF decoupling capacitor to ground, expected voltage = 1.0 V.) Leave pins as open circuit. Do not connect. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 9 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com PIN DESCRIPTIONS (continued) NAME 10 NO. FUNCTION DESCRIPTION PD_ALM/ADC Reset 23 Digital Output signal that indicates a PD sensor or cable fault. Can be connected to the port pin of an external microcontroller. In ADC bypass mode, the PD_ALM pin can be used to bring out the ADC reset signal. RESET 29 Digital AFE-only reset input, active low. Can be connected to the port pin of an external microcontroller. RX_ANA_GND 3, 36, 40 Supply Rx analog ground pin. Connect to common board ground. RX_ANA_SUP 33, 39 Supply Rx analog supply pin (2.0 V to 3.6 V); 0.1-µF decoupling capacitor to ground RX_DIG_GND 19, 32 Supply Rx digital ground pin. Connect to common board ground. RX_DIG_SUP 31 Supply Rx digital supply pin (2.0 V to 3.6 V); 0.1-µF decoupling capacitor to ground RXOUTN 34 Analog External ADC negative input when in ADC bypass mode RXOUTP 35 Analog External ADC positive input when in ADC bypass mode SCLK 24 SPI SPI clock pin SPISIMO 26 SPI SPI serial in master out SPISOMI 25 SPI SPI serial out master in SPI serial interface enable SPISTE 27 SPI TX_CTRL_SUP 11 Supply TX_REF 9 Reference TXN 14 Analog LED driver out B, H-bridge output. Connect to LED. TXP 15 Analog LED driver out B, H-bridge output. Connect to LED. VCM 4 Reference VSS 8 Supply Substrate ground. Connect to common board ground. XOUT 37 Digital Crystal oscillator pins. Connect an external 8-MHz crystal between these pins with the correct load capacitor (as specified by vendor) to ground. XIN 38 Digital Crystal oscillator pins. Connect an external 8-MHz crystal between these pins with the correct load capacitor (as specified by vendor) to ground. Transmit control supply pin, 5 V (0.1-µF decoupling capacitor to ground) Tx reference voltage Input common-mode voltage output. Connect a series resistor (1 kΩ) and a decoupling capacitor (10 nF) to ground. The voltage across the capacitor can be used to shield (guard) the INP, INM traces. Expected voltage = 0.9 V. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 TYPICAL CHARACTERISTICS At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless otherwise noted. 900 15.00 Stage 2 & Amb Cancel Disabled PRF = 600Hz TX_CTRL_SUP Current ( A) RX Analog Current ( A) Stage 2 & Amb Cancel Enabled 800 700 600 500 RX_ANA_SUP = Rx_DIG_SUP PRF = 600Hz Stage 2 Gain = 4 400 14.95 14.90 14.85 14.80 14.75 14.70 14.65 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 RX Supply Voltage (V) 3.0 600 Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Input Referred Noise Current, pA rms in 5Hz Bandwidth LED_DRV_SUP Current ( A) 47.8 47.6 47.4 47.2 47.0 46.8 46.6 46.4 500 400 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 200 0 600 500 400 700 300 200 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). Noise is calculated in 5Hz B/W. 0 0 10 20 30 40 Pleth Current ( A) 50 Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle 600 500 400 40 50 C004 = 1% = 5% = 10% = 15% = 20% = 25% 300 200 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA.) Noise is calculated in 5Hz band. 100 0 0 10 20 30 40 Pleth Current ( A) C005 Figure 6. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 300 Hz) 30 Figure 5. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 100 Hz) (1) = 1% = 5% = 10% = 15% = 20% = 25% 100 20 Pleth Current ( A) Input Referred Noise Current pA rms in 5Hz Bandwidth Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle 10 C003 Figure 4. LED_DRV_SUP CURRENT vs VOLTAGE Input Referred Noise Current pA rms in 5Hz Bandwidth For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). Noise is calculated in 5Hz B/W. 100 5.0 LED_DRV_SUP Voltage (V) 700 C002 300 0 3.2 5.0 = 1% = 5% = 10% = 15% = 20% = 25% With LED Current = 0mA 46.0 3.0 4.5 Figure 3. TX_CTRL_SUP CURRENT vs VOLTAGE 48.0 (1) 4.0 TX_CTRL_SUP Voltage (V) Figure 2. TOTAL Rx CURRENT vs VOLTAGE 46.2 3.5 C001 50 C006 Figure 7. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 600 Hz) Data at PRF = 625 Hz, 5% duty cycle. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 11 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless otherwise noted. Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle 700 600 500 1400 = 1% = 5% = 10% = 15% = 20% = 25% 400 300 200 For each RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). Noise is calculated in 5Hz band. 100 0 0 10 20 30 40 Input Referred Noise Current, pA rms in 5Hz Bandwidth Input Referred Noise Current, pA rms in 5Hz Bandwidth 800 1200 1000 800 200 0 0 Noise-Free Bits in 5Hz Bandwidth Noise-Free Bits in 5Hz Bandwidth 16 15 14 13 11 10 0 10 20 30 = 1% = 5% = 10% = 15% = 20% = 25% 40 Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle 12 11 0 Noise-Free Bits in 5Hz Bandwidth Noise-Free Bits in 5Hz Bandwidth 13 0 10 20 30 40 Pleth Current ( A) 12 30 40 50 C010 = 1% = 5% = 10% = 15% = 20% = 25% For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. 15 14 13 Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle 12 11 10 50 0 C011 Figure 12. NOISE-FREE BITS vs PLETH CURRENT (PRF = 600 Hz) (2) (2) 20 Pleth Current ( A) 16 14 10 10 = 1% = 5% = 10% = 15% = 20% = 25% Figure 11. NOISE-FREE BITS vs PLETH CURRENT (PRF = 300 Hz) 15 11 C008 13 10 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. 12 50 14 C009 Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle 40 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low pleth currents (0.125uA, 0.25uA & 0.5uA.) RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. Figure 10. NOISE-FREE BITS vs PLETH CURRENT (PRF = 100 Hz) 16 30 15 50 Pleth Current ( A) 20 Pleth Current ( A) Figure 9. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 2500 Hz) For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. 12 10 C007 Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). Noise is calculated in 5Hz band. 400 Figure 8. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 1200 Hz) 16 = 1% = 5% = 10% = 15% = 20% = 25% 600 50 Pleth Current ( A) Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle 10 20 30 40 Pleth Current ( A) = 1% = 5% = 10% = 15% = 20% = 25% 50 C012 Figure 13. NOISE-FREE BITS vs PLETH CURRENT (PRF = 1200 Hz) Data at PRF = 625 Hz, 5% duty cycle. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless otherwise noted. 120 110 14 TX Dynamic Range (dB) Noise-Free Bits in 5Hz Bandwidth 15 13 12 Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle For each setting RF adjusted for FullScale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. 11 10 0 10 20 30 = 1% = 5% = 10% = 15% = 20% = 25% 40 100 90 80 70 50 0 50 Pleth Current ( A) 100mA Range 150mA Range 200mA Range 60 60 80 100 C014 Figure 15. Tx DYNAMIC RANGE 500 500 400 400 300 300 DAC Step Error (uA) DAC Step Error (uA) 40 % of Full-Scale LED Current Figure 14. NOISE-FREE BITS vs PLETH CURRENT (PRF = 2500 Hz) 200 100 0 ±100 ±200 ±300 200 100 0 ±100 ±200 ±300 ±400 ±400 TX_REF = 0.5V ±500 TX_REF = 0.5V ±500 0 50 100 150 200 250 TX LED DAC Setting 0 50 100 150 200 250 TX LED DAC Setting C015 Figure 16. DAC CURRENT STEP vs Tx LED SETTING (Tx Range = 200 mA) C016 Figure 17. DAC CURRENT STEP vs Tx LED SETTING (Tx Range = 150 mA) 500 100 Expected + 1% 400 Expected ± 1% 300 80 200 TX Current (mA) DAC Step Error (uA) 20 C013 100 0 ±100 ±200 ±300 Actual DAC Current 60 40 20 ±400 TX_REF = 0.5V TX Reference Voltage = 0.5V 0 ±500 0 50 100 150 200 TX LED DAC Setting 250 0 Figure 18. DAC CURRENT STEP vs Tx LED SETTING (Tx Range = 100 mA) 50 100 150 200 TX LED DAC Setting C017 250 C018 Figure 19. Tx CURRENT LINEARITY (100-mA Range) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 13 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless otherwise noted. 200 160 Expected + 1% 140 Expected ± 1% 160 Actual DAC Current TX Current (mA) TX Current (mA) 120 Expected + 1% 180 Expected ± 1% 100 80 60 40 Actual DAC Current 140 120 100 80 60 40 20 20 TX Reference Voltage = 0.75V 0 TX Reference Voltage = 1.0V 0 0 50 100 150 200 0 250 TX LED DAC Setting 50 100 150 200 250 TX LED DAC Setting C019 Figure 20. Tx CURRENT LINEARITY (150-mA Range) C020 Figure 21. Tx CURRENT LINEARITY (200-mA Range) 800 2200 TX_RANGE = 150mA, Data from 2326 devices 2000 TX_RANGE = 150mA, Data from 7737 devices Number of Occurences Number of Occurences 1800 600 400 200 1600 1400 1200 1000 800 600 400 40 39 38 37 36 35 34 33 32 31 30 0 12 11.6 11.2 10.8 10.4 10 9.6 9.2 8.8 8.4 8 200 0 LED Current (mA) LED Current (mA) C021 C022 Figure 22. LED CURRENT WITH Tx DAC SETTING = 17 (10 mA) Figure 23. LED CURRENT WITH Tx DAC SETTING = 60 (35 mA) 1200 LED Current (mA) 165 163 LED Current (mA) C023 Figure 24. LED CURRENT WITH Tx DAC SETTING = 120 (70 mA) 14 161 159 157 151 149 147 145 143 77 76 75 74 73 72 71 70 69 68 67 0 66 0 65 200 64 200 141 400 139 400 600 137 600 800 135 Number of Occurences 1000 800 63 Number of Occurences 1000 TX_RANGE = 150mA, Data from 7737 devices 155 TX_RANGE = 150mA, Data from 7737 devices 153 1200 Submit Documentation Feedback C024 Figure 25. LED CURRENT WITH Tx DAC SETTING = 255 (150 mA) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 OVERVIEW BG RXOUTN RXOUTP RX_DIG_SUP RX_ANA_SUP RX_ANA_SUP TX_CTRL_SUP LED_DRV_SUP LED_DRV_SUP The AFE4490 is a complete analog front-end (AFE) solution targeted for pulse-oximeter applications. The device consists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED fault detection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is also integrated that functions from an external crystal. The device communicates to an external microcontroller or host processor using an SPI interface. Figure 26 shows a detailed block diagram for the AFE4490. The blocks are described in more detail in the following sections. Device Reference SPISTE RF SPISIMO SPI + CPD INP + + Stage 2 Gain TIA Filter SPISOMI SPICLK Digital Filter 4G ADC Buffer SPI Interface CF INN RF Photodiode CF Control VCM Timing Controller AFE_PDN ADC_RDY CF RESET LED TXN LED Driver LED Current Control DAC TXP DIAG_END DNC(1) DNC(1) DNC(1) Diagnostic Signals Diagnostics LED_ALM PD_ALM/ADC Reset VSS XOUT XIN CLKOUT RX_DIG_GND RX_DIG_GND RX_ANA_GND RX_ANA_GND RX_ANA_GND LED_DRV_GND LED_DRV_GND LED_DRV_GND TX_REF OSC 8 MHz Figure 26. Detailed Block Diagram Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 15 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com RECEIVER CHANNEL This section describes the receiver channel functionality. Receiver Front-End The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier that converts the input photodiode current into an appropriate voltage, as shown in Figure 27. The feedback resistor of the amplifier (RF) is programmable to support a wide range of photodiode currents. Available RF values include: 1 MΩ, 500 kΩ, 250 kΩ, 100 kΩ, 50 kΩ, 25 kΩ, and 10 kΩ. Rx SLED2 CONVLED2 LED2 CF RF RF ADC + CPD +Stage 2 TIA Amb SLED2_amb CONVLED2_amb Gain Buffer SLED1 ADC Output Rate PRF Sa/sec + û ADC CONVLED1 LED1 RF RF CF ADC Convert Ambient DAC I-V Amplifier Amb cancellation DAC Amb SLED1_amb ADC Clock CONVLED1_amb Filter Buffer ADC Ambient-cancellation current can be set digitally using SPI interface. Figure 27. Receiver Front-End The RF amplifier and the feedback capacitor (CF) form a low-pass filter for the input signal current. Always ensure that the low-pass filter has sufficiently high bandwidth (as shown by Equation 1) because the input current consists of pulses. For this reason, the feedback capacitor is also programmable. Available CF values include: 5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be used. Rx Sample Time R F ´ CF £ 10 (1) The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component resulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of a current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the pleth component alone. The amplifier has five programmable gain settings: 1, 1.5, 2, 3, and 4. The gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-bit ADC. The current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value can be digitally specified with the SPI interface. The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on, the amplifier output is filtered and sampled on capacitor CR. Similarly, the LED1 signal is sampled on the CLED1 capacitor when LED1 is ON. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to estimate the ambient signal on capacitors CLED2_amb and CLED1_amb. The sampling duration is termed the Rx sample time and is programmable for each signal, independently. Sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx sample time is used for all dynamic range calculations; the minimum time supported is 50 µs. 16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion takes a maximum of 25% of the pulse repetition period (PRP) and provides a single digital code at the ADC output. As discussed in the Receiver Timing section, the conversions are staggered so that the LED2 conversion starts after the end of the LED2 sample phase, and so on. This configuration also means that the Rx sample time for each signal is no greater than 25% of the pulse repetition period. Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values. Ambient Cancellation Scheme The receiver provides digital samples corresponding to ambient duration. The host processor (external to the AFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must then set the value of the ambient cancellation DAC using the SPI, as shown in Figure 28. Device Host Processor LED2 Data ADC Output Rate PRF Samples per Second Ambient (LED2) Data Front End (LED2 ± Ambient) Data SPI Interface ADC Rx Digital SPI Block LED1 Data Ambient Estimation Block Ambient information is available in the host processor. The processor can: * Read ambient data Ambient (LED1) Data * Estimate ambient value to be cancelled * Set the value to be used by the ambient cancellation DAC using the SPI of AFE (LED1 ± Ambient) Data Digital Control for Ambient-Cancellation DAC Figure 28. Ambient Cancellation Loop (Closed by the Host Processor) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 17 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the pleth component of the received signal, as shown in Figure 29. The amplifier gain is programmable to 1, 1.5, 2, 3, and 4. ICANCEL Cf Rg Rf IPLETH + IAMB Ri Rx VDIFF Ri Rf Rg ICANCEL Cf Value of ICANCEL set using the SPI interface. Figure 29. Front-End (I-V Amplifier and Cancellation Stage) The differential output of the second stage is VDIFF, as given by Equation 2: RF RF + IAMB ´ - ICANCEL ´ RG VDIFF = 2 ´ IPLETH ´ RI RI Where: RI = 100 kΩ, IPLETH = photodiode current pleth component, IAMB = photodiode current ambient component, and ICANCEL = the cancellation current DAC value (as estimated by the host processor). 18 Submit Documentation Feedback (2) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 Receiver Control Signals LED2 sample phase (SLED2): When this signal is high, the amplifier output corresponds to the LED2 on-time. The amplifier output is filtered and sampled into capacitor CLED2. To avoid settling effects resulting from the LED or cable, program SLED2 to start after the LED turns on. This settling delay is programmable. Ambient sample phase (SLED2_amb): When this signal is high, the amplifier output corresponds to the LED2 offtime and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is filtered and sampled into capacitor CLED2_amb. LED1 sample phase (SLED1): When this signal is high, the amplifier output corresponds to the LED1 on-time. The amplifier output is filtered and sampled into capacitor CLED1. To avoid settling effects resulting from the LED or cable, program SLED1 to start after the LED turns on. This settling delay is programmable. Ambient sample phase (SLED1_amb): When this signal is high, the amplifier output corresponds to the LED1 offtime and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is filtered and sampled into capacitor CLED1_amb. LED2 convert phase (CONVLED2): When this signal is high, the voltage sampled on CLED2 is buffered and applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code corresponding to the LED2 sample. Ambient convert phases (CONVLED2_amb, CONVLED1_amb): When this signal is high, the voltage sampled on CLED2_amb (or CLED1_amb) is buffered and applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code corresponding to the ambient sample. LED1 convert phase (CONVLED1): When this signal is high, the voltage sampled on CLED1 is buffered and applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code corresponding to the LED1 sample. Receiver Timing See Figure 30 for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, and the ADC conversion times for each channel. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 19 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com N+1 N+2 N+1 Plethysmograph Signal N N Photodiode Current Or I-V Output Ambient Level (Dark Level) SR, Sample RED SR_amb, Sample Ambient (RED Phase) CONVR, RED ADC Converts (RED ± Ambient) SIR, Sample IR SIR_amb, Sample Ambient (IR Phase) CONVIR, IR ADC Converts (IR ± Ambient) ADCLKR, Red ADC Sample Clock ADCLKIR, IR ADC Sample Clock RED ADC Output Data IR ADC Output Data RED RED N N+1 IR IR N-1 N NOTE: Relationship to the AFE4490EVM is: LED1 = IR and LED2 = RED. Figure 30. Rx Timing Diagram 20 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 CLOCKING AND TIMING SIGNAL GENERATION The crystal oscillator generates a master clock signal using an external 8-MHz crystal. A divide-by-2 block converts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, and diagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller. The clocking functionality is shown in Figure 31. Timer Module Divideby-2 ADC Diagnostics Module Oscillator XIN XOUT CLKOUT 4 MHz 8-MHz Crystal Figure 31. AFE Clocking TIMER MODULE See Figure 32 for a timing diagram detailing the various timing edges that are programmable using the timer module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bit counter (running off of the 4-MHz clock) to set the time-base. All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compare register compares the 16-bit counter value with the reference value specified in the PRF register. Every time that the 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to '0'. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 21 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com LED2 (RED LED) On Signal tLED LED on-time d 0.25 T. LED1 (IR LED) On Signal Rx sample time = tLED ± settle time. SLED2_amb, Sample Ambient [LED2 (RED) Phase] SLED1, Sample LED1 (IR) SLED1_amb, Sample Ambient [LED1 (IR) Phase] SLED2, Sample LED2 (RED) CONVLED2, Convert LED2 (RED) Sample CONVLED2_amb, Convert Ambient Sample [LED2 (RED) Phase] CONVLED1, Convert LED1 (IR) Sample CONVLED1_amb, Convert Ambient Sample [LED1 (IR) Phase] ADC Conversion ADC Reset 1.0 T 0.75 T 0.50 T 0.25 T 0T ADC_RDY Pin Pulse Repetition Period T = 1 / PRF NOTE: Programmable edges are shown in blue and red. Figure 32. AFE Control Signals 22 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 For the 11 signals in Figure 30, the start and stop edge positions are programmable with respect to the PRF period. Each signal uses a separate timer compare module that compares the counter value with preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI interface. When the counter value equals the start reference value, the output signal is set. When the counter value equals the stop reference value, the output signal is reset. Figure 33 shows a diagram of the timer compare register. With a 4-MHz clock, the edge placement resolution is 0.25 µs. The ADC conversion signal requires four pulses in each PRF clock period. The 11th timer compare register uses four sets of start and stop registers to control the ADC conversion signal. Set Output Signal Reset START STOP Start Reference Register Counter Input Stop Reference Register Enable Timer Compare Register Figure 33. Compare Register Enable Reset The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four sets of start and stop registers to control the ADC conversion signal, as shown in Figure 34. Reset CLKIN 16-Bit Counter Reset Counter Enable RED LED IR LED SR Sample RED SIR Sample IR SR_amb, Sample Ambient (red phase) SIR_amb, Sample Ambient (IR phase) S Start R Stop S Start R Stop S Start R Stop S Start R Stop S Start R Stop S Start R Stop Timer Compare 16-Bit Register 1 Timer Compare 16-Bit Register 2 Timer Compare 16-Bit Register 3 Timer Compare 16-Bit Register 4 Timer Compare 16-Bit Register 5 Timer Compare 16-Bit Register 6 En En En En En En En En En En PRF Pulse Timer Compare 16-Bit PRF Register Timer Compare 16-Bit Register 7 Start S Stop R Timer Compare 16-Bit Register 8 Start S Stop R Timer Compare 16-Bit Register 9 Start S Stop R Timer Compare 16-Bit Register 10 Start S Stop R CONVR, Convert RED Sample CONVIR, Convert IR Sample CONVIR_amb, Convert Ambient Sample (IR Phase) CONVR_amb, Convert Ambient Sample (RED Phase) START-A STOP-A En START-B STOP-B Timer Compare 16-Bit Register 11 START-C STOP-D En ADC Conversion START-D STOP-D Timer Module Figure 34. Timer Module Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 23 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com Using the Timer Module The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles. These timing instants and the corresponding registers are listed in Table 2. Note that the device does not restrict the values in these registers; thus, the start and end edges can be positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration of one clock cycle. The following steps describe the timer sequencing configuration: 1. With respect to the start of the PRP period (indicated by timing instant t0 in Figure 35), the sequence of conversions must be followed in order: convert LED2 → LED2 ambient → LED1 → LED1 ambient. 2. Also, starting from t0, the sequence of sampling instants must be staggered with respect to the respective conversions as follows: sample LED2 ambient → LED1 → LED1 ambient → LED2. 3. Finally, align the edges for the two LED pulses with the respective sampling instants. Table 2. Clock Edge Mapping to SPI Registers TIME INSTANT (See Figure 35 and Figure 36) 24 DESCRIPTION CORRESPONDING REGISTER ADDRESS AND REGISTER BITS EXAMPLE (Decimal) t0 Start of pulse repetition period No register control t1 Start of sample LED2 pulse Sample LED2 start count (bits 15-0 of register 01h) 4800 t2 End of sample LED2 pulse Sample LED2 end count (bits 15-0 of register 02h) 6399 t3 Start of LED2 pulse LED2 start count (bits 15-0 of register 03h) 4800 t4 End of LED2 pulse LED2 end count (bits 15-0 of register 04h) 6399 t5 Start of sample LED2 ambient pulse Sample ambient LED2 start count (bits 15-0 of register 05h) 0 t6 End of sample LED2 ambient pulse Sample ambient LED2 end count (bits 15-0 of register 06h) 1599 t7 Start of sample LED1 pulse Sample LED1 start count (bits 15-0 of register 07h) 1600 t8 End of sample LED1 pulse Sample LED1 end count (bits 15-0 of register 08h) 3199 t9 Start of LED1 pulse LED1 start count (bits 15-0 of register 09h) 1600 t10 End of LED1 pulse LED1 end count (bits 15-0 of register 0Ah) 3199 t11 Start of sample LED1 ambient pulse Sample ambient LED1 start count (bits 15-0 of register 0Bh) 3200 t12 End of sample LED1 ambient pulse Sample ambient LED1 end count (bits 15-0 of register 0Ch) 4700 t13 Start of convert LED2 pulse LED2 convert start count (bits 15-0 of register 0Dh) 0 t14 End of convert LED2 pulse LED2 convert end count (bits 15-0 of register 0Eh) 1599 t15 Start of convert LED2 ambient pulse LED2 ambient convert start count (bits 15-0 of register 0Fh) 1600 t16 End of convert LED2 ambient pulse LED2 ambient convert end count (bits 15-0 of register 10h) 3199 t17 Start of convert LED1 pulse LED1 convert start count (bits 15-0 of register 11h) 3200 t18 End of convert LED1 pulse LED1 convert end count (bits 15-0 of register 12h) 4799 t19 Start of convert LED1 ambient pulse LED1 ambient convert start count (bits 15-0 of register 13h) 4800 t20 End of convert LED1 ambient pulse LED1 ambient convert end count (bits 15-0 of register 14h) 6399 t21 Start of first ADC conversion reset pulse ADC reset 0 start count (bits 15-0 of register 15h) t22 End of first ADC conversion reset pulse ADC reset 0 end count (bits 15-0 of register 16h) 0 t23 Start of second ADC conversion reset pulse ADC reset 1 start count (bits 15-0 of register 17h) 1600 t24 End of second ADC conversion reset pulse ADC reset 0 end count (bits 15-0 of register 18h) 1600 t25 Start of third ADC conversion reset pulse ADC reset 2 start count (bits 15-0 of register 19h) 3200 t26 End of third ADC conversion reset pulse ADC reset 0 end count (bits 15-0 of register 1Ah) 3200 t27 Start of fourth ADC conversion reset pulse ADC reset 3 start count (bits 15-0 of register 1Bh) 4800 t28 End of fourth ADC conversion reset pulse ADC reset 0 end count (bits 15-0 of register 1Ch) 4800 t29 End of pulse repetition period Pulse repetition period count (bits 15-0 of register 1Dh) 6399 Submit Documentation Feedback — 0 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 LED2 (RED LED) On Signal t3 LED1 (IR LED) On Signal SLED2_amb, Sample Ambient [LED2 (RED) Phase] t9 t10 t6 t5 SLED1, Sample LED1 (IR) t7 t8 SLED1_amb, Sample Ambient [LED1 (IR) Phase] t11 t12 SLED2, Sample LED2 (RED) CONVLED2, Convert LED2 (RED) Sample t4 t1 t13 t2 t14 CONVLED2_amb, Convert Ambient Sample [LED2 (RED) Phase] t15 t16 CONVLED1, Convert LED1 (IR) Sample t17 t18 CONVLED1_amb, Convert Ambient Sample [LED1 (IR) Phase] t19 t20 ADC Conversion ADC Reset t23 t21 t22 t0 t25 t24 t27 t26 t28 Pulse Repetition Period, One Cycle t29 (1) RED = LED2, IR = LED1. Figure 35. Programmable Clock Edges Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 25 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com CONVLED2, Convert LED2 (RED) Sample t14 t13 CONVLED2_amb, Convert Ambient Sample [LED2 (RED) Phase] t16 t15 CONVLED1, Convert LED1 (IR) Sample t18 t17 CONVLED1_amb, Convert Ambient Sample [LED1 (IR) Phase] t20 t19 ADC Conversion One 4-MHz Clock Cycle t21 ADC Reset t0 t23 t22 t25 t27 t24 t26 Pulse Repetition Period, One Cycle t28 t29 (1) RED = LED2, IR = LED1. Figure 36. Relationship Between the ADC Reset and ADC Conversion Signals 26 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 ADC OPERATION AND AVERAGING MODULE The ADC reset signal must be positioned at 25% intervals of the pulse repetition period (that is, 0%, 25%, 50%, and 75%). After the falling edge of the ADC reset signal, the ADC conversion phase starts. Each ADC conversion takes 50 µs. There are two modes of operation: without averaging and with averaging. The averaging mode can average multiple ADC samples and reduce noise to improve dynamic range because the ADC conversion time is usually shorter than 25% of the pulse repetition period. Figure 37 shows a diagram of the averaging module. Rx Digital ADC Reset ADC 22-Bits ADC Output Rate PRF Samples per Second ADC Register 42 LED2 Data Register 43 LED2_Ambient Data Register 44 LED1 Data Register 45 LED1_Ambient Data LED2 Data Ambient (LED2) Data Averager ADC Reset ADC Convert Register 30 LED1 Data Ambient (LED1) Data Number of Averages ADC Clock Figure 37. Averaging Module Operation Without Averaging In this mode, the ADC outputs a digital sample one time for every 50 µs. At the next rising edge of the ADC reset signal, the first 22-bit conversion value is written into the result registers sequentially as follows (see Figure 38): • At the 25% reset signal, the first 22-bit ADC sample is written to register 2Ah. • At the 50% reset signal, the first 22-bit ADC sample is written to register 2Bh. • At the 75% reset signal, the first 22-bit ADC sample is written to register 2Ch. • At the next 0% reset signal, the first 22-bit ADC sample is written to register 2Dh. The contents of registers 2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh. At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out. Operation With Averaging In this mode, all ADC digital samples are accumulated and averaged after every 50 µs. At the next rising edge of the ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (see Figure 39): • At the 25% reset signal, the averaged 22-bit word is written to register 2Ah. • At the 50% reset signal, the averaged 22-bit word is written to register 2Bh. • At the 75% reset signal, the averaged 22-bit word is written to register 2Ch. • At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh. At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 27 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com The number of samples to be used per conversion phase is specified in the CONTROL1 register (NUMAV[7:0]). The user must specify the correct value for the number of averages, as described in Equation 3: 0.25 ´ Pulse Repetition Period NUMAV[7:0] + 1 = 50 ms (3) When the number of averages is '0', the averaging is disabled and only one ADC sample is written to the result registers. Note that he number of average conversions is limited by 25% of the PRF. For example, eight samples can be averaged with PRF = 625 Hz, and four samples can be averaged with PRF = 1250 Hz. ADC Conversion ADC Data 1 2 3 4 5 6 7 8 9 10 12 11 13 14 15 16 17 18 19 20 ADC Reset 0% 25% ADC data 1 are written into register 42. 50% ADC data 5 are written into register 43. 75% ADC data 9 are written into register 44. 0% ADC data 13 are written into register 45. Register 42 and register 43 are written into register 46. Register 44 and register 45 are written into register 47. ADC RDY Pin 0T Pulse Repetition Period T = 1 / PRF 1.0 T Figure 38. ADC Data Without Averaging (When Number of Averages = 0) 28 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 ADC Conversion ADC Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ADC Reset 0% 25% Average of ADC data 1 to 3 are written into register 42. 0% 50% 75% Average of ADC data 5 to 7 are written into register 43. Average of ADC data 9 to 11 are written into register 44. Average of ADC data 13 to 15 are written into register 45. Register 42 and register 43 are written into register 46. Register 44 and register 45 are written into register 47. ADC_RDY Pin Pulse repetition period T = 1/PRF 0T 1.0 T NOTE: Example is with three averages. The value of the NUMAVG[7:0] register bits = 2. Figure 39. ADC Data with Averaging Enabled Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 29 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com AFE ANALOG OUTPUT MODE (ADC Bypass Mode) The ADC bypass mode brings out the analog output voltage of the receiver front-end on two pins (RXOUTP, RXOUTN), around a common-mode voltage of approximately 0.9 V. In this mode, the internal ADC of the AFE4490 is disabled. Figure 40 shows a block diagram of this mode. RXOUTP INP + RXOUTN + Stage 2 Gain TIA û ADC INN Device Figure 40. AFE4490 Set to ADC Bypass Mode External û ADC In ADC bypass mode, one of the internal clocks (ADC_Reset) can be brought out on the PD_ALM pin, as shown in Figure 41. This signal can be used to convert each of the four phases (within every pulse repetition period). Additionally, the ADC_RDY signal can be used to synchronize the external ADC with the AFE. See Figure 42 for the timing of this mode. Use ADC_RDY to sync the external ADC with the AFE. Use the ADC_Reset signal on the PD_ALM pin to clock the external ADC. RXOUTP RXOUTN ADC_RDY PD_ALM Clocking INP + + TIA Stage 2 Gain Internal û ADC INN Device Figure 41. AFE4490 in ADC Bypass Mode with ADC_Reset to PD_ALM Pin 30 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 LED2 (Red LED) On Signal t3 LED1 (IR LED) On Signal t9 SLED2_amb, Sample Ambient [LED2 (RED) Phase] t10 t6 t5 SLED1, Sample LED1 (IR) t7 t8 SLED1_amb, Sample Ambient [LED1 (IR) Phase] t11 t12 SLED2, Sample LED2 (RED) ADC Reset (Pin 23) t4 t1 t23 t21 t22 t27 t25 t24 t2 t26 t28 ADC_RDY (Pin 28) t0 Pulse Repetition Period, One Cycle t29 NOTE: RED = LED2, IR = LED1. Figure 42. AFE4490 Analog Output Mode (ADC Bypass) Timing Diagram In ADC bypass mode, the ADC reset signal can be used to start conversions with the external ADC. Use registers 15h through 1Ch to position the ADC reset signal edges appropriately. Also, use the EN_RSTCLK on the PD_ALM pin register bit to bring out the ADC reset signal to the PD_ALM pin. ADC_RDY can be used to indicate the start of the pulse repetition period to the external ADC. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 31 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com RECEIVER SUBSYSTEM POWER PATH The block diagram in Figure 43 shows the AFE4490 Rx subsystem power routing. 1.8 V RX_ANA_SUP (2.0 V to 3.6 V) RX_ANA_SUP to 1.8-V Regulator Rx Analog Modules RX_DIG_SUP to 1.8-V Regulator RX_DIG_SUP (2.0 V to 3.6 V) 1.8 V Rx I/O Block Rx Digital I/O Pins Device Figure 43. Receive Subsystem Power Routing 32 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 TRANSMIT SECTION The transmit section integrates the LED driver and the LED current control section with 8-bit resolution. This integration is designed to meet the specified dynamic range (based on a 1-sigma LED current noise). The LED2 and LED1 reference currents can be independently set. The current source (ILED) locally regulates and ensures that the actual LED current tracks the specified reference. Two LED driver schemes are supported: • An H-bridge drive for a two-terminal back-to-back LED package, as shown in Figure 44. The minimum Hbridge supply voltage must be 2.5 V + (maximum voltage drop across the LED). • A push-pull drive for a three-terminal LED package; see Figure 45. The minimum external supply voltage = 2.0 V + (maximum voltage drop across the LED). This value is the nominal value and depends on the registry LED current settings (refer to the LED_RANGE[1:0] bits in the LEDCNTRL register). 5-V Supply H-Bridge Supply External Supply Tx CBULK H-Bridge LED2_ON H-Bridge Driver LED1_ON LED2_ON Or LED1_ON LED2 Current Reference ILED LED Current Control 8-Bit Resolution LED1 Current Reference Register LED2 Current Reference Register LED1 Current Reference Figure 44. Transmit: H-Bridge Drive Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 33 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com 5-V Supply External Supply H-Bridge Supply CBULK Tx LED2_ON H-Bridge Driver LED1_ON LED2_ON Or LED1_ON LED2 Current Reference ILED LED Current Control 8-Bit Resolution LED1 Current Reference Register RED Current Reference Register IR Current Reference Figure 45. Transmit: Push-Pull LED Drive for Common Anode LED Configuration 34 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 Transmitter Power Path The block diagram in Figure 46 shows the AFE4490 Tx subsystem power routing. TX_CTRL_SUP_5V Tx Reference and Control LED Current Control DAC Tx LED Bridge LED_DRV_SUP_5V Device Figure 46. Transmit Subsystem Power Routing LED Power Reduction During Periods of Inactivity The diagram in Figure 47 shows how LED bias current passes 50 µA whenever LED_ON occurs. In order to minimize power consumption in periods of inactivity, the LED_ON control must be turned off. 1 PA 50uA 0 mA to 200 mA (See the LEDRANGE bits in the LEDCNTRL register.) LED_ON Figure 47. LED Bias Current Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 35 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com DIAGNOSTICS The device includes diagnostics to detect open or short conditions of the LED and photosensor, LED current profile feedback, and cable on or off detection. Photodiode-Side Fault Detection Figure 48 shows the diagnostic for the photodiode-side fault detection. Internal LED_DRV_SUP 10 k: Internal LED_DRV_SUP 10 k: Cable Rx On/Off INM To Rx Front-End INP Rx On/Off 1 PA GND Wires 10 k: 10 k: PD Wires LED Wires Cable Legend Figure 48. Photodiode Diagnostic 36 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 Transmitter-Side Fault Detection Figure 49 shows the diagnostic for the transmitter-side fault detection. Internal LED_DRV_SUP Cable LED 2 LED 1 TX_OUTP SW3 10 k: SW1 10 k: D SW2 TX_OUTM SW4 C GND Wires PD Wires LED Wires Cable Legend Figure 49. Transmitter Diagnostic Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 37 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com Diagnostics Module The diagnostics module, when enabled, checks for nine types of faults sequentially. The results of all faults are latched in 11 separate flags. At the end of the sequence, the state of the 11 flags are combined to generate two interrupt signals: PD_ALM for photodiode-related faults and LED_ALM for transmit-related faults. The status of all flags can also be read using the SPI interface. Table 3 details each fault and flag used. Note that the diagnostics module requires all AFE blocks to be enabled in order to function reliably. Table 3. Fault and Flag Diagnostics (1) MODULE SEQ. FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 FLAG8 FLAG9 FLAG10 FLAG11 — — No fault 0 0 0 0 0 0 0 0 0 0 0 1 Rx INP cable shorted to LED cable 1 2 Rx INM cable shorted to LED cable 3 Rx INP cable shorted to GND cable 4 Rx INM cable shorted to GND cable 5 PD open or shorted 1 1 6 Tx OUTM line shorted to GND cable 7 Tx OUTP line shorted to GND cable 8 LED open or shorted 1 1 9 LED open or shorted PD LED (1) FAULT 1 1 1 1 1 1 Resistances below 10 kΩ are considered to be shorted. Figure 50 shows the timing for the diagnostic function. DIAG_EN Register Bit = 1 Diagnostic State Machine Diagnostic State Machine Diagnostic Ends Diagnostic Starts DIAG_END Pin tWIDTH = Four 4-MHz Clock Cycles tDIAG Figure 50. Diagnostic Timing Diagram By default, the diagnostic function takes tDIAG = 8 ms to complete after the DIAG_EN register bit is enabled. By setting the EN_SLOW_DIAG register bit (CONTROL2 register, bit D8) the diagnostic time can be increased to 16 ms. 38 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 SERIAL PROGRAMMING INTERFACE The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data output), SPISIMO (serial interface data input), and SPISTE (serial interface enable). The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts out data from the device. SCLK features a Schmitt-triggered input and clocks data out on SPISOMI. Data are clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK low. The SPISOMI (SPI serial out master in) pin is used with SCLK to clock out the AFE4490 data. The SPISIMO (SPI serial in master out) pin is used with SCLK to clock in data to the AFE4490. The SPISTE (SPI serial interface enable) pin enables the serial interface to clock data on the SPISIMO pin in to the device. READING AND WRITING DATA The device has a set of internal registers that can be accessed by the serial programming interface formed by the SPISTE, SCLK, SPISIMO, and SPISOMI pins. Writing Data When SPISTE is low, • Serially shifting bits into the device is enabled. • Serial data (on the SPISIMO pin) are latched at every SCLK rising edge. • The serial data are loaded into the register at every 32nd SCLK rising edge. In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and the remaining 24 bits form the register data. Figure 51 shows a diagram of the write timing. SPISTE SPISIMO A7 A6 A1 A0 D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0 SCLK 'RQ¶W FDUH, can be high or low. Figure 51. AFE SPI Write Timing Diagram Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 39 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com Reading Data The AFE4490 includes a mode where the contents of the internal registers can be read back on the SPISOMI pin. This mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the AFE. To enable this mode, first set the SPI_READ register bit using the SPI write command, as described in the Writing Data section. In the next command, specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin. Figure 52 shows a timing diagram for the SPI read operation. SPISTE SPISIMO A7 A6 A1 A0 SPISOMI D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0 SCLK 'RQ¶W FDUH, can be high or low. (1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE. (2) Specify the register address of the content that must be readback on bits A[7:0]. (3) The AFE outputs the contents of the specified register on the SPISOMI pin. Figure 52. AFE SPI Read Timing Diagram(1)(2)(3) Register Initialization After power-up, the internal registers must be initialized to the default values. This initialization can be done in one of two ways: • Through a hardware reset by applying a low-going pulse on the RESET pin, or • By applying a software reset. Using the serial interface, set SW_RESET (bit D3 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets to '0'. In this case, the RESET pin is kept high (inactive). AFE SPI Interface Design Considerations Note that when the AFE4490 is deselected, the SPISOMI, CLKOUT, ADC_RDY, PD_ALM, LED_ALM, and DIAG_END digital output pins do not enter a 3-state mode. This condition, therefore, must be taken into account when connecting multiple devices to the SPI port and for power-management considerations. AFE REGISTER MAP The AFE consists of a set of registers that can be used to configure it, such as receiver timings, I-V amplifier settings, transmit LED currents, and so forth. The registers and their contents are listed in Table 4. These registers can be accessed using the AFE SPI interface. 40 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 Table 4. AFE Register Map ADDRESS REGISTER DATA Hex Dec D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_RST DIAG_EN TIM_COUNT_RST SPI_READ NAME 0 0 0 LED2STC 01 1 0 0 0 0 0 0 0 0 LED2STC[15:0] LED2ENDC 02 2 0 0 0 0 0 0 0 0 LED2ENDC[15:0] LED2LEDSTC 03 3 0 0 0 0 0 0 0 0 LED2LEDSTC[15:0] LED2LEDENDC 04 4 0 0 0 0 0 0 0 0 LED2LEDENDC[15:0] ALED2STC 05 5 0 0 0 0 0 0 0 0 ALED2STC[15:0] ALED2ENDC 06 6 0 0 0 0 0 0 0 0 ALED2ENDC[15:0] LED1STC 07 7 0 0 0 0 0 0 0 0 LED1STC[15:0] LED1ENDC 08 8 0 0 0 0 0 0 0 0 LED1ENDC[15:0] LED1LEDSTC 09 9 0 0 0 0 0 0 0 0 LED1LEDSTC[15:0] LED1LEDENDC 0A 10 0 0 0 0 0 0 0 0 LED1LEDENDC[15:0] ALED1STC 0B 11 0 0 0 0 0 0 0 0 ALED1STC[15:0] ALED1ENDC 0C 12 0 0 0 0 0 0 0 0 ALED1ENDC[15:0] LED2CONVST 0D 13 0 0 0 0 0 0 0 0 LED2CONVST[15:0] LED2CONVST 0E 14 0 0 0 0 0 0 0 0 LED2CONVEND[15:0] ALED2CONVST 0F 15 0 0 0 0 0 0 0 0 ALED2CONVST[15:0] ALED2CONVEND 10 16 0 0 0 0 0 0 0 0 ALED2CONVEND[15:0] LED1CONVST 11 17 0 0 0 0 0 0 0 0 LED1CONVST[15:0] LED1CONVEND 12 18 0 0 0 0 0 0 0 0 LED1CONVEND[15:0] ALED1CONVST 13 19 0 0 0 0 0 0 0 0 ALED1CONVST[15:0] ALED1CONVEND 14 20 0 0 0 0 0 0 0 0 ALED1CONVEND[15:0] ADCRSTCNT0 15 21 0 0 0 0 0 0 0 0 ADCRSTCT0[15:0] ADCRSTENDCT0 16 22 0 0 0 0 0 0 0 0 ADCRENDCT0[15:0] ADCRSTSTCT1 17 23 0 0 0 0 0 0 0 0 ADCRSTCT1[15:0] ADCRSTENDCT1 18 24 0 0 0 0 0 0 0 0 ADCRENDCT1[15:0] ADCRSTSTCT2 19 25 0 0 0 0 0 0 0 0 ADCRSTCT2[15:0] ADCRSTENDCT2 1A 26 0 0 0 0 0 0 0 0 ADCRENDCT2[15:0] 1B 27 0 0 0 0 0 0 0 0 ADCRSTCT3[15:0] 1C 28 0 0 0 0 0 0 0 0 ADCRENDCT3[15:0] PRPCOUNT 1D 29 0 0 0 0 0 0 0 0 PRPCT[15:0] CONTROL1 1E 30 0 0 0 0 0 0 0 0 0 0 0 0 SPARE1 1F 31 0 0 0 0 0 0 0 0 0 0 0 0 CLKALMPIN[2:0] 0 0 0 TIMEREN ADCRSTSTCT3 ADCRSTENDCT3 0 NUMAV[7:0] 0 0 0 0 0 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 41 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com Table 4. AFE Register Map (continued) ADDRESS REGISTER DATA 42 Hex Dec D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 TIAGAIN 20 32 0 0 0 0 0 0 0 0 ENSEPGAN 0 0 0 0 0 0 0 TIA_AMB_GAIN 21 33 0 0 0 0 FLTRCNRSEL STAGE2EN NAME 0 0 0 LEDCNTRL 22 34 0 0 0 0 0 0 CONTROL2 23 35 0 0 0 0 0 SPARE2 24 36 0 0 0 0 0 SPARE3 25 37 0 0 0 0 0 0 SPARE4 26 38 0 0 0 0 0 RESERVED1 27 39 0 0 0 0 RESERVED2 28 40 0 0 0 ALARM 29 41 0 0 0 LED RANGE[1:0] 0 0 0 0 0 0 PDNAFE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPSCLED 0 PDNRX 0 0 0 INNSCLED 0 0 0 PDNTX 0 0 INPSCGND 0 0 INNSCGND 0 0 PDSC 0 0 PDOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LED2VAL 2A 42 LED2VAL[23:0] ALED2VAL 2B 43 ALED2VAL[23:0] 44 LED1VAL[23:0] 2D 45 ALED1VAL[23:0] LED2-ALED2VAL 2E 46 LED2-ALED2VAL[23:0] LED1-ALED1VAL 2F 47 LED1-ALED1VAL[23:0] DIAG 30 48 0 0 0 0 0 0 0 0 0 0 Submit Documentation Feedback LED_ALM 2C PD_ALM LED1VAL ALED1VAL 0 RF_LED2[2:0] OUTNSHGND 0 0 CF_LED2[4:0] ALMPINCLKEN 0 0 RF_LED1[2:0] OUTPSHGND 0 0 CF_LED1[4:0] D0 EN_SLOW_DIAG 0 D1 LEDSC 0 0 0 D2 XTALDIS 0 0 0 0 D3 LED2OPEN 0 0 0 D4 LED2[7:0] TXBRGMOD EN_ADC_BYP 0 TX_REF0 0 TX_REF1 0 0 STG2GAIN[2:0] D5 LED1[7:0] 0 0 D6 LED1OPEN AMBDAC[3:0] D7 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 AFE REGISTER DESCRIPTION CONTROL0: Control Register 0 (Address = 00h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 TIM_ SW_RST DIAG_EN COUNT_ RST SPI_ READ This register is used for AFE software and count timer reset, diagnostics enable, and SPI read functions. Bits D[23:4] Must be '0' Bit D3 SW_RST: Software reset 0 = No action (default after reset) 1 = Software reset applied; resets all internal registers to the default values and self-clears to '0' Bit D2 DIAG_EN: Diagnostic enable 0 = No Action (default after reset) 1 = Diagnostic mode is enabled and the diagnostics sequence starts when this bit is set. At the end of the sequence, all fault statuses are stored in the DIAG: Diagnostics Flag Register. Afterwards, the DIAG_EN register bit self-clears to '0'. Bit D1 TIM_CNT_RST: Timer counter reset 0 = Disables timer counter reset, required for normal timer operation (default after reset) 1 = Timer counters are in reset state Bit D0 SPI READ: SPI read 0 = SPI read is disabled (default after reset) 1 = SPI read is enabled LED2STC: Sample LED2 Start Count Register (Address = 01h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2STC[15:0] D3 D2 D1 D0 LED2STC[15:0] This register sets the start timing value for the LED2 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] LED2STC[15:0]: Sample LED2 start count The contents of this register can be used to position the start of the sample LED2 signal with respect to the pulse repetition period (PRP), as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 43 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com LED2ENDC: Sample LED2 End Count Register (Address = 02h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2ENDC[15:0] D3 D2 D1 D0 LED2ENDC[15:0] This register sets the end timing value for the LED2 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] LED2ENDC[15:0]: Sample LED2 end count The contents of this register can be used to position the end of the sample LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value LED2LEDSTC: LED2 LED Start Count Register (Address = 03h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2LEDSTC[15:0] D3 D2 D1 D0 LED2LEDSTC[15:0] This register sets the start timing value for when the LED2 signal turns on. Bits D[23:16] Must be '0' Bits D[15:0] LED2LEDSTC[15:0]: LED2 start count The contents of this register can be used to position the start of the LED2 with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value LED2LEDENDC: LED2 LED End Count Register (Address = 04h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2LEDENDC[15:0] D3 D2 D1 D0 LED2LEDENDC[15:0] This register sets the end timing value for when the LED2 signal turns off. Bits D[23:16] Must be '0' Bits D[15:0] LED2LEDENDC[15:0]: LED2 end count The contents of this register can be used to position the end of the LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value 44 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 ALED2STC: Sample Ambient LED2 Start Count Register (Address = 05h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED2STC[15:0] D3 D2 D1 D0 ALED2STC[15:0] This register sets the start timing value for the ambient LED2 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] ALED2STC[15:0]: Sample ambient LED2 start count The contents of this register can be used to position the start of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value ALED2ENDC: Sample Ambient LED2 End Count Register (Address = 06h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED2ENDC[15:0] D3 D2 D1 D0 ALED2ENDC[15:0] This register sets the end timing value for the ambient LED2 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] ALED2ENDC[15:0]: Sample ambient LED2 end count The contents of this register can be used to position the end of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value LED1STC: Sample LED1 Start Count Register (Address = 07h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1STC[15:0] D3 D2 D1 D0 LED1STC[15:0] This register sets the start timing value for the LED1 signal sample. Bits D[23:17] Must be '0' Bits D[16:0] LED1STC[15:0]: Sample LED1 start count The contents of this register can be used to position the start of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 45 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com LED1ENDC: Sample LED1 End Count (Address = 08h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1ENDC[15:0] D3 D2 D1 D0 LED1ENDC[15:0] This register sets the end timing value for the LED1 signal sample. Bits D[23:17] Must be '0' Bits D[16:0] LED1ENDC[15:0]: Sample LED1 end count The contents of this register can be used to position the end of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value LED1LEDSTC: LED1 LED Start Count Register (Address = 09h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1LEDSTC[15:0] D3 D2 D1 D0 LED1LEDSTC[15:0] This register sets the start timing value for when the LED1 signal turns on. Bits D[23:16] Must be '0' Bits D[15:0] LED1LEDSTC[15:0]: LED1 start count The contents of this register can be used to position the start of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value LED1LEDENDC: LED1 LED End Count Register (Address = 0Ah, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1LEDENDC[15:0] D3 D2 D1 D0 LED1LEDENDC[15:0] This register sets the end timing value for when the LED1 signal turns off. Bits D[23:16] Must be '0' Bits D[15:0] LED1LEDENDC[15:0]: LED1 end count The contents of this register can be used to position the end of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value 46 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 ALED1STC: Sample Ambient LED1 Start Count Register (Address = 0Bh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED1STC[15:0] D3 D2 D1 D0 ALED1STC[15:0] This register sets the start timing value for the ambient LED1 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] ALED1STC[15:0]: Sample ambient LED1 start count The contents of this register can be used to position the start of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value ALED1ENDC: Sample Ambient LED1 End Count Register (Address = 0Ch, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED1ENDC[15:0] D3 D2 D1 D0 ALED1ENDC[15:0] This register sets the end timing value for the ambient LED1 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] ALED1ENDC[15:0]: Sample ambient LED1 end count The contents of this register can be used to position the end of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value LED2CONVST: LED2 Convert Start Count Register (Address = 0Dh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2CONVST[15:0] D3 D2 D1 D0 LED2CONVST[15:0] This register sets the start timing value for the LED2 conversion. Bits D[23:16] Must be '0' Bits D[15:0] LED2CONVST[15:0]: LED2 convert start count The contents of this register can be used to position the start of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 47 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com LED2CONVST: LED2 Convert End Count Register (Address = 0Eh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2CONVST[15:0] D3 D2 D1 D0 LED2CONVST[15:0] This register sets the end timing value for the LED2 conversion. Bits D[23:16] Must be '0' Bits D[15:0] LED2CONVST[15:0]: LED2 convert end count The contents of this register can be used to position the end of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value ALED2CONVST: LED2 Ambient Convert Start Count Register (Address = 0Fh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED2CONVST[15:0] D3 D2 D1 D0 ALED2CONVST[15:0] This register sets the start timing value for the ambient LED2 conversion. Bits D[23:16] Must be '0' Bits D[15:0] ALED2CONVST[15:0]: LED2 ambient convert start count The contents of this register can be used to position the start of the LED2 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value ALED2CONVEND: LED2 Ambient Convert End Count Register (Address = 10h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED2CONVEND[15:0] D3 D2 D1 D0 ALED2CONVEND[15:0] This register sets the end timing value for the ambient LED2 conversion. Bits D[23:16] Must be '0' Bits D[15:0] ALED2CONVEND[15:0]: LED2 ambient convert end count The contents of this register can be used to position the end of the LED2 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value 48 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 LED1CONVST: LED1 Convert Start Count Register (Address = 11h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1CONVST[15:0] D3 D2 D1 D0 LED1CONVST[15:0] This register sets the start timing value for the LED1 conversion. Bits D[23:16] Must be '0' Bits D[15:0] LED1CONVST[15:0]: LED1 convert start count The contents of this register can be used to position the start of the LED1 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value LED1CONVEND: LED1 Convert End Count Register (Address = 12h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1CONVEND[15:0] D3 D2 D1 D0 LED1CONVEND[15:0] This register sets the end timing value for the LED1 conversion. Bits D[23:16] Must be '0' Bits D[15:0] LED1CONVEND[15:0]: LED1 convert end count The contents of this register can be used to position the end of the LED1 conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value ALED1CONVST: LED1 Ambient Convert Start Count Register (Address = 13h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED1CONVST[15:0] D3 D2 D1 D0 ALED1CONVST[15:0] This register sets the start timing value for the ambient LED1 conversion. Bits D[23:16] Must be '0' Bits D[15:0] ALED1CONVST[15:0]: LED1 ambient convert start count The contents of this register can be used to position the start of the LED1 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 49 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com ALED1CONVEND: LED1 Ambient Convert End Count Register (Address = 14h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED1CONVEND[15:0] D3 D2 D1 D0 ALED1CONVEND[15:0] This register sets the end timing value for the ambient LED1 conversion. Bits D[23:16] Must be '0' Bits D[15:0] ALED1CONVEND[15:0]: LED1 ambient convert end count The contents of this register can be used to position the end of the LED1 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 0 = 0000h 1 = PRP value ADCRSTCNT0: ADC Reset 0 Start Count Register (Address = 15h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTCNT0[15:0] D3 D2 D1 D0 ADCRSTCNT0[15:0] This register sets the start position of the ADC0 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTCNT0[15:0]: ADC RESET 0 start count The contents of this register can be used to position the start of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details. ADCRSTENDCT0: ADC Reset 0 End Count Register (Address = 16h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTENDCT0[15:0] D3 D2 D1 D0 ADCRSTENDCT0[15:0] This register sets the end position of the ADC0 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTENDCT0[15:0]: ADC RESET 0 end count The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details. 50 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 ADCRSTSTCT1: ADC Reset 1 Start Count Register (Address = 17h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTSTCT1[15:0] D3 D2 D1 D0 ADCRSTSTCT1[15:0] This register sets the start position of the ADC1 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTSTCT1[15:0]: ADC RESET 1 start count The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details. ADCRSTENDCT1: ADC Reset 1 End Count Register (Address = 18h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTENDCT1[15:0] D3 D2 D1 D0 ADCRSTENDCT1[15:0] This register sets the end position of the ADC1 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTENDCT1[15:0]: ADC RESET 1 end count The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details. ADCRSTSTCT2: ADC Reset 2 Start Count Register (Address = 19h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTSTCT2[15:0] D3 D2 D1 D0 ADCRSTSTCT2[15:0] This register sets the start position of the ADC2 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTSTCT2[15:0]: ADC RESET 2 start count The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 51 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com ADCRSTENDCT2: ADC Reset 2 End Count Register (Address = 1Ah, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTENDCT2[15:0] D3 D2 D1 D0 ADCRSTENDCT2[15:0] This register sets the end position of the ADC2 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTENDCT2[15:0]: ADC RESET 2 end count The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details. ADCRSTSTCT3: ADC Reset 3 Start Count Register (Address = 1Bh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTSTCT3[15:0] D3 D2 D1 D0 ADCRSTSTCT3[15:0] This register sets the start position of the ADC3 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTSTCT3[15:0]: ADC RESET 3 start count The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details. ADCRSTENDCT3: ADC Reset 3 End Count Register (Address = 1Ch, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTENDCT3[15:0] D3 D2 D1 D0 ADCRSTENDCT3[15:0] This register sets the end position of the ADC3 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTENDCT3[15:0]: ADC RESET 3 end count The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details. 52 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 PRPCOUNT: Pulse Repetition Period Count Register (Address = 1Dh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 PRPCOUNT[15:0] D3 D2 D1 D0 PRPCOUNT[15:0] This register sets the device pulse repetition period count. Bits D[23:16] Must be '0' Bits D[15:0] PRPCOUNT[15:0]: Pulse repetition period count The contents of this register can be used to set the pulse repetition period (in number of clock cycles of the 4-MHz clock). CONTROL1: Control Register 1 (Address = 1Eh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 CLKALMPIN[2:0] TIMEREN NUMAV[7:0] This register configures the clock alarm pin, timer, and number of averages. Bits D[23:12] Must be '0' Bits D[11:9] CLKALMPIN[2:0]: Clocks on ALM pins Internal clocks can be brought to the PD_ALM and LED_ALM pins for monitoring. Note that the CLKALMPIN[2:0] register bits must be set before using this register bit. Table 5 defines the settings for the two alarm pins. Bit D8 TIMEREN: Timer enable 0 = Timer module is disabled and all internal clocks are off (default after reset) 1 = Timer module is enabled Bits D[7:0] NUMAV[7:0]: Number of averages Specify an 8-bit value corresponding to the number of ADC samples to be averaged – 1. For example, to average four ADC samples, set NUMAV[7:0] equal to 3. Table 5. PD_ALM and LED_ALM Pin Settings CLKALMPIN[2:0] PD_ALM PIN SIGNAL LED_ALM PIN SIGNAL 000 Sample LED2 Sample LED1 001 LED2 pulse LED1 pulse 010 Sample LED2 Sample LED1 pulse 011 LED2 convert LED1 convert 100 LED2 ambient LED1 ambient 101 No output No output 110 No output No output 111 No output No output Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 53 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com SPARE1: SPARE1 Register For Future Use (Address = 1Fh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is a spare register and is reserved for future use. Bits D[23:0] Must be '0' TIAGAIN: Transimpedance Amplifier Gain Setting Register (Address = 20h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 ENSEP GAIN 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 CF_LED1[4:0] RF_LED1[2:0] This register sets the device transimpedance amplifier gain mode and feedback resistor and capacitor values. Bits D[23:16] Must be '0' Bit D15 ENSEPGAIN: Enable separate gain mode 0 = The RF and CF values are the same for both LED2 and LED1 signals; the value specified by the RF_LED2[2:0] register bits is used (default after reset) 1 = The RF value is different for the LED2 and LED1 signals; the values are specified by the RF_LED1[2:0] and RF_LED2[2:0] register bits Bits D[14:8] Must be '0' Bits D[7:3] CF_LED1[4:0]: Program CF for LED1 00000 = 5 pF (default after reset) 00001 = 5 pF + 5 pF 00010 = 15 pF + 5 pF 00100 = 25 pF + 5 pF 01000 = 50 pF + 5 pF 10000 = 150 pF + 5 pF Note that any combination of these CF settings is also supported by setting multiple bits to '1'. For example, to obtain CF = 100 pF, set D[7:3] = 01111. Bits D[2:0] RF_LED1[2:0]: Program RF for LED1 000 001 010 011 54 = = = = 500 kΩ (default after reset) 250 kΩ 100 kΩ 50 kΩ 100 101 110 111 Submit Documentation Feedback = = = = 25 kΩ 10 kΩ 1 MΩ None Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 TIA_AMB_GAIN: Transimpedance Amplifier and Ambient Cancellation Stage Gain Register (Address = 21h, Reset Value = 0000h) D23 D22 0 0 D11 D10 0 D21 D20 0 0 D9 D8 D19 D18 D17 D16 AMBDAC[3:0] D7 D6 STG2GAIN[2:0] D5 D4 D15 D14 D13 D12 FLTR CNRSEL STAGE2 EN 0 0 D3 D2 D1 D0 CF_LED2[4:0] RF_LED2[2:0] This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner frequency. Bits D[23:20] Must be '0' Bits D[19:16] AMBDAC[3:0]: Ambient DAC value These bits set the value of the cancellation current. 0000 0001 0010 0011 0100 0101 0110 0111 Bit D15 = = = = = = = = 0 µA (default after reset) 1 µA 2 µA 3 µA 4 µA 5 µA 6 µA 7 µA 1000 1001 1010 1011 1100 1101 1110 1111 = = = = = = = = 8 µA 9 µA 10 µA Do not Do not Do not Do not Do not use use use use use FLTRCNRSEL: Filter corner selection 0 = 500-Hz filter corner (default after reset) 1 = 1000-Hz filter corner Bit D14 STAGE2EN: Stage 2 enable 0 = Stage 2 is bypassed (default after reset) 1 = Stage 2 is enabled with the gain value specified by the STG2GAIN[2:0] bits Bits D[13:11] Must be '0' Bits D[10:8] STG2GAIN[2:0]: Stage 2 gain setting 000 = 0 reset) 001 = 3 010 = 6 011 = 9 Bits D[7:3] dB, or linear gain of 1 (default after dB, or linear gain of 1.414 dB, or linear gain of 2 dB, or linear gain of 2.818 100 101 110 111 = = = = 12 dB, or linear gain of 4 Do not use Do not use Do not use CF_LED2[4:0]: Program CF for LED2 00000 = 5 pF (default after reset) 00001 = 5 pF + 5 pF 00010 = 15 pF + 5 pF 00100 = 25 pF + 5 pF 01000 = 50 pF + 5 pF 10000 = 150 pF + 5 pF Note that any combination of these CF settings is also supported by setting multiple bits to '1'. For example, to obtain CF = 100 pF, set D[7:3] = 01111. Bits D[2:0] RF_LED2[2:0]: Program RF for LED2 000 001 010 011 = = = = 500 kΩ 250 kΩ 100 kΩ 50 kΩ 100 101 110 111 = = = = 25 kΩ 10 kΩ 1 MΩ None Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 55 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com LEDCNTRL: LED Control Register (Address = 22h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D17 D16 D15 LED_RANGE[1:0] D5 D13 D12 LED1[7:0] D4 LED1[7:0] D14 D3 D2 D1 D0 LED2[7:0] This register sets the LED current range and the LED1 and LED2 drive current. Bits D[23:18] Must be '0' Bits D[17:16] LED_RANGE[1:0]: LED range These bits program the full-scale LED current range for Tx. Table 6 details the settings. Bits D[15:8] LED1[7:0]: Program LED current for LED1 signal Use these register bits to specify the LED current setting for LED1 (default after reset is 00h). The nominal value of the LED current is given by Equation 4, where the full-scale LED current is either 0 mA, 50 mA, 75 mA, 100 mA, 150 mA, or 200 mA (as specified by the LED_RANGE[1:0] register bits). Bits D[7:0] LED2[7:0]: Program LED current for LED2 signal Use these register bits to specify the LED current setting for LED2 (default after reset is 00h). The nominal value of LED current is given by Equation 5, where the full-scale LED current is either 0 mA, 50 mA, 75 mA, 100 mA, 150 mA, or 200 mA (as specified by the LED_RANGE[1:0] register bits). Table 6. Full-Scale LED Current across Tx Reference Voltage Settings LED_RANGE[1:0] 0.5 V (TX_REF[1:0] = 01) 1.0 V (TX_REF[1:0] = 10) 00 (default after reset) 150 mA 100 mA 200 mA 01 75 mA 50 mA 100 mA 10 150 mA 100 mA 200 mA 11 Tx is off Tx is off Tx is off LED1[7:0] 256 LED2[7:0] 256 56 LED CURRENT RANGE FOR Tx REFERENCE VOLTAGE 0.75 V (TX_REF[1:0] = 00) ´ Full-Scale Current (4) ´ Full-Scale Current (5) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 CONTROL2: Control Register 2 (Address = 23h, Reset Value = 0000h) D23 D22 D21 D18 D17 D16 D15 D14 D13 D12 0 EN_ADC _BYP 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XTAL DIS EN_ SLOW_ DIAG 0 0 0 0 0 PDNTX PDNRX PDNAFE 0 0 D11 D10 0 D19 TX_SUP_ 3V 0 TXBRG MOD D20 This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes. Bits D[23:19] Must be '0' Bits D[18:17] TX_REF[1:0]: Tx reference voltage These bits set the transmitter reference voltage. This Tx reference voltage is available on the device TX_REF pin. 00 01 10 11 = = = = 0.75-V Tx reference voltage (default value after reset) 0.5-V Tx reference voltage 1.0-V Tx reference voltage 0.75-V Tx reference voltage Bit D16 Must be '0' Bit D15 EN_ADC_BYP: ADC bypass mode enable 0 = Normal mode, the internal ADC is active (default after reset) 1 = ADC bypass mode, the analog signal is output to the ADC_BYPP and ADC_BYPN pins Bits D[14:12] Must be '0' Bit D11 TXBRGMOD: Tx bridge mode 0 = LED driver is configured as an H-bridge (default after reset) 1 = LED driver is configured as a push-pull Bit D10 Must be '0' Bit D9 XTALDIS: Crystal disable mode 0 = The crystal module is enabled; the 8-MHz crystal must be connected to the XIN and XOUT pins 1 = The crystal module is disabled; an external 8-MHz clock must be applied to the XIN pin Bit D8 EN_SLOW_DIAG: Fast diagnostics mode enable 0 = Fast diagnostics mode, 8 ms (default value after reset) 1 = Slow diagnostics mode, 16 ms Bits D[7:3] Must be '0' Bit D2 PDN_TX: Tx power-down 0 = The Tx is powered up (default after reset) 1 = Only the Tx module is powered down Bit D1 PDN_RX: Rx power-down 0 = The Rx is powered up (default after reset) 1 = Only the Rx module is powered down Bit D0 PDN_AFE: AFE power-down 0 = The AFE is powered up (default after reset) 1 = The entire AFE is powered down (including the Tx, Rx, and diagnostics blocks) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 57 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com SPARE2: SPARE2 Register For Future Use (Address = 24h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is a spare register and is reserved for future use. Bits D[23:0] Must be '0' SPARE3: SPARE3 Register For Future Use (Address = 25h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is a spare register and is reserved for future use. Bits D[23:0] Must be '0' SPARE4: SPARE4 Register For Future Use (Address = 26h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is a spare register and is reserved for future use. Bits D[23:0] Must be '0' RESERVED1: RESERVED1 Register For Factory Use Only (Address = 27h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is reserved for factory use. Readback values vary between devices. Bits D[23:0] Must be '0' RESERVED2: RESERVED2 Register For Factory Use Only (Address = 28h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is reserved for factory use. Readback values vary between devices. Bits D[23:0] 58 Must be '0' Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 ALARM: Alarm Register (Address = 29h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 ALMPIN CLKEN 0 0 0 0 0 0 0 This register controls the Alarm pin functionality. Bits D[23:8] Must be '0' Bit D7 ALMPINCLKEN: Alarm pin clock enable 0 = Disables the monitoring of internal clocks; the PD_ALM and LED_ALM pins function as diagnostic fault alarm output pins (default after reset) 1 = Enables the monitoring of internal clocks; these clocks can be brought out on PD_ALM and LED_ALM selectively (depending on the value of the CLKALMPIN[2:0] register bits). Bits D[6:0] Must be '0' LED2VAL: LED2 Digital Sample Value Register (Address = 2Ah, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 LED2VAL[23:0] D11 D10 D9 D8 D7 D6 D5 LED2VAL[23:0] This register contains the digital value of the latest LED2 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Bits D[23:0] LED2VAL[23:0]: LED2 digital value This register contains the digital value of the latest LED2 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. ALED2VAL: Ambient LED2 Digital Sample Value Register (Address = 2Bh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 ALED2VAL[23:0] D11 D10 D9 D8 D7 D6 D5 ALED2VAL[23:0] This register contains the digital value of the latest LED2 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Bits D[23:0] ALED2VAL[23:0]: LED2 ambient digital value This register contains the digital value of the latest LED2 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 59 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com LED1VAL: LED1 Digital Sample Value Register (Address = 2Ch, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 LED1VAL[23:0] D11 D10 D9 D8 D7 D6 D5 LED1VAL[23:0] This register contains the digital value of the latest LED1 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Bits D[23:0] LED1VAL[23:0]: LED1 digital value This register contains the digital value of the latest LED1 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. ALED1VAL: Ambient LED1 Digital Sample Value Register (Address = 2Dh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 ALED1VAL[23:0] D11 D10 D9 D8 D7 D6 D5 ALED1VAL[23:0] This register contains the digital value of the latest LED1 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Bits D[23:0] ALED1VAL[23:0]: LED1 ambient digital value This register contains the digital value of the latest LED1 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. LED2-ALED2VAL: LED2-Ambient LED2 Digital Sample Value Register (Address = 2Eh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 LED2-ALED2VAL[23:0] D11 D10 D9 D8 D7 D6 D5 LED2-ALED2VAL[23:0] This register contains the digital value of the LED2 sample after the LED2 ambient is subtracted. The host processor must readout this register before the next sample is converted by the AFE. Bits D[23:0] LED2-ALED2VAL[23:0]: (LED2 – LED2 ambient) digital value This register contains the digital value of the LED2 sample after the LED2 ambient is subtracted. The host processor must readout this register before the next sample is converted by the AFE. 60 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 LED1-ALED1VAL: LED1-Ambient LED1 Digital Sample Value Register (Address = 2Fh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 LED1-ALED1VAL[23:0] D11 D10 D9 D8 D7 D6 D5 LED1-ALED1VAL[23:0] This register contains the digital value of the LED1 sample after the LED1 ambient is subtracted. The host processor must readout this register before the next sample is converted by the AFE. Bits D[23:0] LED1-ALED1VAL[23:0]: (LED1 – LED1 ambient) digital value This register contains the digital value of the LED1 sample after the LED1 ambient is subtracted from it. The host processor must readout this register before the next sample is converted by the AFE. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 61 AFE4490 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 www.ti.com DIAG: Diagnostics Flag Register (Address = 30h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 PD_ALM D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LED_ ALM LED1 OPEN LED2 OPEN LEDSC OUTPSH GND OUTNSH GND PDOC PDSC INNSC GND INPSC GND INNSC LED INPSC LED This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin. Bits D[23:13] Read only Bit D12 PD_ALM: Power-down alarm status diagnostic flag This bit indicates the status of PD_ALM (and the PD_ALM pin). 0 = No fault (default after reset) 1 = Fault present Bit D11 LED_ALM: LED alarm status diagnostic flag This bit indicates the status of LED_ALM (and the LED_ALM pin). 0 = No fault (default after reset) 1 = Fault present Bit D10 LED1OPEN: LED1 open diagnostic flag This bit indicates that LED1 is open. 0 = No fault (default after reset) 1 = Fault present Bit D9 LED2OPEN: LED2 open diagnostic flag This bit indicates that LED2 is open. 0 = No fault (default after reset) 1 = Fault present Bit D8 LEDSC: LED short diagnostic flag This bit indicates an LED short. 0 = No fault (default after reset) 1 = Fault present Bit D7 OUTPSHGND: OUTP to GND diagnostic flag This bit indicates that OUTP is shorted to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit D6 OUTNSHGND: OUTN to GND diagnostic flag This bit indicates that OUTN is shorted to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit D5 PDOC: PD open diagnostic flag This bit indicates that PD is open. 0 = No fault (default after reset) 1 = Fault present Bit D4 PDSC: PD short diagnostic flag This bit indicates a PD short. 0 = No fault (default after reset) 1 = Fault present 62 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 AFE4490 www.ti.com Bit D3 SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013 INNSCGND: INN to GND diagnostic flag This bit indicates a short from the INN pin to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit D2 INPSCGND: INP to GND diagnostic flag This bit indicates a short from the INP pin to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit D1 INNSCLED: INN to LED diagnostic flag This bit indicates a short from the INN pin to the LED cable. 0 = No fault (default after reset) 1 = Fault present Bit D0 INPSCLED: INP to LED diagnostic flag This bit indicates a short from the INP pin to the LED cable. 0 = No fault (default after reset) 1 = Fault present Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4490 63 PACKAGE OPTION ADDENDUM www.ti.com 22-Feb-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) AFE4490RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 AFE4490RHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 25-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant AFE4490RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 AFE4490RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AFE4490RHAR VQFN RHA 40 2500 367.0 367.0 38.0 AFE4490RHAT VQFN RHA 40 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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