IRF IRF6619 Directfet power mosfet Datasheet

PD - 96917
IRF6619
DirectFET™ Power MOSFET ‚
Typical values (unless otherwise specified)
l
l
l
l
l
l
l
l
Low Profile (<0.7 mm)
VDSS
VGS
RDS(on)
RDS(on)
Dual Sided Cooling Compatible 
20V max ±20V max 1.65mΩ@ 10V 2.2mΩ@ 4.5V
Ultra Low Package Inductance
Qg tot Qgd
Qgs2
Qrr
Qoss Vgs(th)
Optimized for High Frequency Switching above 1MHz 
Ideal for CPU Core DC-DC Converters
38nC
13nC
3.5nC
18nC
22nC
2.0V
Optimized for Sync. FET socket of Sync. Buck Converter
Low Conduction Losses
Compatible with existing Surface Mount Techniques 
MX
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
SQ
SX
ST
MQ
MX
DirectFET™ ISOMETRIC
MX
MT
Description
The IRF6619 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the
lowest on-state resistance in a package that has the footprint of an SO-8 and only 0.7 mm profile. The DirectFET package is compatible with
existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual
sided cooling to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%.
The IRF6619 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching
losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of processors
operating at higher frequencies. The IRF6619 has been optimized for parameters that are critical in synchronous buck operating from 12 volt
buss converters including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6619 offers particularly low Rds(on) and high
Cdv/dt immunity for synchronous FET applications.
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
20
V
VGS
Gate-to-Source Voltage
±20
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
ID @ TA = 70°C
Continuous Drain Current, VGS
ID @ TC = 25°C
Continuous Drain Current, VGS
IDM
EAS (Thermally limited)
Pulsed Drain Current
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
Parameter
e
e
h
@ 10V h
@ 10V k(Package Limited)
e
Notes:
VGS, Gate-to-Source Voltage (V)
Typical R DS (on) (mΩ)
TJ = 125°C
2.0
TJ = 25°C
2.0
4.0
6.0
8.0
VGS, Gate-to-Source Voltage (V)
10.0
Fig 1. Typical On-Resistance Vs. Gate Voltage
 Click on this section to link to the appropriate technical paper.
‚ Click on this section to link to the DirectFET Website.
ƒ Repetitive rating; pulse width limited by max. junction temperature.
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240
mJ
See Fig. 14, 15, 17a, 17b,
A
mJ
4.0
1.0
A
240
ID = 30A
3.0
24
150
f
6.0
5.0
30
12
ID= 16A
10
VDS = 16V
VDS= 10V
8
6
4
2
0
0
20
40
60
80
100
QG Total Gate Charge (nC)
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
„ Limited by TJmax, starting TJ = 25°C, L = 0.86mH, RG = 25Ω, IAS =
24A, VGS =10V. Part not recommended for use above this value.
† Surface mounted on 1 in. square Cu board, steady state.
‰ TC measured with thermocouple mounted to top (Drain) of part.
1
2/10/05
IRF6619
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min.
Conditions
Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
20
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
14
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
1.65
2.2
–––
2.2
3.0
V
VGS = 0V, ID = 250µA
mV/°C Reference to 25°C, ID = 1mA
mΩ
VGS = 10V, ID = 30A g
VGS = 4.5V, ID = 24A g
VDS = VGS, ID = 250µA
VGS(th)
Gate Threshold Voltage
1.55
–––
2.45
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-5.8
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Forward Transconductance
89
–––
–––
Qg
Total Gate Charge
–––
38
57
Pre-Vth Gate-to-Source Charge
–––
10.2
–––
VDS = 10V
VGS = 4.5V
IGSS
Qgs1
VDS = 16V, VGS = 0V
VDS = 16V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
S
VDS = 10V, ID = 24A
Qgs2
Post-Vth Gate-to-Source Charge
–––
3.5
–––
Qgd
Gate-to-Drain Charge
–––
13.2
–––
ID = 16A
Qgodr
Gate Charge Overdrive
–––
11.1
–––
See Fig. 17
Qsw
Switch Charge (Qgs2 + Qgd)
–––
16.7
–––
Qoss
Output Charge
–––
22
–––
nC
RG
Gate Resistance
–––
–––
2.3
Ω
td(on)
Turn-On Delay Time
–––
21
–––
tr
Rise Time
–––
71
–––
td(off)
Turn-Off Delay Time
–––
25
–––
tf
Fall Time
–––
9.3
–––
Ciss
Input Capacitance
–––
5040
nC
VDS = 10V, VGS = 0V
VDD = 16V, VGS = 4.5Vg
ID = 24A
ns
Clamped Inductive Load
–––
VGS = 0V
pF
VDS = 10V
Coss
Output Capacitance
–––
1580
–––
Crss
Reverse Transfer Capacitance
–––
780
–––
Min.
Typ. Max. Units
–––
–––
ƒ = 1.0MHz
Diode Characteristics
Parameter
IS
Continuous Source Current
Pulsed Source Current
MOSFET symbol
30
(Body Diode)
ISM
A
–––
–––
Conditions
showing the
integral reverse
240
p-n junction diode.
(Body Diode)e
VSD
Diode Forward Voltage
–––
0.8
1.0
V
TJ = 25°C, IS = 24A, VGS = 0V g
trr
Reverse Recovery Time
–––
29
44
ns
TJ = 25°C, IF = 24A
Qrr
Reverse Recovery Charge
–––
18
27
nC
di/dt = 100A/µs g
Notes:
ƒ Repetitive rating; pulse width limited by max. junction temperature.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRF6619
Absolute Maximum Ratings
Parameter
PD @TC = 25°C
h
Power Dissipation h
Power Dissipation k
TP
Peak Soldering Temperature
TJ
Operating Junction and
TSTG
Storage Temperature Range
Power Dissipation
PD @TA = 25°C
PD @TA = 70°C
Max.
Units
2.8
W
1.8
89
270
°C
-40 to + 150
Thermal Resistance
Parameter
hl
Junction-to-Ambient il
Junction-to-Ambient jl
Junction-to-Case kl
RθJA
Typ.
Max.
–––
45
Junction-to-Ambient
RθJA
RθJA
RθJC
RθJ-PCB
12.5
–––
20
–––
–––
1.4
Junction-to-PCB Mounted
Linear Derating Factor
1.0
h
Units
°C/W
–––
0.017
W/°C
100
D = 0.50
0.20
0.10
0.05
0.02
0.01
Thermal Response ( Z thJA )
10
1
0.1
τJ
0.01
R1
R1
τJ
τ1
R2
R2
τ2
τ1
R3
R3
τC
τ
τ3
τ2
τ4
τ3
τ4
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.001
τi (sec)
Ri (°C/W)
R4
R4
0.6784
0.00086
17.299
0.57756
17.566
8.94
9.4701
106
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient †
Notes:
† Surface mounted on 1 in. square Cu board, steady state.
‡ Used double sided cooling , mounting pad.
ˆ Mounted on minimum footprint full size board with metalized
‰ TC measured with thermocouple incontact with top (Drain) of part.
Š Rθ is measured at TJ of approximately 90°C.
back and with small clip heatsink.
† Surface mounted on 1 in. square Cu
board (still air).
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‡ Mounted to a PCB with a
thin gap filler and heat sink.
(still air)
ˆ Mounted on minimum
footprint full size board with
metalized back and with small
clip heatsink (still air)
3
IRF6619
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
10
2.5V
1
≤ 60µs PULSE WIDTH
Tj = 25°C
100
BOTTOM
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
2.5V
10
≤ 60µs PULSE WIDTH
Tj = 150°C
0.1
1
0.1
1
10
0.1
VDS , Drain-to-Source Voltage (V)
1
10
VDS , Drain-to-Source Voltage (V)
Fig 4. Typical Output Characteristics
Fig 5. Typical Output Characteristics
100.0
1.5
Typical R DS(on) (Normalized)
ID, Drain-to-Source Current(Α)
ID = 30A
TJ = 150°C
TJ = 25°C
TJ = -40°C
10.0
1.0
VDS = 10V
VGS = 10V
1.0
≤ 60µs PULSE WIDTH
0.1
1.5
2.0
2.5
3.0
3.5
0.5
4.0
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
(mΩ)
DS(on)
Ciss
4000
Typical R
C, Capacitance (pF)
80 100 120 140 160
TA= 25°C
9
VGS = 3.0V
8
VGS = 3.5V
7
VGS = 4.5V
VGS = 4.0V
VGS = 5.0V
6
VGS = 10V
5
4
Coss
3
Crss
2
1
0
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
4
60
10
Coss = Cds + Cgd
2000
40
Fig 7. Normalized On-Resistance vs. Temperature
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
6000
20
TJ , Junction Temperature (°C)
Fig 6. Typical Transfer Characteristics
8000
0
0
40
80
120
160
200
ID, Drain Current (A)
Fig 9. Typical On-Resistance Vs.
Drain Current and Gate Voltage
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IRF6619
1000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
1000.0
100.0
TJ = 150°C
TJ = 25°C
10.0
TJ = -40°C
1.0
VGS = 0V
0.6
1.0
1.4
100
100µsec
10
1msec
10msec
1
TA = 25°C
Tj = 150°C
Single Pulse
0.1
0.1
0.2
OPERATION IN THIS AREA
LIMITED BY R DS (on)
0.01
1.8
VSD , Source-to-Drain Voltage (V)
Fig 10. Typical Source-Drain Diode Forward Voltage
1.00
10.00
100.00
Fig11. Maximum Safe Operating Area
180
2.5
LIMITED BY PACKAGE
VGS(th) Gate threshold Voltage (V)
160
140
ID , Drain Current (A)
0.10
VDS , Drain-toSource Voltage (V)
120
100
80
60
40
20
0
25
50
75
100
125
2.0
ID = 250µA
1.5
1.0
0.5
150
-75
TC , Case Temperature (°C)
-50
-25
0
25
50
75
100
125
150
TJ , Junction Temperature ( °C )
Fig 12. Maximum Drain Current vs. Case Temperature
Fig 13. Typical Threshold Voltage vs. Junction
Temperature
1000
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
Avalanche Current (A)
100
10
0.01
1
0.05
0.10
0.1
0.01
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
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5
IRF6619
EAR , Avalanche Energy (mJ)
300
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 17a, 17b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 3)
Single Pulse
ID = 24A
200
100
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
EAS, Single Pulse Avalanche Energy (mJ)
1000
15V
ID
12A
15A
BOTTOM 24A
TOP
800
D.U.T
RG
600
20V
VGS
400
DRIVER
L
VDS
+
V
- DD
IAS
A
0.01Ω
tp
Fig 17a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
200
0
25
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy Vs. Drain Current
Current Regulator
Same Type as D.U.T.
I AS
Fig 17b. Unclamped Inductive Waveforms
LD
VDS
50KΩ
12V
.2µF
+
.3µF
VDD -
+
V
- DS
D.U.T.
D.U.T
VGS
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
3mA
IG
ID
Current Sampling Resistors
Fig 19a. Switching Time Test Circuit
Fig 18a. Gate Charge Test Circuit
Id
Vds
Vgs
VDS
90%
10%
Vgs(th)
VGS
Qgs1 Qgs2
td(on)
Qgd
Qgodr
Fig 18b. Gate Charge Waveform
6
tr
td(off)
tf
Fig 19b. Switching Time Waveforms
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IRF6619
D.U.T
Driver Gate Drive
+
ƒ
+
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
di/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
D=
Period
P.W.
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
+
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
-
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 20. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
DirectFET™ Substrate and PCB Layout, MX Outline
(Medium Size Can, X-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
VGS
This includes all recommendations
for stencil and substrate designs.
1- Drain
2- Drain
3- Source
4- Source
5- Gate
6- Drain
7- Drain
6
1
3
5
4
7
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2
7
IRF6619
DirectFET™ Outline Dimension, MX Outline
(Medium Size Can, X-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
DIMENSIONS
METRIC
CODE MIN
MAX
A
6.35
6.25
B
5.05
4.80
C
3.95
3.85
D
0.45
0.35
E
0.72
0.68
F
0.72
0.68
G
1.42
1.38
H
0.84
0.80
J
0.42
0.38
K
0.88 1.01
L
2.28
2.41
M
0.59
0.70
N
0.03
0.08
P
0.08
0.17
IMPERIAL
MAX
MAX
0.246 0.250
0.189 0.201
0.152 0.156
0.014 0.018
0.027 0.028
0.027 0.028
0.054 0.056
0.032 0.033
0.015 0.017
0.035 0.039
0.090 0.095
0.023 0.028
0.001 0.003
0.003 0.007
DirectFET™ Part Marking
8
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IRF6619
DirectFET™ Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6619). For 1000 parts on 7" reel,
order IRF6619TR1
REEL DIMENSIONS
STANDARD OPTION (QTY 4800)
TR1 OPTION (QTY 1000)
IMPERIAL
IMPERIAL
METRIC
METRIC
MIN
MIN
MAX
MIN
MAX
MAX
12.992
6.9
N.C
177.77 N.C
N.C
0.795
0.75
N.C
19.06
N.C
N.C
0.504
0.53
0.50
13.5
0.520
12.8
0.059
0.059
1.5
N.C
N.C
N.C
3.937
2.31
58.72
N.C
N.C
N.C
N.C
N.C
N.C
0.53
0.724
13.50
0.488
0.47
11.9
N.C
0.567
12.01
0.469
0.47
11.9
N.C
0.606
12.01
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.2/05
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9