TI1 LM2700Q 600khz/1.25mhz, 2.5a, step-up pwm dc/dc converter Datasheet

LM2700Q
600kHz/1.25MHz, 2.5A, Step-up PWM DC/DC Converter
General Description
Features
The LM2700Q is a step-up DC/DC converter with a 3.6A,
80mΩ internal switch and pin selectable operating frequency.
With the ability to produce 500mA at 8V from a single Lithium
Ion battery, the LM2700Q is an ideal part for biasing LCD displays. The LM2700Q can be operated at switching frequencies of 600kHz and 1.25MHz allowing for easy filtering and
low noise. An external compensation pin gives the user flexibility in setting frequency compensation, which makes possible the use of small, low ESR ceramic capacitors at the
output. The LM2700Q features continuous switching at light
loads and operates with a switching quiescent current of
2.0mA at 600kHz and 3.0mA at 1.25MHz. The LM2700Q is
available in a low profile 14-lead TSSOP package or a 14-lead
LLP package.
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AEC-Q100 Grade 2 qualified (-40°c to +105°c)
3.6A, 0.08Ω, internal switch
Operating input voltage range of 2.2V to 12V
Input undervoltage protection
Adjustable output voltage up to 17.5V
600kHz/1.25MHz pin selectable frequency operation
Over temperature protection
Small 14-Lead TSSOP or LLP package
Applications
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LCD Bias Supplies
Handheld Devices
Portable Applications
GSM/CDMA Phones
Digital Cameras
Typical Application Circuit
30186101
600 kHz Operation
Connection Diagram
Top View
30186104
14-Lead TSSOP
© 2012 Texas Instruments Incorporated
301861 SNVS794
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LM2700Q 600kHz/1.25MHz, 2.5A, Step-up PWM DC/DC Converter
March 1, 2012
LM2700Q
Ordering Information
Order Number
Package Type
NSC Package Drawing
Supplied As
LM2700QMT-ADJ
TSSOP-14
MTC14
94 Units, Rail
LM2700QMTX-ADJ
TSSOP-14
MTC14
2500 Units, Tape and Reel
Pin Description
Pin
Name
Function
1
VC
Compensation network connection. Connected to the output of the voltage error amplifier.
2
FB
Output voltage feedback input.
3
SHDN
Shutdown control input, active low.
4
AGND
Analog ground.
5
PGND
Power ground. PGND pins must be connected together directly at the part.
6
PGND
Power ground. PGND pins must be connected together directly at the part.
7
PGND
Power ground. PGND pins must be connected together directly at the part.
8
SW
Power switch input. Switch connected between SW pins and PGND pins.
9
SW
Power switch input. Switch connected between SW pins and PGND pins.
10
SW
Power switch input. Switch connected between SW pins and PGND pins.
11
NC
Pin not connected internally.
12
VIN
Analog power input.
13
FSLCT
14
NC
Switching frequency select input. VIN = 1.25MHz. Ground = 600kHz.
Connect to ground.
Block Diagram
30186103
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The LM2700Q utilizes a PWM control scheme to regulate the
output voltage over all load conditions. The operation can best
be understood referring to the block diagram and Figure 1 of
the Operation section. At the start of each cycle, the oscillator
sets the driver logic and turns on the NMOS power device
conducting current through the inductor, cycle 1 of Figure 1
(a). During this cycle, the voltage at the VC pin controls the
peak inductor current. The VC voltage will increase with larger
loads and decrease with smaller. This voltage is compared
with the summation of the SW voltage and the ramp compensation. The ramp compensation is used in PWM architectures to eliminate the sub-harmonic oscillations that occur
during duty cycles greater than 50%. Once the summation of
the ramp compensation and switch voltage equals the VC
voltage, the PWM comparator resets the driver logic turning
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LM2700Q
off the NMOS power device. The inductor current then flows
through the schottky diode to the load and output capacitor,
cycle 2 of Figure 1 (b). The NMOS power device is then set
by the oscillator at the end of the period and current flows
through the inductor once again.
The LM2700Q has dedicated protection circuitry running during normal operation to protect the IC. The Thermal Shutdown
circuitry turns off the NMOS power device when the die temperature reaches excessive levels. The UVP comparator protects the NMOS power device during supply power startup
and shutdown to prevent operation at voltages less than the
minimum input voltage. The OVP comparator is used to prevent the output voltage from rising at no loads allowing full
PWM operation over all load conditions. The LM2700Q also
features a shutdown mode decreasing the supply current to
5µA.
Detailed Description
LM2700Q
Vapor Phase (60 sec.)
Infrared (15 sec.)
ESD Susceptibility (Note 4)
Human Body Model
Machine Model
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
VIN
SW Voltage
FB Voltage
VC Voltage
12V
18V
7V
SHDN Voltage (Note 1)
FSLCT (Note 1)
Maximum Junction Temperature
Power Dissipation(Note 3)
Lead Temperature
215°C
220°C
2kV
200V
Operating Conditions
Operating Junction
Temperature Range
(Note 5)
Storage Temperature
Supply Voltage
SW Voltage
0.965V ≤ VC ≤ 1.565V
7V
12V
150°C
Internally Limited
300°C
−40°C to +105°C
−65°C to +150°C
2.2V to 12V
17.5V
Electrical Characteristics
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature
Range (TJ = −40°C to +125°C) Unless otherwise specified. VIN =2.2V and IL = 0A, unless otherwise specified.
Symbol
IQ
Typ
(Note 6)
Max
(Note 5)
Units
FB = 2.2V (Not Switching)
FSLCT = 0V
1.2
2
mA
FB = 2.2V (Not Switching)
FSLCT = VIN
1.3
2
mA
5
20
µA
1.26
1.2915
V
Parameter
Quiescent Current
Conditions
Min
(Note 5)
VSHDN = 0V
VFB
Feedback Voltage
ICL(Note 7)
Switch Current Limit
VIN = 2.7V (Note 8)
%VFB/ΔVIN
Feedback Voltage Line
Regulation
2.2V ≤ VIN ≤ 12.0V
IB
FB Pin Bias Current
(Note 9)
VIN
Input Voltage Range
2.2
gm
Error Amp Transconductance ΔI = 5µA
40
AV
Error Amp Voltage Gain
DMAX
Maximum Duty Cycle
FSLCT = Ground
DMIN
Minimum Duty Cycle
FSLCT = Ground
15
FSLCT = VIN
30
fS
Switching Frequency
ISHDN
Shutdown Pin Current
1.2285
2.55
78
FSLCT = Ground
480
FSLCT = VIN
4.3
A
0.07
%/V
0.5
40
12
V
155
290
µmho
nA
135
V/V
85
%
%
600
720
kHz
MHz
1.25
1.5
VSHDN = VIN
0.008
1
VSHDN = 0V
−0.5
−1
0.02
20
µA
80
150
mΩ
1
IL
Switch Leakage Current
VSW = 18V
RDSON
Switch RDSON (Note 10)
VIN = 2.7V, ISW = 2A
ThSHDN
SHDN Threshold
Output High
UVP
µA
0.9
0.6
0.6
0.3
V
On Threshold
1.95
2.05
2.2
V
Off Threshold
1.85
1.95
2.1
V
Output Low
θJA
3.6
0.02
Thermal Resistance
(Note 11)
TSSOP, package only
150
LLP, package only
45
V
°C/W
Note 1: This voltage should never exceed VIN.
Note 2: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended
to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance,
θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance. The maximum allowable power dissipation at any ambient
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Note 4: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin.
Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% tested
or guaranteed through statistical analysis. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Note 6: Typical numbers are at 25°C and represent the most likely norm.
Note 7: Duty cycle affects current limit due to ramp generator.
Note 8: Current limit at 0% duty cycle. See TYPICAL PERFORMANCE section for Switch Current Limit vs. VIN
Note 9: Bias current flows into FB pin.
Note 10: Does not include the bond wires. Measured directly at the die.
Note 11: Refer to National's packaging website for more detailed thermal information and mounting techniques for the LLP and TSSOP packages.
Typical Performance Characteristics
Efficiency vs. Load Current
(VOUT = 8V, fS = 600 kHz)
Efficiency vs. Load Current
(VOUT = 8V, fS = 1.25 MHz)
30186126
30186125
Efficiency vs. Load Current
(VOUT = 5V, fS = 600 kHz)
Efficiency vs. Load Current
(VOUT = 12V, fS = 600 kHz)
30186134
30186135
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LM2700Q
temperature is calculated using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and
the regulator will go into thermal shutdown.
LM2700Q
Switch Current Limit vs. Temperature
Switch Current Limit vs. VIN
30186120
30186122
RDSON vs. VIN
(ISW = 2A)
IQ vs. VIN
(600 kHz, not switching)
30186128
30186127
IQ vs. VIN
(600 kHz, switching)
IQ vs. VIN
(1.25 MHz, not switching)
30186129
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30186121
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LM2700Q
IQ vs. VIN
(1.25 MHz, switching)
IQ vs. VIN
(In shutdown)
30186119
30186118
Frequency vs. VIN
(600 kHz)
Frequency vs. VIN
(1.25 MHz)
30186123
30186124
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LM2700Q
Operation
30186102
FIGURE 1. Simplified Boost Converter Diagram
(a) First Cycle of Operation (b) Second Cycle Of Operation
INTRODUCTION TO COMPENSATION
CONTINUOUS CONDUCTION MODE
The LM2700Q is a current-mode, PWM boost regulator. A
boost regulator steps the input voltage up to a higher output
voltage. In continuous conduction mode (when the inductor
current never reaches zero at steady state), the boost regulator operates in two cycles.
In the first cycle of operation, shown in Figure 1 (a), the transistor is closed and the diode is reverse biased. Energy is
collected in the inductor and the load current is supplied by
COUT.
The second cycle is shown in Figure 1 (b). During this cycle,
the transistor is open and the diode is forward biased. The
energy stored in the inductor is transferred to the load and
output capacitor.
The ratio of these two cycles determines the output voltage.
The output voltage is defined approximately as:
where D is the duty cycle of the switch, D and D′ will be required for design calculations.
30186105
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the feedback pin and a resistor
divider connected to the output as shown in Figure 3. The
feedback pin voltage is 1.26V, so the ratio of the feedback
resistors sets the output voltage according to the following
equation:
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FIGURE 2. (a) Inductor current. (b) Diode current.
The LM2700Q is a current mode PWM boost converter. The
signal flow of this control scheme has two feedback loops,
one that senses switch current and one that senses output
voltage.
To keep a current programmed control converter stable
above duty cycles of 50%, the inductor must meet certain criteria. The inductor, along with input and output voltage, will
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The inductor ripple current is important for a few reasons. One
reason is because the peak switch current will be the average
inductor current (input current or ILOAD/D') plus ΔiL. As a side
note, discontinuous operation occurs when the inductor current falls to zero during a switching cycle, or ΔiL is greater than
the average inductor current. Therefore, continuous conduction mode occurs when ΔiL is less than the average inductor
current. Care must be taken to make sure that the switch will
not reach its current limit during normal operation. The inductor must also be sized accordingly. It should have a saturation
current rating higher than the peak inductor current expected.
The output voltage ripple is also affected by the total ripple
current.
The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output current.
The typical current waveform for the diode in continuous conduction mode is shown in Figure 2 (b). The diode must be
rated for a reverse voltage equal to or greater than the output
voltage used. The average current rating must be greater than
the maximum load current expected, and the peak current
rating must be greater than the peak inductor current. During
short circuit testing, or if short circuit conditions are possible
in the application, the diode current rating must exceed the
switch current limit. Using Schottky diodes with lower forward
voltage drop will decrease power dissipation and increase efficiency.
where RO is the output impedance of the error amplifier, approximately 850kΩ. For most applications, performance can
be optimized by choosing values within the range 5kΩ ≤ RC
≤ 20kΩ (RC can be up to 200kΩ if CC2 is used, see High Output Capacitor ESR Compensation) and 680pF ≤ CC ≤ 4.7nF.
Refer to the Applications Information section for recommended values for specific circuits and conditions. Refer to the
Compensation section for other design requirement.
DC GAIN AND OPEN-LOOP GAIN
Since the control stage of the converter forms a complete
feedback loop with the power components, it forms a closedloop system that must be stabilized to avoid positive feedback
and instability. A value for open-loop DC gain will be required,
from which you can calculate, or place, poles and zeros to
determine the crossover frequency and the phase margin. A
high phase margin (greater than 45°) is desired for the best
stability and transient response. For the purpose of stabilizing
the LM2700Q, choosing a crossover point well below where
the right half plane zero is located will ensure sufficient phase
margin. A discussion of the right half plane zero and checking
the crossover using the DC gain will follow.
COMPENSATION
This section will present a general design procedure to help
insure a stable and operational circuit. The designs in this
datasheet are optimized for particular requirements. If different conversions are required, some of the components may
need to be changed to ensure stability. Below is a set of general guidelines in designing a stable circuit for continuous
conduction operation (loads greater than approximately 100mA), in most all cases this will provide for stability during
discontinuous operation as well. The power components and
their effects will be determined first, then the compensation
components will be chosen to produce stability.
INDUCTOR AND DIODE SELECTION
Although the inductor sizes mentioned earlier are fine for most
applications, a more exact value can be calculated. To ensure
stability at duty cycles above 50%, the inductor must have
some minimum value determined by the minimum input voltage and the maximum output voltage. This equation is:
INPUT AND OUTPUT CAPACITOR SELECTION
The switching action of a boost regulator causes a triangular
voltage waveform at the input. A capacitor is required to reduce the input ripple and noise for proper operation of the
regulator. The size used is dependant on the application and
board layout. If the regulator will be loaded uniformly, with
very little load changes, and at lower current outputs, the input
capacitor size can often be reduced. The size can also be
reduced if the input of the regulator is very close to the source
output. The size will generally need to be larger for applications where the regulator is supplying nearly the maximum
rated output or if large load steps are expected. A minimum
value of 10µF should be used for the less stressful condtions
while a 33µF or 47µF capacitor may be required for higher
power and dynamic loads. Larger values and/or lower ESR
may be needed if the application requires very low ripple on
the input source voltage.
The choice of output capacitors is also somewhat arbitrary
and depends on the design requirements for output voltage
where fs is the switching frequency, D is the duty cycle, and
RDSON is the ON resistance of the internal switch taken from
the graph "RDSON vs. VIN" in the Typical Performance Characteristics section. This equation is only good for duty cycles
greater than 50% (D>0.5), for duty cycles less than 50% the
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LM2700Q
recommended values may be used. The corresponding inductor current ripple as shown in Figure 2 (a) is given by:
determine the slope of the current through the inductor (see
Figure 2 (a)). If the slope of the inductor current is too great,
the circuit will be unstable above duty cycles of 50%. A 4.7µH
inductor is recommended for most 600 kHz applications,
while a 2.2µH inductor may be used for most 1.25 MHz applications. If the duty cycle is approaching the maximum of
85%, it may be necessary to increase the inductance by as
much as 2X. See Inductor and Diode Selection for more detailed inductor sizing.
The LM2700Q provides a compensation pin (VC) to customize
the voltage loop feedback. It is recommended that a series
combination of RC and CC be used for the compensation network, as shown in Figure 3. For any given application, there
exists a unique combination of RC and CC that will optimize
the performance of the LM2700Q circuit in terms of its transient response. The series combination of RC and CC introduces a pole-zero pair according to the following equations:
LM2700Q
and then set the zero fZC to a point approximately in the middle. The frequency of this zero is determined by:
ripple. It is recommended that low ESR (Equivalent Series
Resistance, denoted RESR) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR
capacitors may be used but will require more compensation
which will be explained later on in the section. The ESR is also
important because it determines the peak to peak output voltage ripple according to the approximate equation:
Now RC can be chosen with the selected value for CC. Check
to make sure that the pole fPC is still in the 10Hz to 500Hz
range, change each value slightly if needed to ensure both
component values are in the recommended range. After
checking the design at the end of this section, these values
can be changed a little more to optimize performance if desired. This is best done in the lab on a bench, checking the
load step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of
RC should be chosen. This will improve the overall bandwidth
which makes the regulator respond more quickly to transients. If more detail is required, or the most optimal performance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.
ΔVOUT ≊ 2ΔiLRESR (in Volts)
A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output capacitor
you can determine a pole-zero pair introduced into the control
loop by the following equations:
Where RL is the minimum load resistance corresponding to
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the High
Output Capacitor ESR Compensation section.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just
to improve the overall phase margin of the control loop, another pole may be introduced to cancel the zero created by
the ESR. This is accomplished by adding another capacitor,
CC2, directly from the compensation pin VC to ground, in parallel with the series combination of RC and CC. The pole
should be placed at the same frequency as fZ1, the ESR zero.
The equation for this pole follows:
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90° in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
loop should be designed to have a bandwidth of less than ½
the frequency of the RHP zero. This zero occurs at a frequency of:
To ensure this equation is valid, and that CC2 can be used
without negatively impacting the effects of RC and CC, fPC2
must be greater than 10fZC.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP zero. This is
done by calculating the open-loop DC gain, ADC. After this
value is known, you can calculate the crossover visually by
placing a −20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is less than ½ the RHP zero, the phase
margin should be high enough for stability. The phase margin
can also be improved by adding CC2 as discussed earlier in
the section. The equation for ADC is given below with additional equations required for the calculation:
where ILOAD is the maximum load current.
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components RC
and CC is to set a dominant low frequency pole in the control
loop. Simply choose values for RC and CC within the ranges
given in the Introduction to Compensation section to set this
pole in the area of 10Hz to 500Hz. The frequency of the pole
created is determined by the equation:
where RO is the output impedance of the error amplifier, approximately 850kΩ. Since RC is generally much less than
RO, it does not have much effect on the above equation and
can be neglected until a value is chosen to set the zero fZC.
fZC is created to cancel out the pole created by the output
capacitor, fP1. The output capacitor pole will shift with different
load currents as shown by the equation, so setting the zero is
not exact. Determine the range of fP1 over the expected loads
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mc ≊ 0.072fs (in V/s)
where RL is the minimum load resistance, VIN is the minimum
input voltage, gm is the error amplifier transconductance
found in the Electrical Characteristics table, and RDSON is the
value chosen from the graph "RDSON vs. VIN " in the Typical
Performance Characteristics section.
LAYOUT CONSIDERATIONS
The LM2700Q uses two separate ground connections, PGND
for the driver and NMOS power device and AGND for the
sensitive analog control circuitry. The AGND and PGND pins
should be tied directly together at the package. The feedback
and compensation networks should be connected directly to
a dedicated analog ground plane and this ground plane must
Application Information
30186131
FIGURE 3. 600 kHz operation, 8V output
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LM2700Q
connect to the AGND pin. If no analog ground plane is available then the ground connections of the feedback and compensation networks must tie directly to the AGND pin.
Connecting these networks to the PGND can inject noise into
the system and effect performance.
The input bypass capacitor CIN, as shown in Figure 3, must
be placed close to the IC. This will reduce copper trace resistance which effects input voltage ripple of the IC. For
additional input voltage filtering, a 100nF bypass capacitor
can be placed in parallel with CIN, close to the VIN pin, to shunt
any high frequency noise to ground. The output capacitor,
COUT, should also be placed close to the IC. Any copper trace
connections for the COUT capacitor can increase the series
resistance, which directly effects output voltage ripple. The
feedback network, resistors RFB1 and RFB2, should be kept
close to the FB pin, and away from the inductor, to minimize
copper trace connections that can inject noise into the system. Trace connections made to the inductor and schottky
diode should be minimized to reduce power dissipation and
increase overall efficiency. For more detail on switching power supply layout considerations see Application Note
AN-1149: Layout Guidelines for Switching Power Supplies.
LM2700Q
30186130
FIGURE 4. 1.25 MHz operation, 8V output
30186132
FIGURE 5. 600 kHz operation, 5V output
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LM2700Q
30186152
VIN = 3.3V, IOUT = 200mA~> 700mA ~>200mA
CH1: IOUT 0.5A/div DC Coupled
CH2: VOUT 500mV/div AC Coupled
CH3: Inductor Current 1A/div DC Coupled
20µs/div
Load Transient for Figure 5
30186133
FIGURE 6. 600 kHz operation, 12V output
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LM2700Q
30186151
VIN = 3.3V, IOUT = 50mA~> 350mA ~>50mA
CH1: IOUT 0.5A/div DC Coupled
CH2: VOUT 500mV/div AC Coupled
CH3: Inductor Current 1A/div DC Coupled
50µs/div
Load Transient for Figure 6
30186108
FIGURE 7. Triple Output TFT Bias (600 kHz operation)
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LM2700Q
30186149
VIN = 3.3V, IOUT = 500mA
CH1: VIN 2V/div DC Coupled
CH2: VOUT 5V/div DC Coupled
CH3: Inductor Current 500mA/div DC Coupled
1ms/div
Start Up Waveform for Figure 7
30186150
VIN = 3.3V, IOUT = 50mA~> 375mA ~>50mA
CH1: IOUT 0.2A/div DC Coupled
CH2: VOUT 2V/div AC Coupled
CH3: Inductor Current 1A/div DC Coupled
500µs/div
Load Transient for Figure 7, 8V Output
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LM2700Q
Physical Dimensions inches (millimeters) unless otherwise noted
TSSOP-14 Pin Package (MTC)
For Ordering, Refer to Ordering Information Table
NS Package Number MTC14
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LM2700Q
Notes
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LM2700Q 600kHz/1.25MHz, 2.5A, Step-up PWM DC/DC Converter
Notes
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dsp.ti.com
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logic.ti.com
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www.ti.com/security
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power.ti.com
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Microcontrollers
microcontroller.ti.com
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www.ti.com/video
RFID
www.ti-rfid.com
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www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
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