LINER LTC2345-18 Buffered octal, 16-bit, 200ksps/ch differential â±10.24v adc with 30vp-p common mode range Datasheet

LTC2358-16
Buffered Octal, 16-Bit, 200ksps/Ch
Differential ±10.24V ADC with
30VP-P Common Mode Range
DESCRIPTION
FEATURES
200ksps per Channel Throughput
nn Eight Buffered Simultaneous Sampling Channels
nn 500pA/12nA Max Input Leakage at 85°C/125°C
nn ±1LSB INL (Maximum, ±10.24V Range)
nn Guaranteed 16-Bit, No Missing Codes
nn Differential, Wide Common Mode Range Inputs
nn Per-Channel SoftSpan Input Ranges:
±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V
±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V
nn 94.2dB Single-Conversion SNR (Typical)
nn −111dB THD (Typical) at f = 2kHz
IN
nn 128dB CMRR (Typical) at f = 200Hz
IN
nn Rail-to-Rail Input Overdrive Tolerance
nn Integrated Reference and Buffer (4.096V)
nn SPI CMOS (1.8V to 5V) and LVDS Serial I/O
nn Internal Conversion Clock, No Cycle Latency
nn 219mW Power Dissipation (27mW/Ch Typical)
nn 48-Lead (7mm x 7mm) LQFP Package
The LTC®2358-16 is a 16-bit, low noise 8-channel simultaneous sampling successive approximation register (SAR)
ADC with buffered differential, wide common mode range
picoamp inputs. Operating from a 5V low voltage supply,
flexible high voltage supplies, and using the internal reference and buffer, each channel of this SoftSpanTM ADC can be
independently configured on a conversion-by-conversion
basis to accept ±10.24V, 0V to 10.24V, ±5.12V, or 0V to
5.12V signals. Individual channels may also be disabled
to increase throughput on the remaining channels.
nn
The integrated picoamp-input analog buffers, wide input
common mode range and 128dB CMRR of the LTC2358-16
allow the ADC to directly digitize a variety of signals using minimal board space and power. This input signal
flexibility, combined with ±1LSB INL, no missing codes
at 16 bits, and 94.2dB SNR, makes the LTC2358-16 an
ideal choice for many high voltage applications requiring
wide dynamic range.
The LTC2358-16 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces. Between one and eight
lanes of data output may be employed in CMOS mode,
allowing the user to optimize bus width and throughput.
APPLICATIONS
Programmable Logic Controllers
Industrial Process Control
nn Power Line Monitoring
nn Test and Measurement
nn
nn
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 7705765, 7961132, 8319673, 9197235.
TYPICAL APPLICATION
15V
0.1µF
5V
0.1µF
Integral Nonlinearity vs
Output Code and Channel
1.8V TO 5V
0.1µF
2.2µF
CMOS OR LVDS
I/O INTERFACE
0V
–10V
–5V
+10V
0V
0V
–10V
–10V
VDD
VDDLBYP
UNIPOLAR
DIFFERENTIAL INPUTS IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
S/H
MUX
16-BIT
SAR ADC
SDO7
SCKO
SCKI
SDI
CS
BUSY
CNV
S/H
S/H
VEE REFBUF
REFIN
GND
235816 TA01a
EIGHT BUFFERED
SIMULTANEOUS
SAMPLING CHANNELS
0.1µF
47µF
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
ALL CHANNELS
0.50
S/H
IN7+
IN7–
0.75
SDO0
S/H
S/H
1.00
OVDD LVDS/CMOS
PD
LTC2358-16
S/H
• • •
TRUE BIPOLAR
+10V
VCC
• • •
0V
BUFFERS
IN0+
S/H
–
IN0
INL ERROR (LSB)
+10V
ARBITRARY
FULLY
DIFFERENTIAL
+5V
0.1µF
0.25
0
–0.25
–0.50
SAMPLE
CLOCK
–0.75
–1.00
–32768
–16384
0
16384
OUTPUT CODE
32768
235816 TA01b
–15V
Rev A
Document Feedback
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1
LTC2358-16
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
ORDER INFORMATION
48
47
46
45
44
43
42
41
40
39
38
37
IN7+
IN7–
GND
VEE
GND
VDD
VDD
GND
VDDLBYP
CS
BUSY
SDI
TOP VIEW
IN6– 1
IN6+ 2
IN5– 3
IN5+ 4
IN4– 5
IN4+ 6
IN3– 7
IN3+ 8
IN2– 9
IN2+ 10
IN1– 11
IN1+ 12
36
35
34
33
32
31
30
29
28
27
26
25
SDO7
SDO–/SDO6
SDO+/SDO5
SCKO–/SDO4
SCKO+/SCKO
OVDD
GND
SCKI–/SCKI
SCKI+/SDO3
SDI–/SDO2
SDI+/SDO1
SDO0
IN0– 13
IN0+ 14
GND 15
VCC 16
VEE 17
GND 18
REFIN 19
GND 20
REFBUF 21
PD 22
LVDS/CMOS 23
CNV 24
Supply Voltage (VCC)......................–0.3V to (VEE + 40V)
Supply Voltage (VEE)................................. –17.4V to 0.3V
Supply Voltage Difference (VCC – VEE).......................40V
Supply Voltage (VDD)...................................................6V
Supply Voltage (OVDD).................................................6V
Internal Regulated Supply Bypass (VDDLBYP).... (Note 3)
Analog Input Voltage
IN0+ to IN7+,
IN0– to IN7– (Note 4).......... (VEE – 0.3V) to (VCC + 0.3V)
REFIN..................................................... –0.3V to 2.8V
REFBUF, CNV (Note 5).............. –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 5)...... –0.3V to (OVDD + 0.3V)
Digital Output Voltage (Note 5)... –0.3V to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2358C................................................. 0°C to 70°C
LTC2358I..............................................–40°C to 85°C
LTC2358H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
LX PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
TJMAX = 150°C, θJA = 53°C/W
http://www.linear.com/product/LTC2358-16#orderinfo
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2358CLX-16#PBF
LTC2358LX-16
48-Lead (7mm × 7mm) Plastic LQFP
0°C to 70°C
LTC2358ILX-16#PBF
LTC2358LX-16
48-Lead (7mm × 7mm) Plastic LQFP
–40°C to 85°C
LTC2358HLX-16#PBF
LTC2358LX-16
48-Lead (7mm × 7mm) Plastic LQFP
–40°C to 125°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
Rev A
2
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LTC2358-16
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 6)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range
(IN0+ to IN7+)
VIN–
Absolute Input Range
(IN0– to IN7–)
VIN+ – VIN– Input Differential Voltage
Range
VCM
MIN
IOVERDRIVE
Input Overdrive
Current Tolerance
IIN
Analog Input Leakage Current
RIN
Analog Input Resistance
CIN
Analog Input Capacitance
CMRR
Input Common Mode
Rejection Ratio
VIHCNV
VILCNV
IINCNV
CNV Input Current
MAX
UNITS
(Note 7)
VEE + 4
VCC – 4
V
(Note 7)
l
VEE + 4
VCC – 4
V
SoftSpan 7: ±2.5 • VREFBUF Range (Note 7)
SoftSpan 6: ±2.5 • VREFBUF/1.024 Range (Note 7)
SoftSpan 5: 0V to 2.5 • VREFBUF Range (Note 7)
SoftSpan 4: 0V to 2.5 • VREFBUF/1.024 Range (Note 7)
SoftSpan 3: ±1.25 • VREFBUF Range (Note 7)
SoftSpan 2: ±1.25 • VREFBUF/1.024 Range (Note 7)
SoftSpan 1: 0V to 1.25 • VREFBUF Range (Note 7)
l
–2.5 • VREFBUF
l –2.5 • VREFBUF/1.024
l
0
l
0
l
–1.25 • VREFBUF
l –1.25 • VREFBUF/1.024
l
0
2.5 • VREFBUF
2.5 • VREFBUF/1.024
2.5 • VREFBUF
2.5 • VREFBUF/1.024
1.25 • VREFBUF
1.25 • VREFBUF/1.024
1.25 • VREFBUF
V
V
V
V
V
V
V
Input Common Mode Voltage (Note 7)
Range
VIN+ – VIN– Input Differential Overdrive
Tolerance
TYP
l
l
VEE + 4
VCC – 4
V
(Note 8)
l
−(VCC − VEE)
(VCC − VEE)
V
VIN+ > VCC, VIN– > VCC (Note 8)
VIN+ < VEE, VIN– < VEE (Note 8)
l
l
0
C-Grade and I-Grade
H-Grade
l
l
10
5
For Each Pin
l
VIN+ = VIN− = 18VP-P 200Hz Sine
100
CNV High Level Input Voltage
l
1.3
CNV Low Level Input Voltage
l
VIN = 0V to VDD
500
12
pA
pA
nA
>1000
GΩ
3
pF
128
dB
V
–10
l
mA
mA
0.5
V
10
μA
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Resolution
l
16
Bits
No Missing Codes
l
16
Bits
Transition Noise
SoftSpans 7 and 6: ±10.24V and ±10V Ranges
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges
SoftSpans 3 and 2: ±5.12V and ±5V Ranges
SoftSpan 1: 0V to 5.12V Range
INL
Integral Linearity Error
SoftSpans 7 and 6: ±10.24V and ±10V Ranges (Note 10)
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges (Note 10)
SoftSpans 3 and 2: ±5.12V and ±5V Ranges (Note 10)
SoftSpan 1: 0V to 5.12V Range (Note 10)
DNL
ZSE
0.35
0.7
0.5
1.1
LSBRMS
LSBRMS
LSBRMS
LSBRMS
l
l
l
l
–1
–1.25
–1
–1.5
±0.3
±0.4
±0.4
±0.5
1
1.25
1
1.5
LSB
LSB
LSB
LSB
Differential Linearity Error (Note 11)
l
–0.9
±0.1
0.9
LSB
Zero-Scale Error
(Note 12)
l
–700
±160
700
μV
Full-Scale Error
VREFBUF = 4.096V (REFBUF Overdriven) (Note 12)
l
−0.1
±0.025
Full-Scale Error Drift
VREFBUF = 4.096V (REFBUF Overdriven) (Note 12)
Zero-Scale Error Drift
FSE
TYP
±4
±2.5
μV/°C
0.1
%FS
ppm/°C
Rev A
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3
LTC2358-16
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 9, 13)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
SINAD
Signal-to-(Noise +
Distortion) Ratio
l
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz l
l
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
l
SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz
91.5
86.7
88.8
83.5
94.1
89.6
91.6
86.5
dB
dB
dB
dB
SNR
Signal-to-Noise Ratio
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz
l
l
l
l
91.7
86.8
88.9
83.6
94.2
89.7
91.6
86.5
dB
dB
dB
dB
THD
Total Harmonic Distortion
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz
l
l
l
l
SFDR
Spurious Free Dynamic
Range
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz
l
l
l
l
Channel-to-Channel
Crosstalk
One Channel Converting 18VP-P 200Hz Sine in ±10.24V Range,
Crosstalk to All Other Channels
–111
–107
–113
–113
101
99
102
102
–3dB Input Bandwidth
Aperture Delay
Aperture Delay Matching
–101
–99
–101
–100
Full-Scale Step, 0.005% Settling
UNITS
dB
dB
dB
dB
113
107
113
113
dB
dB
dB
dB
−109
dB
6
MHz
1
ns
150
ps
3
Aperture Jitter
Transient Response
MAX
psRMS
420
ns
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
VREFIN
Internal Reference Output Voltage
CONDITIONS
Internal Reference Temperature Coefficient
(Note 14)
Internal Reference Line Regulation
VDD = 4.75V to 5.25V
MIN
TYP
MAX
2.043
2.048
2.053
5
20
l
0.1
Internal Reference Output Impedance
VREFIN
REFIN Voltage Range
1.25
V
ppm/°C
mV/V
20
REFIN Overdriven (Note 7)
UNITS
kΩ
2.2
V
REFERENCE BUFFER CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
VREFBUF
Reference Buffer Output Voltage
REFIN Overdriven, VREFIN = 2.048V
REFBUF Voltage Range
REFBUF Overdriven (Notes 7, 15)
REFBUF Input Impedance
VREFIN = 0V, Buffer Disabled
REFBUF Load Current
VREFBUF = 5V, 8 Channels Enabled (Notes 15, 16)
VREFBUF = 5V, Acquisition or Nap Mode (Note 15)
IREFBUF
MIN
TYP
MAX
UNITS
l
4.091
4.096
4.101
V
l
2.5
5
13
l
1.5
0.39
V
kΩ
1.9
mA
mA
Rev A
4
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LTC2358-16
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS Digital Inputs and Outputs
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Digital Input Current
CIN
Digital Input Capacitance
l 0.8 • OVDD
V
l
VIN = 0V to OVDD
l
0.2 • OVDD
V
10
μA
–10
5
pF
VOH
High Level Output Voltage
IOUT = –500μA
l OVDD – 0.2
VOL
Low Level Output Voltage
IOUT = 500μA
l
V
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–50
mA
ISINK
Output Sink Current
VOUT = OVDD
50
mA
0.2
–10
V
10
μA
LVDS Digital Inputs and Outputs
VID
Differential Input Voltage
RID
On-Chip Input Termination
Resistance
CS = 0V, VICM = 1.2V
CS = OVDD
l
200
350
600
mV
l
90
106
10
125
Ω
MΩ
1.2
2.2
V
10
μA
mV
VICM
Common-Mode Input Voltage
l
0.3
IICM
Common-Mode Input Current
VIN+ = VIN– = 0V to OVDD
l
–10
VOD
Differential Output Voltage
RL = 100Ω Differential Termination
l
275
350
425
VOCM
Common-Mode Output Voltage
RL = 100Ω Differential Termination
l
1.1
1.2
1.3
V
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
–10
10
μA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN
VCC
Supply Voltage
l
7.5
VEE
TYP
MAX
UNITS
38
V
Supply Voltage
l
–16.5
0
V
VCC − VEE Supply Voltage Difference
l
10
38
V
VDD
Supply Voltage
l
4.75
5.00
5.25
V
IVCC
Supply Current
200ksps Sample Rate, 8 Channels Enabled (Note 17)
Acquisition Mode (Note 17)
Nap Mode
Power Down Mode
l
l
l
l
4.6
8.5
2.9
6
5.3
9.8
3.3
15
mA
mA
mA
μA
IVEE
Supply Current
200ksps Sample Rate, 8 Channels Enabled (Note 17)
Acquisition Mode (Note 17)
Nap Mode
Power Down Mode
l
l
l
l
–5.5
–9.8
–3.5
–15
l
1.71
–4.5
–8
–2.8
–4
mA
mA
mA
μA
CMOS I/O Mode
OVDD
Supply Voltage
IVDD
Supply Current
200ksps Sample Rate, 8 Channels Enabled
200ksps Sample Rate, 8 Channels Enabled, VREFBUF = 5V (Note 15)
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
l
15.6
13.8
2.1
1.7
106
106
5.25
V
18
16
2.7
2.4
275
500
mA
mA
mA
mA
μA
µA
Rev A
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5
LTC2358-16
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN
IOVDD
Supply Current
200ksps Sample Rate, 8 Channels Enabled (CL = 25pF)
Acquisition or Nap Mode
Power Down Mode
l
l
l
PD
Power Dissipation
200ksps Sample Rate, 8 Channels Enabled
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
TYP
MAX
UNITS
1.7
1
1
2.6
20
20
mA
μA
μA
219
258
94
0.68
0.68
259
308
114
1.9
3
mW
mW
mW
mW
mW
5.25
V
LVDS I/O Mode
OVDD
Supply Voltage
IVDD
Supply Current
200ksps Sample Rate, 8 Channels Enabled
200ksps Sample Rate, 8 Channels Enabled, VREFBUF = 5V (Note 15)
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
l
18.4
16.8
3.7
3.4
106
106
20.7
19.2
4.5
4.1
275
500
mA
mA
mA
mA
μA
µA
IOVDD
Supply Current
200ksps Sample Rate, 8 Channels Enabled (RL = 100Ω)
Acquisition or Nap Mode (RL = 100Ω)
Power Down Mode
l
l
l
7
7
1
8.5
8.0
20
mA
mA
μA
PD
Power Dissipation
200ksps Sample Rate, 8 Channels Enabled
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
245
284
120
0.68
0.68
287
337
143
1.9
3
mW
mW
mW
mW
mW
l
2.375
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
fSMPL
Maximum Sampling Frequency
8 Channels Enabled
7 Channels Enabled
6 Channels Enabled
5 Channels Enabled
4 Channels Enabled
3 Channels Enabled
2 Channels Enabled
1 Channel Enabled
l
l
l
l
l
l
l
l
tCYC
Time Between Conversions
8 Channels Enabled, fSMPL = 200ksps
7 Channels Enabled, fSMPL = 225ksps
6 Channels Enabled, fSMPL = 250ksps
5 Channels Enabled, fSMPL = 300ksps
4 Channels Enabled, fSMPL = 350ksps
3 Channels Enabled, fSMPL = 425ksps
2 Channels Enabled, fSMPL = 550ksps
1 Channel Enabled, fSMPL = 800ksps
l
l
l
l
l
l
l
l
5000
4444
4000
3333
2855
2350
1815
1250
tCONV
Conversion Time
N Channels Enabled, 1 ≤ N ≤ 8
l
450•N
500•N
tACQ
Acquisition Time
(tACQ = tCYC – tCONV – tBUSYLH)
8 Channels Enabled, fSMPL = 200ksps
7 Channels Enabled, fSMPL = 225ksps
6 Channels Enabled, fSMPL = 250ksps
5 Channels Enabled, fSMPL = 300ksps
4 Channels Enabled, fSMPL = 350ksps
3 Channels Enabled, fSMPL = 425ksps
2 Channels Enabled, fSMPL = 550ksps
1 Channel Enabled, fSMPL = 800ksps
l
l
l
l
l
l
l
l
570
564
670
553
625
670
685
670
980
924
980
813
835
830
795
730
6
For more information www.analog.com
MIN
TYP
MAX
UNITS
200
225
250
300
350
425
550
800
ksps
ksps
ksps
ksps
ksps
ksps
ksps
ksps
ns
ns
ns
ns
ns
ns
ns
ns
550•N
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev A
LTC2358-16
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
tCNVH
tCNVL
CONDITIONS
MIN
TYP
MAX
UNITS
CNV High Time
l
40
ns
CNV Low Time
l
750
ns
tBUSYLH
CNV to BUSY Delay
tQUIET
Digital I/O Quiet Time from CNV
CL = 25pF
l
20
30
ns
tPDH
PD High Time
l
40
ns
tPDL
PD Low Time
l
40
tWAKE
REFBUF Wake-Up Time
l
CREFBUF = 47μF, CREFIN = 0.1μF
ns
ns
200
ms
CMOS I/O Mode
tSCKI
SCKI Period
(Notes 18, 19)
l
10
ns
tSCKIH
SCKI High Time
l
4
ns
tSCKIL
SCKI Low Time
tSSDISCKI
SDI Setup Time from SCKI
(Note 18)
l
4
ns
l
2
ns
tHSDISCKI
SDI Hold Time from SCKI
(Note 18)
l
1
ns
tDSDOSCKI
SDO Data Valid Delay from SCKI
CL = 25pF (Note 18)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI
CL = 25pF (Note 18)
l
1.5
tSKEW
SDO to SCKO Skew
(Note 18)
l
–1
CL = 25pF (Note 18)
l
0
tDSDOBUSYL SDO Data Valid Delay from BUSY
7.5
ns
ns
0
1
ns
ns
tEN
Bus Enable Time After CS
(Note 18)
l
15
ns
tDIS
Bus Relinquish Time After CS
(Note 18)
l
15
ns
LVDS I/O Mode
tSCKI
SCKI Period
(Note 20)
l
4
ns
tSCKIH
SCKI High Time
(Note 20)
l
1.5
ns
tSCKIL
SCKI Low Time
(Note 20)
l
1.5
ns
tSSDISCKI
SDI Setup Time from SCKI
(Notes 11, 20)
l
1.2
ns
tHSDISCKI
SDI Hold Time from SCKI
(Notes 11, 20)
l
–0.2
ns
tDSDOSCKI
SDO Data Valid Delay from SCKI
(Notes 11, 20)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI
(Notes 11, 20)
l
1
tSKEW
SDO to SCKO Skew
(Note 11)
l
–0.4
(Note 11)
l
0
tDSDOBUSYL SDO Data Valid Delay from BUSY
6
ns
0.4
ns
ns
0
ns
tEN
Bus Enable Time After CS
l
50
ns
tDIS
Bus Relinquish Time After CS
l
15
ns
Rev A
For more information www.analog.com
7
LTC2358-16
ADC TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VDDLBYP is the output of an internal voltage regulator, and should
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,
as described in the Pin Functions section. Do not connect this pin to any
external circuitry.
Note 4: When these pin voltages are taken below VEE or above VCC, they
will be clamped by internal diodes. This product can handle input currents
of up to 100mA below VEE or above VCC without latchup.
Note 5: When these pin voltages are taken below GND or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
currents of up to 100mA below ground or above VDD or OVDD without
latchup.
Note 6: –16.5V ≤ VEE ≤ 0V, 7.5V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V,
VDD = 5V, unless otherwise specified.
Note 7: Recommended operating conditions.
Note 8: Exceeding these limits on any channel may corrupt conversion
results on other channels. Driving an analog input above VCC on any
channel up to 10mA will not affect conversion results on other channels.
Driving an analog input below VEE may corrupt conversion results on other
channels. Refer to Applications Information section for further details.
Refer to Absolute Maximum Ratings section for pin voltage limits related
to device reliability.
Note 9: VCC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 200ksps,
internal reference and buffer, true bipolar input signal drive in bipolar
SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless
otherwise specified.
Note 10: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 11: Guaranteed by design, not subject to test.
Note 12: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
the offset voltage measured from –0.5LSB when the output code flickers
between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
error for these SoftSpan ranges is the worst-case deviation of the first and
last code transitions from ideal and includes the effect of offset error. For
unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage
measured from 0.5LSB when the output code flickers between 0000 0000
0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan
ranges is the worst-case deviation of the last code transition from ideal
and includes the effect of offset error.
Note 13: All specifications in dB are referred to a full-scale input in the
relevant SoftSpan input range, except for crosstalk, which is referred to
the crosstalk injection signal amplitude.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: When REFBUF is overdriven, the internal reference buffer must
be disabled by setting REFIN = 0V.
Note 16: IREFBUF varies proportionally with sample rate and the number of
active channels.
Note 17: Analog input buffer supply currents from IVCC and IVEE are
reduced outside the acquisition period. Refer to nap mode in Applications
Information section.
Note 18: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
and OVDD = 5.25V.
Note 19: A tSCKI period of 10ns minimum allows a shift clock frequency of
up to 100MHz for rising edge capture.
Note 20: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
CMOS Timings
0.8 • OVDD
tWIDTH
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
235816 F01
LVDS Timings (Differential)
+200mV
tWIDTH
–200mV
tDELAY
tDELAY
+200mV
+200mV
–200mV
–200mV
0V
0V
235816 F01b
Figure 1. Voltage Levels for Timing Specifications
Rev A
8
For more information www.analog.com
LTC2358-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.
Integral Nonlinearity
vs Output Code and Channel
1.00
Integral Nonlinearity
vs Output Code and Channel
1.00
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
ALL CHANNELS
0.75
–0.25
0
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
–32768
–1.00
–32768
0
16384
OUTPUT CODE
32768
–16384
1.00
±5.12V AND ±5V
RANGES
0
16384
OUTPUT CODE
0.25
–0.25
±10.24V AND ±10V
RANGES
–16384
0
16384
OUTPUT CODE
–0.25
–0.50
–0.75
–1.00
–32768
ARBITRARY DRIVE
IN+/IN– COMMON MODE
SWEPT –10.24V to 10.24V
–16384
0
–0.25
0
16384
OUTPUT CODE
32768
235816 G07
0V TO 10.24V AND
0V TO 10V RANGES
–0.50
–1.00
32768
0
16384
32768
49152
OUTPUT CODE
DC Histogram (Near Full-Scale)
180000
±10.24V RANGE
160000
160000
140000
140000
120000
120000
100000
80000
80000
60000
40000
40000
20000
20000
–4
–3
–2
–1
0
1
CODE
2
3
4
235816 G08
±10.24V RANGE
100000
60000
0
65536
235816 G06
COUNTS
COUNTS
INL ERROR (LSB)
TRUE BIPOLAR DRIVE (IN– = 0V)
0
0V TO 5.12V RANGE
0.25
DC Histogram (Zero-Scale)
180000
±10.24V RANGE
65536
UNIPOLAR DRIVE (IN– = 0V)
ONE CHANNEL
0.75
235816 G05
0.75
0.25
32768
49152
OUTPUT CODE
–0.75
–1.00
–32768
32768
Integral Nonlinearity
vs Output Code
0.50
1.00
0.50
0
235816 G04
1.00
16384
235816 G03
–0.75
–16384
0
Integral Nonlinearity
vs Output Code and Range
±5.12V AND ±5V
RANGES
–0.50
–0.75
–1.00
–32768
–0.2
–0.5
32768
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ONE CHANNEL
0.75
INL ERROR (LSB)
INL ERROR (LSB)
–0.50
0
16384
OUTPUT CODE
0.50
±10.24V AND ±10V
RANGES
0
–0.25
–0.1
Integral Nonlinearity
vs Output Code and Range
TRUE BIPOLAR DRIVE (IN– = 0V)
ONE CHANNEL
0.75
0.0
235816 G02
Integral Nonlinearity
vs Output Code and Range
1.00
0.1
–0.4
INL ERROR (LSB)
–16384
0.2
–0.3
235816 G01
0.25
0.3
DNL ERROR (LSB)
INL ERROR (LSB)
INL ERROR (LSB)
0
0.25
ALL RANGES
ALL CHANNELS
0.4
0.50
0.25
0.50
0.5
±10.24V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ALL CHANNELS
0.75
0.50
Differential Nonlinearity
vs Output Code and Channel
0
32759
32761
32763
CODE
32765
32767
235816 G09
Rev A
For more information www.analog.com
9
LTC2358-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.
32k Point Arbitrary Two-Tone FFT
32k Point FFT fSMPL = 200kHz,
32k Point FFT fSMPL = 200kHz,
fSMPL = 200kHz, IN+ = –7dBFS 2kHz
fIN = 2kHz
fIN = 2kHz
Sine, IN– = –7dBFS 3.1kHz Sine
–40
SNR = 94.3dB
THD = –111dB
SINAD = 94.2dB
SFDR = 113dB
–60
–80
–100
–120
–40
–40
SNR = 94.3dB
THD = –115dB
SINAD = 94.3dB
SFDR = 120dB
–60
–80
–100
–120
–80
–100
–140
–160
–160
80
–180
100
0
20
40
60
FREQUENCY (kHz)
235816 G10
32k Point FFT fSMPL = 200kHz,
fIN = 2kHz
96
±5.12V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–20
–40
–80
–100
–120
–140
–105
±2.5 • VREFBUF RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
94
SINAD
93
92
40
60
FREQUENCY (kHz)
80
100
THD, Harmonics vs VREFBUF,
fIN = 2kHz
±2.5 • VREFBUF RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–115
THD
–120
2ND
–125
–130
3RD
20
40
60
FREQUENCY (kHz)
80
100
3
3.5
4
4.5
REFBUF VOLTAGE (V)
5
100
0
–60
±10.24V RANGE
–
–70 TRUE BIPOLAR DRIVE (IN = 0V)
95
THD, HARMONICS (dBFS)
SNR
SINAD
80
75
70
65 ±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
60
10
100
1k
10k
FREQUENCY (Hz)
–80
–90
1kΩ
10kΩ
SOURCE
SOURCE
–100
–110
50Ω SOURCE
235816 G16
–130
5
THD, Harmonics vs Input
Common Mode, fIN = 2kHz
–20
–120
100k
3.5
4
4.5
REFBUF VOLTAGE (V)
235816 G15
THD vs Input Frequency
90
3
235816 G14
SNR, SINAD
vs Input Frequency
85
–135
2.5
THD, HARMONICS (dBFS)
0
91
2.5
235816 G13
SNR, SINAD (dBFS)
20
–110
SNR
–160
–180
0
235816 G12
SNR, SINAD vs VREFBUF,
fIN = 2kHz
95
SNR = 91.8dB
THD = –113dB
SINAD = 91.7dB
SFDR = 116dB
–60
–180
100
235816 G11
SNR, SINAD (dBFS)
0
80
THD, HARMONICS (dBFS)
40
60
FREQUENCY (kHz)
6.2kHz
–120
–140
20
SFDR = 118dB
SNR = 94.3dB
–60
–160
0
±10.24V RANGE
ARBITRARY DRIVE
–20
–140
–180
AMPLITUDE (dBFS)
0
±10.24V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
AMPLITUDE (dBFS)
0
±10.24V RANGE
2VP–P FULLY DIFFERENTIAL DRIVE
–40
–60
–11V ≤ VCM ≤ 11V
–80
–100
THD
–120
–140
10
100
1k
10k
FREQUENCY (Hz)
100k
235816 G17
–160
–15
3RD
–10
2ND
–5
0
5
10
INPUT COMMON MODE (V)
15
235816 G18
Rev A
10
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LTC2358-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.
140
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–90
SNR
94.4
SINAD
–95
CROSSTALK (dB)
94.6
110
100
90
0
10
100
235816 G19
96.0
SNR
94.5
94.0
SINAD
93.5
93.0
1k
10k
FREQUENCY (Hz)
100k
92.5
–105
THD
–110
2ND
–115
–125
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
0.100
0.075
FULL-SCALE ERROR (%)
ANALOG INPUT LEAKAGE CURRENT (pA)
10k
100
10
1
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
235816 G25
1k
10k
FREQUENCY (Hz)
100k
0.050
±10.24V RANGE
REFBUF OVERDRIVEN
VREFBUF = 4.096V
ALL CHANNELS
0.025
0.000
–0.025
–0.050
–0.100
–55 –35 –15
1M
INL, DNL vs Temperature
1.00
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
ALL CHANNELS
0.75
0.50
0.25
MAX INL
0
MAX DNL
–0.25
MIN DNL
–0.50
MIN INL
–1.00
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
235816 G24
Zero-Scale Error vs
Temperature and Channel
3
2
±10.24V RANGE
ALL CHANNELS
1
0
–1
–2
–0.075
0.1
–55 –35 –15
100
235816 G21
Positive Full-Scale Error vs
Temperature and Channel
IN = 0V
IN = +10V
IN = –10V
10
235816 G23
Analog Input Leakage
Current vs Temperature
16 ANALOG INPUT PIN TRACES
FOR EACH INPUT VOLTAGE
CH7
–0.75
3RD
235816 G22
1k
1M
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–120
92.0
–55 –35 –15
–115
–135
THD, Harmonics vs Temperature,
fIN = 2kHz
–100
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
–95
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
95.0
–110
235816 G20
SNR, SINAD vs Temperature,
fIN = 2kHz
95.5
CH2
–105
–130
INL, DNL ERROR (LSB)
–30
–20
–10
INPUT LEVEL (dBFS)
60
–100
–125
70
94.0
–40
CH1
–120
80
94.2
±10.24V RANGE
IN0+ = 0V
IN0– = 18VP–P SINE
ALL CHANNELS CONVERTING
–85
120
CMRR (dB)
SNR, SINAD (dBFS)
–80
±10.24V RANGE
IN+ = IN– = 18VP–P SINE
ALL CHANNELS
130
94.8
Crosstalk vs Input Frequency
and Channel
ZERO-SCALE ERROR (LSB)
95.0
CMRR vs Input Frequency
and Channel
SNR, SINAD vs Input Level,
fIN = 2kHz
5 25 45 65 85 105 125
TEMPERATURE (°C)
235816 G26
–3
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
235816 G27
Rev A
For more information www.analog.com
11
LTC2358-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.
Power-Down Current
vs Temperature
Supply Current vs Temperature
IVDD
16
POWER-DOWN CURRENT (µA)
12
10
8
IVCC
4
IOVDD
2
0
–2
IVEE
–4
150
IVDD
100
130
10
IVCC
–IVEE
1
0.1
INTERNAL REFERENCE OUTPUT (V)
OFFSET ERROR (LSB)
1.0
0.5
VCC = 38V, VEE = 0V
VCM = 4V to 34V
0
–0.5
–1.0
VCC = 21.5V, VEE = –16.5V
VCM = –12.5V to 17.5V
0
17
INPUT COMMON MODE (V)
34
2.049
OUTPUT CODE (LSB)
POWER DISSIPATION (mW)
160
140
120
WITH NAP MODE
tCNVL = 750ns
100 200 300 400 500 600 700 800
SAMPLING FREQUENCY (kHz)
235816 G34
100k
2.048
2.047
8
6
IVCC
4
2
0
IOVDD
–2
2.046
–4
–6
5 25 45 65 85 105 125
TEMPERATURE (°C)
IVEE
0
40
80
120
160
SAMPLING FREQUENCY (kHz)
Step Response
(Fine Settling)
100
24576
80
16384
8192
–8192
200
235816 G33
32768
0
IVDD
10
Step Response
(Large-Signal Settling)
N=4
180
WITH NAP MODE
14 tCNVL = 1µs
12
235816 G32
N=2
N=8
1k
10k
FREQUENCY (Hz)
Supply Current vs Sampling Rate
2.050
2.045
–55 –35 –15
N=1
220
100
235816 G30
15 UNITS
Power Dissipation vs Sampling
Rate, N-Channels Enabled
240
10
16
235816 G31
260
50
5 25 45 65 85 105 125
TEMPERATURE (°C)
2.051
±10.24V RANGE
0
VDD
Internal Reference Output
vs Temperature
1.5
80
70
SUPPLY CURRENT (mA)
2.0
100
90
235816 G29
Offset Error
vs Input Common Mode
200
VEE
100
IOVDD
235816 G28
–2.0
–17
110
80
0.01
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
IN+ = IN– = 0V
OVDD
120
60
–6
–55 –35 –15
–1.5
VCC
140
±10.24V RANGE
IN+ = 199.99987kHz SQUARE WAVE
IN– = 0V
–16384
–24576
–32768
–100 0 100 200 300 400 500 600 700 800 900
SETTLING TIME (ns)
235816 G35
DEVIATION FROM FINAL VALUE (LSB)
SUPPLY CURRENT (mA)
14
6
PSRR vs Frequency
1000
PSRR (dB)
18
60
±10.24V RANGE
IN+ = 199.99987kHz
SQUARE WAVE
IN– = 0V
40
20
0
–20
–40
–60
–80
–100
–100 0 100 200 300 400 500 600 700 800 900
SETTLING TIME (ns)
235816 G36
Rev A
12
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LTC2358-16
PIN FUNCTIONS
Pins that are the Same for All Digital I/O Modes
IN0+/IN0– to IN7+/IN7– (Pins 14/13, 12/11, 10/9, 8/7, 6/5,
4/3, 2/1, and 48/47): Positive and Negative Analog Inputs,
Channels 0 to 7. The converter simultaneously samples
and digitizes (VIN+ – VIN–) for all channels. Wide input
common mode range (VEE + 4V ≤ VCM ≤ VCC – 4V) and
high common mode rejection allow the inputs to accept
a wide variety of signal swings. Full-scale input range is
determined by the channel’s SoftSpan configuration.
GND (Pins 15, 18, 20, 30, 41, 44, 46): Ground. Solder
all GND pins to a solid ground plane.
VCC (Pin 16): Positive High Voltage Power Supply. The
range of VCC is 7.5V to 38V with respect to GND and 10V
to 38V with respect to VEE. Bypass VCC to GND close to
the pin with a 0.1μF ceramic capacitor.
VEE (Pins 17, 45): Negative High Voltage Power Supply.
The range of VEE is 0V to –16.5V with respect to GND and
–10V to –38V with respect to VCC. Connect Pins 17 and 45
together and bypass the VEE network to GND close to Pin
17 with a 0.1μF ceramic capacitor. In applications where
VEE is shorted to GND, this capacitor may be omitted.
REFIN (Pin 19): Bandgap Reference Output/Reference Buffer Input. An internal bandgap reference nominally outputs
2.048V on this pin. An internal reference buffer amplifies
VREFIN to create the converter master reference voltage
VREFBUF = 2 • VREFIN on the REFBUF pin. When using the
internal reference, bypass REFIN to GND (Pin 20) close to
the pin with a 0.1μF ceramic capacitor to filter the bandgap
output noise. If more accuracy is desired, overdrive REFIN
with an external reference in the range of 1.25V to 2.2V.
Do not load this pin when internal reference is used.
REFBUF (Pin 21): Internal Reference Buffer Output. An
internal reference buffer amplifies VREFIN to create the
converter master reference voltage VREFBUF = 2 • VREFIN
on this pin, nominally 4.096V when using the internal
bandgap reference. Bypass REFBUF to GND (Pin 20) close
to the pin with a 47μF ceramic capacitor. The internal reference buffer may be disabled by grounding its input at
REFIN. With the buffer disabled, overdrive REFBUF with
an external reference voltage in the range of 2.5V to 5V.
When using the internal reference buffer, limit the loading
of any external circuitry connected to REFBUF to less than
200µA. Using a high input impedance amplifier to buffer
VREFBUF to any external circuits is recommended.
PD (Pin 22): Power Down Input. When this pin is brought
high, the LTC2358-16 is powered down and subsequent
conversion requests are ignored. If this occurs during a
conversion, the device powers down once the conversion
completes. If this pin is brought high twice without an
intervening conversion, an internal global reset is initiated, equivalent to a power-on-reset event. Logic levels
are determined by OVDD.
LVDS/CMOS (Pin 23): I/O Mode Select. Tie this pin to OVDD
to select LVDS I/O mode, or to ground to select CMOS I/O
mode. Logic levels are determined by OVDD.
CNV (Pin 24): Conversion Start Input. A rising edge on
this pin puts the internal sample-and-holds into the hold
mode and initiates a new conversion. CNV is not gated
by CS, allowing conversions to be initiated independent
of the state of the serial I/O bus.
BUSY (Pin 38): Busy Output. The BUSY signal indicates
that a conversion is in progress. This pin transitions lowto-high at the start of each conversion and stays high until
the conversion is complete. Logic levels are determined
by OVDD.
VDDLBYP (Pin 40): Internal 2.5V Regulator Bypass Pin. The
voltage on this pin is generated via an internal regulator
operating off of VDD. This pin must be bypassed to GND
close to the pin with a 2.2μF ceramic capacitor. Do not
connect this pin to any external circuitry.
VDD (Pins 42, 43): 5V Power Supply. The range of VDD
is 4.75V to 5.25V. Connect Pins 42 and 43 together and
bypass the VDD network to GND with a shared 0.1μF
ceramic capacitor close to the pins.
Rev A
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13
LTC2358-16
PIN FUNCTIONS
CMOS I/O Mode
LVDS I/O Mode
SDO0 to SDO7 (Pins 25, 26, 27, 28, 33, 34, 35, and 36):
CMOS Serial Data Outputs, Channels 0 to 7. The most
recent conversion result along with channel configuration
information is clocked out onto the SDO pins on each rising edge of SCKI. Output data formatting is described in
the Digital Interface section. Leave unused SDO outputs
unconnected. Logic levels are determined by OVDD.
SDO0, SDO7, SDI (Pins 25, 36, and 37): CMOS Serial
Data I/O. In LVDS I/O mode, these pins are Hi-Z.
SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with
the serial I/O clock. SCKI rising edges latch serial data in
on SDI and clock serial data out on SDO0 to SDO7. For
standard SPI bus operation, capture output data at the
receiver on rising edges of SCKI. SCKI is allowed to idle
either high or low. Logic levels are determined by OVDD.
OVDD (Pin 31): I/O Interface Power Supply. In CMOS I/O
mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD
to GND (Pin 30) close to the pin with a 0.1μF ceramic
capacitor.
SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising
edges trigger transitions on SCKO that are skew-matched
to the serial output data streams on SDO0 to SDO7. The
resulting SCKO frequency is half that of SCKI. Rising and
falling edges of SCKO may be used to capture SDO data
at the receiver (FPGA) in double data rate (DDR) fashion.
For standard SPI bus operation, SCKO is not used and
should be left unconnected. SCKO is forced low at the
falling edge of BUSY. Logic levels are determined by OVDD.
SDI (Pin 37): CMOS Serial Data Input. Drive this pin with
the desired 24-bit SoftSpan configuration word (see Table
1a), latched on the rising edges of SCKI. If all channels
will be configured to operate only in SoftSpan 7, tie SDI
to OVDD. Logic levels are determined by OVDD.
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI.
Logic levels are determined by OVDD.
SDI+/SDI– (Pins 26/27): LVDS Positive and Negative Serial
Data Input. Differentially drive SDI+/SDI– with the desired
24-bit SoftSpan configuration word (see Table 1a), latched
on both the rising and falling edges of SCKI+/SCKI–. The
SDI+/SDI– input pair is internally terminated with a 100Ω
differential resistor when CS is low.
SCKI+/SCKI– (Pins 28/29): LVDS Positive and Negative
Serial Clock Input. Differentially drive SCKI+/SCKI– with
the serial I/O clock. SCKI+/SCKI– rising and falling edges
latch serial data in on SDI+/SDI– and clock serial data out
on SDO+/SDO–. Idle SCKI+/SCKI– low, including when
transitioning CS. The SCKI+/SCKI– input pair is internally
terminated with a 100Ω differential resistor when CS is low.
OVDD (Pin 31): I/O Interface Power Supply. In LVDS I/O
mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD
to GND (Pin 30) close to the pin with a 0.1μF ceramic
capacitor.
SCKO+/SCKO– (Pins 32/33): LVDS Positive and Negative
Serial Clock Output. SCKO+/SCKO– outputs a copy of the
input serial I/O clock received on SCKI+/SCKI–, skewmatched with the serial output data stream on SDO+/SDO–.
Use the rising and falling edges of SCKO+/SCKO– to capture SDO+/SDO– data at the receiver (FPGA). The SCKO+/
SCKO– output pair must be differentially terminated with
a 100Ω resistor at the receiver (FPGA).
SDO+/SDO– (Pins 34/35): LVDS Positive and Negative
Serial Data Output. The most recent conversion result
along with channel configuration information is clocked
out onto SDO+/SDO– on both rising and falling edges of
SCKI+/SCKI–, beginning with channel 0. The SDO+/SDO–
output pair must be differentially terminated with a 100Ω
resistor at the receiver (FPGA).
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low, and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI+/
SCKI–. The internal 100Ω differential termination resistors
on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled
when CS is high. Logic levels are determined by OVDD.
Rev A
14
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LTC2358-16
CONFIGURATION TABLES
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Independent Binary SoftSpan Codes SS[2:0] for Each
Channel Based on Desired Analog Input Range. Combine SoftSpan Codes to Form 24-Bit SoftSpan Configuration Word S[23:0]. Use
Serial Interface to Write SoftSpan Configuration Word to LTC2358-16, as shown in Figure 18
BINARY SoftSpan CODE
SS[2:0]
111
110
101
100
011
010
001
000
ANALOG INPUT RANGE
FULL SCALE RANGE
±2.5 • VREFBUF
±2.5 • VREFBUF/1.024
0V to 2.5 • VREFBUF
0V to 2.5 • VREFBUF/1.024
±1.25 • VREFBUF
±1.25 • VREFBUF/1.024
0V to 1.25 • VREFBUF
Channel Disabled
5 • VREFBUF
5 • VREFBUF/1.024
2.5 • VREFBUF
2.5 • VREFBUF/1.024
2.5 • VREFBUF
2.5 • VREFBUF/1.024
1.25 • VREFBUF
Channel Disabled
BINARY FORMAT OF
CONVERSION RESULT
Two’s Complement
Two’s Complement
Straight Binary
Straight Binary
Two’s Complement
Two’s Complement
Straight Binary
All Zeros
Table 1b. Reference Configuration Table. The LTC2358-16 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
Internal Reference with
Internal Buffer
VREFIN
2.048V
1.25V
(Min Value)
VREFBUF
4.096V
2.5V
External Reference with
Internal Buffer
(REFIN Pin Externally
Overdriven)
2.2V
(Max Value)
4.4V
BINARY SoftSpan CODE
SS[2:0]
ANALOG INPUT RANGE
111
±10.24V
110
±10V
101
0V to 10.24V
100
0V to 10V
011
±5.12V
010
±5V
001
0V to 5.12V
111
±6.25V
110
±6.104V
101
0V to 6.25V
100
0V to 6.104V
011
±3.125V
010
±3.052V
001
0V to 3.125V
111
±11V
110
±10.742V
101
0V to 11V
100
0V to 10.742V
011
±5.5V
010
±5.371V
001
0V to 5.5V
Rev A
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15
LTC2358-16
CONFIGURATION TABLES
Table 1b. Reference Configuration Table (Continued). The LTC2358-16 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
VREFIN
0V
VREFBUF
2.5V
(Min Value)
External Reference
Unbuffered
(REFBUF Pin
Externally Overdriven,
REFIN Pin Grounded)
0V
5V
(Max Value)
BINARY SoftSpan CODE
SS[2:0]
ANALOG INPUT RANGE
111
±6.25V
110
±6.104V
101
0V to 6.25V
100
0V to 6.104V
011
±3.125V
010
±3.052V
001
0V to 3.125V
111
±12.5V
110
±12.207V
101
0V to 12.5V
100
0V to 12.207V
011
±6.25V
010
±6.104V
001
0V to 6.25V
Rev A
16
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LTC2358-16
FUNCTIONAL BLOCK DIAGRAM
CMOS I/O Mode
BUFFERS
IN0+
IN0–
VCC
VDD
VDDLBYP
S/H
2.5V
REGULATOR
IN1+
SDO0
S/H
• • •
IN1–
OVDD
LTC2358-16
IN2+
S/H
IN3+
IN3–
S/H
IN4+
IN4–
S/H
IN5+
IN5–
S/H
16-BIT
SAR ADC
8-CHANNEL MULTIPLEXER
IN2–
SCKO
SDI
CS
S/H
20k
2.048V
REFERENCE
IN7+
IN7–
SDO7
CMOS
SERIAL
I/O
INTERFACE
SCKI
IN6+
IN6–
16 BITS
S/H
VEE
GND
REFERENCE
BUFFER
2×
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
235816 BD01
LVDS I/O Mode
BUFFERS
IN0+
IN0–
VCC
VDD
VDDLBYP
S/H
SDO+
2.5V
REGULATOR
IN1+
IN1–
OVDD
LTC2358-16
SDO–
S/H
SCKO+
IN2+
S/H
IN3+
IN3–
S/H
IN4+
IN4–
S/H
IN5+
IN5–
S/H
16-BIT
SAR ADC
8-CHANNEL MULTIPLEXER
IN2–
SDI+
SDI–
SCKI–
CS
S/H
2.048V
REFERENCE
IN7+
IN7–
SCKO–
SCKI+
IN6+
IN6–
16 BITS
LVDS
SERIAL
I/O
INTERFACE
S/H
VEE
GND
20k
REFERENCE
BUFFER
2×
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
235816 BD02
Rev A
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17
LTC2358-16
TIMING DIAGRAM
CMOS I/O Mode
CS = PD = 0
SAMPLE N
SAMPLE N + 1
CNV
CONVERT
BUSY
ACQUIRE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCKI
DON’T CARE
SDI
S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
SCKO
DON’T CARE
SDO0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
0
• • •
CONVERSION RESULT
C2 C1 C0 SS2 SS1 SS0 D15
CHANNEL ID SoftSpan
CONVERSION RESULT
CHANNEL 0
CONVERSION N
SDO7
DON’T CARE
CHANNEL 1
CONVERSION N
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
CONVERSION RESULT
0
C2 C1 C0 SS2 SS1 SS0 D15
CHANNEL ID SoftSpan
CHANNEL 7
CONVERSION N
CONVERSION RESULT
CHANNEL 0
CONVERSION N
235816 TD01
LVDS I/O Mode
CS = PD = 0
SAMPLE
N+1
SAMPLE N
CNV
(CMOS)
BUSY
(CMOS)
CONVERT
SCKI
(LVDS)
SDI
DON’T CARE
(LVDS)
• • •
ACQUIRE
1
2
3
4
5
6
7
8
• • •
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
186 187 188 189 190 191 192
• • •
S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
• • •
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
SCKO
(LVDS)
• • •
SDO
(LVDS) DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
CONVERSION RESULT
0
C2 C1 C0 SS2 SS1 SS0 D15 D14 D13 • • • 0
CHANNEL ID SoftSpan
CHANNEL 0
CONVERSION N
CHANNEL 1
CONVERSION N
C2 C1 C0 SS2 SS1 SS0 D15
CHANNEL ID SoftSpan
CHANNEL 7
CONVERSION N
CONVERSION
RESULT
CHANNEL 0
CONVERSION N
235816 TD02
Rev A
18
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LTC2358-16
APPLICATIONS INFORMATION
OVERVIEW
CONVERTER OPERATION
The LTC2358-16 is a 16-bit, low noise 8-channel simultaneous sampling successive approximation register
(SAR) ADC with buffered differential, wide common
mode range picoamp inputs. The ADC operates from a
5V low voltage supply and flexible high voltage supplies,
nominally ±15V. Using the integrated low-drift reference
and buffer (VREFBUF = 4.096V nominal), each channel of
this SoftSpan ADC can be independently configured on a
conversion-by-conversion basis to accept ±10.24V, 0V to
10.24V, ±5.12V, or 0V to 5.12V signals. The input signal
range may be expanded up to ±12.5V using an external
5V reference. Individual channels may also be disabled to
increase throughput on the remaining channels.
The LTC2358-16 operates in two phases. During the acquisition phase, the sampling capacitors in each channel’s
sample-and-hold (S/H) circuit connect to their respective
analog input buffers, which track the differential analog
input voltage (VIN+ – VIN–). A rising edge on the CNV pin
transitions all channels’ S/H circuits from track mode to
hold mode, simultaneously sampling the input signals
on all channels and initiating a conversion. During the
conversion phase, each channel’s sampling capacitors
are connected, one channel at a time, to a 16-bit charge
redistribution capacitor D/A converter (CDAC). The CDAC
is sequenced through a successive approximation algorithm, effectively comparing the sampled input voltage
with binary-weighted fractions of the channel’s SoftSpan
full-scale range (e.g., VFSR/2, VFSR/4 … VFSR/65536) using a differential comparator. At the end of this process,
the CDAC output approximates the channel’s sampled
analog input. Once all channels have been converted in
this manner, the ADC control logic prepares the 16-bit
digital output codes from each channel for serial transfer.
The integrated picoamp-input analog buffers, wide input
common mode range, and 128dB CMRR of the LTC235816 allow the ADC to directly digitize a variety of signals
using minimal board space and power. This input signal
flexibility, combined with ±1LSB INL, no missing codes
at 16 bits, and 94.2dB SNR, makes the LTC2358-16 an
ideal choice for many high voltage applications requiring
wide dynamic range.
The absolute common mode input range (VEE + 4V to
VCC – 4V) is determined by the choice of high voltage
supplies. These supplies may be biased asymmetrically
around ground and include the ability for VEE to be tied
directly to ground.
The LTC2358-16 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces, enabling it to communicate equally well with legacy microcontrollers and
modern FPGAs. In CMOS mode, applications may employ
between one and eight lanes of serial output data, allowing
the user to optimize bus width and data throughput. The
LTC2358-16 typically dissipates 219mW when converting
eight channels simultaneously at 200ksps per channel.
Optional nap and power down modes may be employed to
further reduce power consumption during inactive periods.
TRANSFER FUNCTION
The LTC2358-16 digitizes each channel’s full-scale voltage
range into 216 levels. In conjunction with the ADC master
reference voltage, VREFBUF, a channel’s SoftSpan configuration determines its input voltage range, full-scale range,
LSB size, and the binary format of its conversion result, as
shown in Tables 1a and 1b. For example, employing the
internal reference and buffer (VREFBUF = 4.096V nominal),
SoftSpan 7 configures a channel to accept a ±10.24V bipolar analog input voltage range, which corresponds to a
20.48V full-scale range with a 312.5μV LSB. Other SoftSpan
configurations and reference voltages may be employed to
convert both larger and smaller bipolar and unipolar input
ranges. Conversion results are output in two’s complement binary format for all bipolar SoftSpan ranges, and
in straight binary format for all unipolar SoftSpan ranges.
Rev A
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19
LTC2358-16
APPLICATIONS INFORMATION
OUTPUT CODE (TWO’S COMPLEMENT)
The ideal two’s complement transfer function is shown in
Figure 2, while the ideal straight binary transfer function
is shown in Figure 3.
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/65536
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
235816 F02
OUTPUT CODE (STRAIGHT BINARY)
Figure 2. LTC2358-16 Two’s Complement Transfer Function
111...111
111...110
100...001
100...000
011...111 UNIPOLAR
ZERO
011...110
000...001
FSR = +FS
1LSB = FSR/65536
000...000
0V
FSR – 1LSB
INPUT VOLTAGE (V)
235816 F03
LTC2358-16 enables it to accept a wide variety of signal
swings, including traditional classes of analog input signals
such as pseudo-differential unipolar, pseudo-differential
true bipolar, and fully differential, simplifying signal chain
design. For conversion of signals extending to VEE, the
unbuffered LTC2348-16 ADC is recommended.
The wide operating range of the high voltage supplies
offers further input common mode flexibility. As long as
the voltage difference limits of 10V ≤ (VCC – VEE) ≤ 38V
are observed, VCC and VEE may be independently biased
anywhere within their own individually allowed operating
ranges, including the ability for VEE to be tied directly to
ground. This feature enables the common mode input
range of the LTC2358-16 to be tailored to specific application requirements.
In all SoftSpan ranges, each channel’s analog inputs can
be modeled by the equivalent circuit shown in Figure 4. At
the start of acquisition, the sampling capacitors (CSAMP)
connect to the integrated buffers Buffer+/Buffer– through
the sampling switches. The sampled voltage is reset during the conversion process and is therefore re-acquired
for each new conversion.
The diodes between the inputs and the VCC and VEE supplies provide input ESD protection. While within the supply
voltages, the analog inputs of the LTC2358-16 draw only
5pA typical DC leakage current and the ESD protection
diodes don’t turn on. This offers a significant advantage
over external op amp buffers, which often have diode
protection that turns on during transients and corrupts
the voltage on any filter capacitors at their inputs.
Figure 3. LTC2358-16 Straight Binary Transfer Function
VCC
BUFFER+
BUFFERED ANALOG INPUTS
IN+
Each channel of the LTC2358-16 simultaneously samples
the voltage difference (VIN+ – VIN–) between its analog
input pins over a wide common mode input range while
attenuating unwanted signals common to both input pins
by the common-mode rejection ratio (CMRR) of the ADC.
Wide common mode input range coupled with high CMRR
allows the IN+/IN– analog inputs to swing with an arbitrary
relationship to each other, provided each pin remains
between (VEE + 4V) and (VCC – 4V). This feature of the
RSAMP
750Ω
CSAMP
30pF
VEE
VCC
IN–
BUFFER–
RSAMP
750Ω
CSAMP
30pF
BIAS
VOLTAGE
235816 F04
VEE
Figure 4. Equivalent Circuit for Differential Analog
Inputs, Single Channel Shown
Rev A
20
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LTC2358-16
APPLICATIONS INFORMATION
Bipolar SoftSpan Input Ranges
For channels configured in SoftSpan ranges 7, 6, 3,
or 2, the LTC2358-16 digitizes the differential analog
input voltage (VIN+ – VIN–) over a bipolar span of
±2.5 • VREFBUF, ±2.5 • VREFBUF/1.024, ±1.25 • VREFBUF, or
±1.25 • VREFBUF/1.024, respectively, as shown in Table 1a.
These SoftSpan ranges are useful for digitizing input signals
where IN+ and IN– swing above and below each other.
Traditional examples include fully differential input signals,
where IN+ and IN– are driven 180 degrees out-of-phase
with respect to each other centered around a common
mode voltage (VIN+ + VIN–)/2, and pseudo-differential
true bipolar input signals, where IN+ swings above and
below a ground reference level, driven on IN–. Regardless
of the chosen SoftSpan range, the wide common mode
input range and high CMRR of the IN+/IN– analog inputs
allow them to swing with an arbitrary relationship to each
other, provided each pin remains between (VCC – 4V) and
(VEE + 4V). The output data format for all bipolar SoftSpan
ranges is two’s complement.
Unipolar SoftSpan Input Ranges
For channels configured in SoftSpan ranges 5, 4, or 1, the
LTC2358-16 digitizes the differential analog input voltage
(VIN+ – VIN–) over a unipolar span of 0V to 2.5 • VREFBUF,
0V to 2.5 • VREFBUF/1.024, or 0V to 1.25 • VREFBUF, respectively, as shown in Table 1a. These SoftSpan ranges are
useful for digitizing input signals where IN+ remains above
IN–. A traditional example includes pseudo-differential
unipolar input signals, where IN+ swings above a ground
reference level, driven on IN–. Regardless of the chosen
SoftSpan range, the wide common mode input range and
high CMRR of the IN+/IN– analog inputs allow them to
swing with an arbitrary relationship to each other, provided
each pin remains between (VCC – 4V) and (VEE + 4V).
The output data format for all unipolar SoftSpan ranges
is straight binary.
INPUT DRIVE CIRCUITS
less than 10kΩ of impedance can drive the passive 3pF
analog input capacitance directly. For higher impedances
and slow-settling circuits, add a 680pF capacitor at the
pins to maintain the full DC accuracy of the LTC2358-16.
The very high input impedance of the unity gain buffers in
the LTC2358-16 greatly reduces the drive requirements of
the differential amplifier and make it possible to include
optional RC filters with kΩ impedance and arbitrarily slow
time constants for anti-aliasing or other purposes. Micropower op amps with limited drive capability are also well
suited to drive the high impedance analog inputs directly.
The LTC2358-16 features proprietary circuitry to achieve
exceptional internal crosstalk isolation between channels
(109dB typical). The PC board wiring to the analog inputs
should be short and shielded to prevent external capacitive
crosstalk between channels. The capacitance between adjacent package pins is 0.16pF. Low source resistance and/or
high source capacitance help reduce external capacitively
coupled crosstalk. Single ended input drive also enjoys
additional external crosstalk isolation because every other
input pin is grounded, or at a low impedance DC source,
and serves as a shield between channels.
INPUT OVERDRIVE TOLERANCE
Driving an analog input above VCC on any channel up to 10mA
will not affect conversion results on other channels. Approximately 70% of this overdrive current will flow out of the VCC
pin and the remaining 30% will flow out of VEE. This current
flowing out of VEE will produce heat across the VCC – VEE
voltage drop and must be taken into account for the total
Absolute Maximum power dissipation of 500mW. Driving
an analog input below VEE may corrupt conversion results
on other channels. This product can handle input currents
of up to 100mA below VEE or above VCC without latchup.
Keep in mind that driving the inputs above VCC or below
VEE may reverse the normal current flow from the external
power supplies driving these pins.
The CMOS buffer input stage offers a very high degree of
transient isolation from the sampling process. Most sensors, signal conditioning amplifiers and filter networks with
Rev A
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21
LTC2358-16
APPLICATIONS INFORMATION
Input Filtering
The true high impedance analog inputs can accommodate
a very wide range of passive or active signal conditioning
filters. The buffered ADC inputs have an analog bandwidth
of 6MHz, and impose no particular bandwidth requirement
on external filters. The external input filters can therefore be
optimized independent of the ADC to reduce signal chain
noise and interference. A common filter configuration is
the simple anti-aliasing and noise reducing RC filter with its
pole at half the sampling frequency. For example, 100kHz
with R=2.43kΩ and C=680pF as shown in Figure 5.
IN+
0V
R = 2.43k
–10V
+10V
680pF
UNIPOLAR
0V
–10V
15V
OPTIONAL
LOWPASS FILTER
TRUE BIPOLAR
+10V
0.1µF
IN0+
IN0–
VCC
LTC2358-16
IN–
VEE REFBUF
0.1µF
REFIN
47µF
0.1µF
–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY
235816 F05
Figure 5. Filtering Single-Ended Input Signals
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion.
NPO/COG and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Arbitrary and Fully Differential Analog Input Signals
The wide common mode input range and high CMRR of
the LTC2358-16 allow each channel’s IN+ and IN– pins to
swing with an arbitrary relationship to each other, provided
each pin remains between (VCC – 4V) and (VEE + 4V). This
feature of the LTC2358-16 enables it to accept a wide
variety of signal swings, simplifying signal chain design.
The two-tone test shown in Figure 6b demonstrates the
arbitrary input drive capability of the LTC2358-16. This test
simultaneously drives IN+ with a −7dBFS 2kHz single-ended
sine wave and IN− with a −7dBFS 3.1kHz single-ended sine
wave. Together, these signals sweep the analog inputs
across a wide range of common mode and differential
mode voltage combinations, similar to the more general
arbitrary input signal case. They also have a simple spectral representation. An ideal differential converter with no
common-mode sensitivity will digitize this signal as two
−7dBFS spectral tones, one at each sine wave frequency.
The FFT plot in Figure 6b demonstrates the LTC2358-16
response approaches this ideal, with 119dB of SFDR
limited by the converter's second harmonic distortion
response to the 3.1kHz sine wave on IN–.
The ability of the LTC2358-16 to accept arbitrary signal
swings over a wide input common mode range with high
CMRR can simplify application solutions. In practice,
many sensors produce a differential sensor voltage riding
on top of a large common mode signal. Figure 7a depicts
one way of using the LTC2358-16 to digitize signals of
this type. The amplifier stage provides a differential gain
of approximately 10V/V to the desired sensor signal while
the unwanted common mode signal is attenuated by the
ADC CMRR. The circuit employs the ±5V SoftSpan range of
the ADC. Figure 7b shows measured CMRR performance
of this solution, which is competitive with the best commercially available instrumentation amplifiers. Figure 7c
shows measured AC performance of this solution.
In Figure 8, another application circuit is shown which
uses two channels of the LTC2358-16 to simultaneously
sense the voltage and bidirectional current through a sense
resistor over a wide common mode range.
Rev A
22
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LTC2358-16
APPLICATIONS INFORMATION
+10V
ARBITRARY
0V
0V
–10V
–5V
TRUE BIPOLAR
+10V
15V
FULLY
DIFFERENTIAL
+5V
+10V
0V
0V
–10V
–10V
0.1µF
IN+
UNIPOLAR
VCC
IN0+
IN0–
LTC2358-16
IN–
VEE REFBUF
REFIN
47µF
0.1µF
0.1µF
–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY
235816 F06a
Figure 6a. Input Arbitrary, Fully Differential, True Bipolar, and Unipolar Signals
Arbitrary Drive
0
±10.24V RANGE
SFDR = 118dB
SNR = 94.3dB
–40
–40
–60
–80
–100
6.2kHz
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
0
20
40
60
FREQUENCY (kHz)
80
±10.24V RANGE
SNR = 94.3dB
THD = –115dB
SINAD = 94.3dB
SFDR = 120dB
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
Fully Differential Drive
0
–180
100
0
20
40
60
FREQUENCY (kHz)
80
235816 F06b
235816 F06c
Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine,
IN– = –7dBFS 3.1kHz Sine, 32k Point FFT, fSMPL = 200ksps.
Circuit Shown in Figure 6a
Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine,
VCM = 0V, 32k Point FFT, fSMPL = 200ksps. Circuit Shown in
Figure 6a
True Bipolar Drive
0
–60
–40
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
0
20
40
60
FREQUENCY (kHz)
80
0V to 10.24V RANGE
SNR = 89.9dB
THD = –114dB
SINAD = 89.8dB
SFDR = 115dB
–20
AMPLITUDE (dBFS)
–40
AMPLITUDE (dBFS)
Unipolar Drive
0
±10.24V RANGE
SNR = 94.3dB
THD = –111dB
SINAD = 94.2dB
SFDR = 113dB
–20
100
–180
100
235816 F06d
0
20
40
60
FREQUENCY (kHz)
80
100
235816 F06e
Figure 6d. IN+ = –1dBFS 2kHz True Bipolar Sine, IN– = 0V, 32k
Point FFT, fSMPL = 200ksps. Circuit Shown in Figure 6a
Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN– = 0V,
32k Point FFT, fSMPL = 200ksps. Circuit Shown in Figure 6a
Rev A
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23
LTC2358-16
APPLICATIONS INFORMATION
ARBITRARY
IN+
24V
+
–
INTERNAL HI-Z BUFFERS
ALLOW OPTIONAL
LTC2057HV kΩ PASSIVE FILTERS
31V
31V
3.65k
BUFFERED
ANALOG
INPUTS
2.49k
COMMON MODE
INPUT RANGE
549Ω
2.2nF
GAIN = 10
2.49k
0.1µF
LTC2358-16
3.65k
DIFFERENTIAL MODE
INPUT RANGE: ±500mV
0V
IN–
–
+
VCC
IN0+
IN0–
VEE REFBUF
BW = 10kHz
LTC2057HV
0.1µF
47µF
0.1µF
–7V
ONLY CHANNEL 0 SHOWN FOR CLARITY
REFIN
235816 F07a
–7V
Figure 7a. Amplify Differential Signals with Gain of 10
Over a Wide Common Mode Range with Buffered Analog Inputs
0
160
±5V RANGE
150
140
AMPLITUDE (dBFS)
CMRR (dB)
SNR = 90.5dB
THD = –111dB
SINAD = 90.4dB
SFDR = 112dB
–40
130
120
110
IN+ = IN– = 1VP–P SINE
100
90
–60
–80
–100
–120
80
–140
70
–160
60
±5V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–20
10
100
1k
FREQUENCY (Hz)
–180
10k
0
20
40
60
FREQUENCY (kHz)
80
100
235816 F07c
235816 F07b
Figure 7c. IN+/IN– = 450mV 200Hz Fully
Figure 7b. CMRR vs Input Frequency.
Circuit Shown in Figure 7a
Differential Sine, 0V ≤ VCM ≤ 24V, 32k Point FFT,
fSMPL = 200ksps. Circuit Shown in Figure 7a
15V
0.1µF
VS1
RSENSE
ISENSE
VS2
IN0+
IN0–
VCC
LTC2358-16
IN1+
–
IN1
VEE REFBUF
REFIN
0.1µF
47µF
–15V
0.1µF
235816 F08
ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY
V – VS2
ISENSE = S1
RSENSE
–10.24V ≤ VS1 ≤ 10.24V
–10.24V ≤ VS2 ≤ 10.24V
Figure 8. Simultaneously Sense Voltage (CH0) and Current (CH1) Over a Wide Common Mode Range
Rev A
24
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LTC2358-16
APPLICATIONS INFORMATION
ADC REFERENCE
LTC2358-16
REFIN
As shown previously in Table 1b, the LTC2358-16 supports
three reference configurations. The first uses both the internal bandgap reference and reference buffer. The second
externally overdrives the internal reference but retains the
internal buffer, which isolates the external reference from
ADC conversion transients. This configuration is ideal
for sharing a single precision external reference across
multiple ADCs. The third disables the internal buffer and
overdrives the REFBUF pin externally.
REFBUF
REFERENCE
BUFFER
6.5k
47µF
6.5k
GND
235816 F09a
Figure 9a. Internal Reference with Internal
Buffer Configuration
LTC2358-16
REFIN
20k
BANDGAP
REFERENCE
2.7µF
REFBUF
47µF
LTC6655-2.048
REFERENCE
BUFFER
6.5k
6.5k
GND
235816 F09b
Figure 9b. External Reference with Internal
Buffer Configuration
External Reference with Internal Buffer
If more accuracy and/or lower drift is desired, REFIN can
be easily overdriven by an external reference since 20kΩ
of resistance separates the internal bandgap reference
output from the REFIN pin, as shown in Figure 9b. The
valid range of external reference voltage overdrive on the
REFIN pin is 1.25V to 2.2V, resulting in converter master
reference voltages VREFBUF between 2.5V and 4.4V, respectively. Analog Devices, Inc. offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power, and high
accuracy, the LTC6655-2.048 is well suited for use with the
LTC2358-16 when overdriving the internal reference. The
BANDGAP
REFERENCE
0.1µF
Internal Reference with Internal Buffer
The LTC2358-16 has an on-chip, low noise, low drift
(20ppm/°C maximum), temperature compensated bandgap reference that is factory trimmed to 2.048V. The
reference output connects through a 20kΩ resistor to
the REFIN pin, which serves as the input to the on-chip
reference buffer, as shown in Figure 9a. When employing
the internal bandgap reference, the REFIN pin should be
bypassed to GND (Pin 20) close to the pin with a 0.1μF
ceramic capacitor to filter wideband noise. The reference
buffer amplifies VREFIN to create the converter master
reference voltage VREFBUF = 2 • VREFIN on the REFBUF pin,
nominally 4.096V when using the internal bandgap reference. Bypass REFBUF to GND (Pin 20) close to the pin with
at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or
X5R, 10V, 0805 size) to compensate the reference buffer,
absorb transient conversion currents, and minimize noise.
20k
LTC2358-16
REFIN
REFBUF
47µF
LTC6655-5
20k
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
6.5k
GND
235816 F09c
Figure 9c. External Reference with Disabled
Internal Buffer Configuration
Rev A
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25
LTC2358-16
APPLICATIONS INFORMATION
External Reference with Disabled Internal Buffer
The internal reference buffer supports VREFBUF = 4.4V
maximum. By grounding REFIN, the internal buffer may
be disabled allowing REFBUF to be overdriven with an
external reference voltage between 2.5V and 5V, as shown
in Figure 9c. Maximum input signal swing and SNR are
achieved by overdriving REFBUF using an external 5V
reference. The buffer feedback resistors load the REFBUF
pin with 13kΩ even when the reference buffer is disabled.
The LTC6655-5 offers the same small size, accuracy, drift,
and extended temperature range as the LTC6655-2.048,
and achieves a typical SNR of 94.8dB when paired with
the LTC2358-16. Bypass the LTC6655-5 to GND (Pin 20)
close to the REFBUF pin with at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or X5R, 10V, 0805 size) to
absorb transient conversion currents and minimize noise.
The LTC2358-16 converter draws a charge (QCONV) from
the REFBUF pin during each conversion cycle. On short
time scales most of this charge is supplied by the external
REFBUF bypass capacitor, but on longer time scales all of
the charge is supplied by either the reference buffer, or
when the internal reference buffer is disabled, the external
reference. This charge draw corresponds to a DC current
equivalent of IREFBUF = QCONV • fSMPL, which is proportional
to sample rate. In applications where a burst of samples
is taken after idling for long periods of time, as shown in
Figure 10, IREFBUF quickly transitions from approximately
0.4mA to 1.5mA (VREFBUF = 5V, fSMPL = 200kHz). This
current step triggers a transient response in the external
reference that must be considered, since any deviation in
VREFBUF affects converter accuracy. If an external reference
is used to overdrive REFBUF, the fast settling LTC6655
family of references is recommended.
Internal Reference Buffer Transient Response
For optimum performance in applications employing burst
sampling, the external reference with internal reference
buffer configuration should be used. The internal reference
buffer incorporates a proprietary design that minimizes
movements in VREFBUF when responding to a burst of
conversions following an idle period. Figure 11 compares
the burst conversion response of the LTC2358-16 with an
input near full scale for two reference configurations. The
first configuration employs the internal reference buffer
with REFIN externally overdriven by an LTC6655-2.048,
while the second configuration disables the internal reference buffer and overdrives REFBUF with an external
LTC6655-4.096. In both cases REFBUF is bypassed to
GND with a 47µF ceramic capacitor.
10.0
DEVIATION FROM FINAL VALUE (LSB)
LTC6655-2.048 offers 0.025% (maximum) initial accuracy
and 2ppm/°C (maximum) temperature coefficient for high
precision applications. The LTC6655-2.048 is fully specified over the H-grade temperature range, complementing
the extended temperature range of the LTC2358-16 up to
125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF
ceramic capacitor close to the REFIN pin is recommended.
±10.24V RANGE
IN+ = 10V
IN– = 0V
7.5
5.0
EXTERNAL REFERENCE ON REFBUF
2.5
0
INTERNAL REFERENCE BUFFER
–2.5
–5.0
0
100
200
300
TIME (µs)
400
500
235816 F11
Figure 11. Burst Conversion Response of the LTC2358-16,
fSMPL = 200ksps
CNV
IDLE
PERIOD
IDLE
PERIOD
235816 F10
Figure 10. CNV Waveform Showing Burst Sampling
Rev A
26
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LTC2358-16
APPLICATIONS INFORMATION
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion, and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2358-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies below half the sampling frequency, excluding DC. Figure 12 shows that the LTC2358-16 achieves a
typical SINAD of 94.1dB in the ±10.24V range at a 200kHz
sampling rate with a true bipolar 2kHz input signal.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 12 shows
that the LTC2358-16 achieves a typical SNR of 94.2dB in
the ±10.24V range at a 200kHz sampling rate with a true
bipolar 2kHz input signal.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD = 20 log
V22 + V32 + V42 ...VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics, respectively. Figure 12 shows
that the LTC2358-16 achieves a typical THD of –111dB
(N = 6) in the ±10.24V range at a 200kHz sampling rate
with a true bipolar 2kHz input signal.
0
±10.24V RANGE
SNR = 94.2dB
THD = –111dB
SINAD = 94.1dB
SFDR = 113dB
–20
–40
AMPLITUDE (dBFS)
DYNAMIC PERFORMANCE
–60
–80
–100
–120
–140
–160
–180
0
20
40
60
FREQUENCY (kHz)
80
100
235816 F12
Figure 12. 32k Point FFT fSMPL = 200ksps, fIN = 2kHz
POWER CONSIDERATIONS
The LTC2358-16 requires four power supplies: the positive and negative high voltage power supplies (VCC and
VEE), the 5V core power supply (VDD) and the digital input/
output (I/O) interface power supply (OVDD). As long as
the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V
are observed, VCC and VEE may be independently biased
anywhere within their own individual allowed operating
ranges, including the ability for VEE to be tied directly to
ground. This feature enables the common mode input
range of the LTC2358-16 to be tailored to the specific
application’s requirements. The flexible OVDD supply allows the LTC2358-16 to communicate with CMOS logic
operating between 1.8V and 5V, including 2.5V and 3.3V
systems. When using LVDS I/O mode, the range of OVDD
is 2.375V to 5.25V.
Power Supply Sequencing
The LTC2358-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2358-16 has
an internal power-on-reset (POR) circuit which resets the
Rev A
For more information www.analog.com
27
LTC2358-16
APPLICATIONS INFORMATION
converter on initial power-up and whenever VDD drops
below 2V. Once the supply voltage re-enters the nominal
supply voltage range, the POR reinitializes the ADC. No
conversions should be initiated until at least 10ms after
a POR event to ensure the initialization period has ended.
When employing the internal reference buffer, allow 200ms
for the buffer to power up and recharge the REFBUF bypass
capacitor. Any conversion initiated before these times will
produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2358-16 sampling and conversion is controlled
by CNV. A rising edge on CNV transitions all channels’ S/H
circuits from track mode to hold mode, simultaneously
sampling the input signals on all channels and initiating
a conversion. Once a conversion has been started, it
cannot be terminated early except by resetting the ADC,
as discussed in the Reset Timing section. For optimum
performance, drive CNV with a clean, low jitter signal and
avoid transitions on data I/O lines leading up to the rising
edge of CNV. Additionally, to minimize channel-to-channel
crosstalk, avoid high slew rates on the analog inputs for
100ns before and after the rising edge of CNV. Converter
status is indicated by the BUSY output, which transitions
low-to-high at the start of each conversion and stays high
until the conversion is complete. Once CNV is brought high
to begin a conversion, it should be returned low between
40ns and 60ns later or after the falling edge of BUSY to
minimize external disturbances during the internal conver-
sion process. The CNV timing required to take advantage
of the reduced power nap mode of operation is described
in the Nap Mode section.
Internal Conversion Clock
The LTC2358-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 550•N ns with N
channels enabled. With a minimum acquisition time of
570ns when converting eight channels simultaneously,
throughput performance of 200ksps is guaranteed without
any external adjustments. Also note that the minimum
acquisition time varies with sampling frequency (fSMPL)
and the number of enabled channels.
Nap Mode
The LTC2358-16 can be placed into nap mode after a conversion has been completed to reduce power consumption
between conversions. In this mode a portion of the device
circuitry is turned off, including circuits associated with
sampling the analog input signals. Nap mode is enabled
by keeping CNV high between conversions, as shown in
Figure 13. To initiate a new conversion after entering nap
mode, bring CNV low and hold for at least 750ns before
bringing it high again. The converter acquisition time (tACQ)
is set by the CNV low time (tCNVL) when using nap mode.
Power Down Mode
When PD is brought high, the LTC2358-16 is powered
down and subsequent conversion requests are ignored. If
this occurs during a conversion, the device powers down
once the conversion completes. In this mode, the device
t CNVL
CNV
tCONV
BUSY
NAP
NAP MODE
tACQ
235816 F13
Figure 13. Nap Mode Timing for the LTC2358-16
Rev A
28
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LTC2358-16
APPLICATIONS INFORMATION
draws only a small regulator standby current resulting in a
typical power dissipation of 0.68mW. To exit power down
mode, bring the PD pin low and wait at least 10ms before
initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
reduced, as shown in Figure 15. This decrease in average power dissipation occurs because a portion of the
LTC2358-16 circuitry is turned off during nap mode, and
the fraction of the conversion cycle (tCYC) spent napping
increases as the sampling frequency (fSMPL) is decreased.
16
WITH NAP MODE
14 tCNVL = 1µs
12
A global reset of the LTC2358-16, equivalent to a poweron-reset event, may be executed without needing to cycle
the supplies. This feature is useful when recovering from
system-level events that require the state of the entire system to be reset to a known synchronized value. To initiate
a global reset, bring PD high twice without an intervening
conversion, as shown in Figure 14. The reset event is triggered on the second rising edge of PD, and asynchronously
ends based on an internal timer. Reset clears all serial data
output registers and restores the internal SoftSpan configuration register default state of all channels in SoftSpan 7.
If reset is triggered during a conversion, the conversion
is immediately halted. The normal power down behavior
associated with PD going high is not affected by reset. Once
PD is brought low, wait at least 10ms before initiating a
conversion. When employing the internal reference buffer,
allow 200ms for the buffer to power up and recharge the
REFBUF bypass capacitor. Any conversion initiated before
these times will produce invalid results.
Power Dissipation vs Sampling Frequency
When nap mode is employed, the power dissipation of
the LTC2358-16 decreases as the sampling frequency is
SUPPLY CURRENT (mA)
Reset Timing
IVDD
10
8
6
IVCC
4
2
0
IOVDD
–2
–4
–6
IVEE
0
40
80
120
160
SAMPLING FREQUENCY (kHz)
200
235816 F15
Figure 15. Power Dissipation of the LTC2358-16
Decreases with Decreasing Sampling Frequency
DIGITAL INTERFACE
The LTC2358-16 features CMOS and LVDS serial interfaces,
selectable using the LVDS/CMOS pin. The flexible OVDD
supply allows the LTC2358-16 to communicate with any
CMOS logic operating between 1.8V and 5V, including
2.5V and 3.3V systems, while the LVDS interface supports
low noise digital designs. In CMOS mode, applications
may employ between one and eight lanes of serial data
output, allowing the user to optimize bus width and data
throughput. Together, these I/O interface options enable
the LTC2358-16 to communicate equally well with legacy
microcontrollers and modern FPGAs.
tPDH
t WAKE
PD
CNV
BUSY
RESET
tPDL
tCNVH
SECOND RISING EDGE OF
PD TRIGGERS RESET
tCONV
RESET TIME
SET INTERNALLY
235816 F14
Figure 14. Reset Timing for the LTC2358-16
Rev A
For more information www.analog.com
29
LTC2358-16
APPLICATIONS INFORMATION
CS = PD = 0
SAMPLE N
tCNVL
CNV
tCONV
BUSY
tACQ
tBUSYLH
RECOMMENDED DATA TRANSACTION WINDOW
tSCKI
tSCKIH
SCKI
SDI
SAMPLE N + 1
tCYC
tCNVH
1
S23
DON’T CARE
tDSDOBUSYL
2
3
4
5
6
7 8
tSCKIL
tSSDISCKI
tQUIET
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tHSDISCKI
S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
tHSDOSCKI
SOFTSPAN CONFIGURATION WORD FOR CONVERSION N + 1
tSKEW
SCKO
tDSDOSCKI
SDO0
DON’T CARE
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
0
CONVERSION RESULT
CONVERSION RESULT
CHANNEL 0
24-BIT PACKET
CONVERSION N
• • •
SDO7
C2 C1 C0 SS2 SS1 SS0 D15
CHANNEL ID SOFTSPAN
DON’T CARE
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
CONVERSION RESULT
CHANNEL 7
24-BIT PACKET
CONVERSION N
CHANNEL 1
24-BIT PACKET
CONVERSION N
0
C2 C1 C0 SS2 SS1 SS0 D15
CHANNEL ID SOFTSPAN
CONVERSION RESULT
CHANNEL 0
24-BIT PACKET
CONVERSION N
235816 F16
Figure 16. Serial CMOS I/O Mode
Serial CMOS I/O Mode
As shown in Figure 16, in CMOS I/O mode the serial data
bus consists of a serial clock input, SCKI, serial data
input, SDI, serial clock output, SCKO, and eight lanes of
serial data output, SDO0 to SDO7. Communication with
the LTC2358-16 across this bus occurs during predefined
data transaction windows. Within a window, the device
accepts 24-bit SoftSpan configuration words for the next
conversion on SDI and outputs 24-bit packets containing
conversion results and channel configuration information
from the previous conversion on SDO0 to SDO7. New
data transaction windows open 10ms after powering up
or resetting the LTC2358-16, and at the end of each conversion on the falling edge of BUSY. In the recommended
use case, the data transaction should be completed with
a minimum tQUIET time of 20ns prior to the start of the
next conversion, as shown in Figure 16. New SoftSpan
configuration words are only accepted within this recommended data transaction window, but SoftSpan changes
take effect immediately with no additional analog input
settling time required before starting the next conversion.
It is still possible to read conversion data after starting the
next conversion, but this will degrade conversion accuracy
and therefore is not recommended.
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SCKO is forced low and
SDO0 to SDO7 are updated with the latest conversion
results from analog input channels 0 to 7, respectively.
Rising edges on SCKI serially clock conversion results
and analog input channel configuration information out
on SDO0 to SDO7 and trigger transitions on SCKO that are
skew-matched to the data on SDO0 to SDO7. The resulting
SCKO frequency is half that of SCKI. SCKI rising edges
also latch SoftSpan configuration words provided on SDI,
Rev A
30
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LTC2358-16
APPLICATIONS INFORMATION
which are used to program the internal 24-bit SoftSpan
configuration register. See the section Programming the
SoftSpan Configuration Register in CMOS I/O Mode for
further details. SCKI is allowed to idle either high or low
in CMOS I/O mode. As shown in Figure 17, the CMOS
bus is enabled when CS is low and is disabled and Hi-Z
when CS is high, allowing the bus to be shared across
multiple devices.
The data on SDO0 to SDO7 are grouped into 24-bit packets
consisting of a 16-bit conversion result followed by two
zeros, 3-bit analog channel ID, and 3-bit SoftSpan code, all
presented MSB first. As suggested in Figures 16 and 17,
each SDO lane outputs these packets for all analog input
channels in a sequential, circular manner. For example,
the first 24-bit packet output on SDO0 corresponds to
analog input channel 0, followed by the packets for channels 1 through 7. The data output on SDO0 then wraps
back to channel 0, and this pattern repeats indefinitely.
Other SDO lanes follow a similar circular pattern, except
the first packet presented on each lane corresponds to
its associated analog input channel.
When interfacing the LTC2358-16 with a standard SPI
bus, capture output data at the receiver on rising edges of
SCKI. SCKO is not used in this case. Multiple SDO lanes
are also usually not useful in this case. In other applications, such as interfacing the LTC2358-16 with an FPGA
or CPLD, rising and falling edges of SCKO may be used
to capture serial output data on SDO0 to SDO7 in double
data rate (DDR) fashion. Capturing data using SCKO adds
robustness to delay variations over temperature and supply.
Full Eight Lane Serial CMOS Output Data Capture
As shown in Table 2, full 200ksps per channel throughput
can be achieved with a 45MHz SCKI frequency by capturing
the first packet (24 SCKI cycles total) from all eight serial
data output lanes SDO0 to SDO7. This configuration also
allows conversion results from all channels to be captured
using as few as 16 SCKI cycles if the 3-bit analog channel
ID and 3-bit SoftSpan code are not needed and the device
SoftSpan configuration is not being changed. Multi-lane
data capture is usually best suited for use with FPGA
or CPLD capture hardware, but may be useful in other
application-specific cases.
PD = 0
BUSY
CS
SCKI DON’T CARE
SDI DON’T CARE
SCKO
SDO7
NEW SoftSpan CONFIGURATION WORD
(OVERWRITES INTERNAL CONFIG REGISTER)
TWO ALL-ZERO WORDS AND ONE PARTIAL WORD
(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)
DON’T CARE
Hi-Z
Hi-Z
Hi-Z
CHANNEL 0 PACKET
CHANNEL 1 PACKET
CHANNEL 2 PACKET
CHANNEL 3 PACKET
(PARTIAL)
tEN
• • •
SDO0
DON’T CARE
Hi-Z
Hi-Z
t DIS
CHANNEL 7 PACKET
CHANNEL 0 PACKET
CHANNEL 1 PACKET
CHANNEL 2 PACKET
(PARTIAL)
Hi-Z
235816 F17
Figure 17. Internal SoftSpan Configuration Register Behavior. Serial CMOS Bus Response to CS
Rev A
For more information www.analog.com
31
LTC2358-16
APPLICATIONS INFORMATION
Fewer Than Eight Lane Serial CMOS Output Data Capture
Applications that cannot accommodate the full eight lanes
of serial data capture may employ fewer lanes without
reconfiguring the LTC2358-16. For example, capturing
the first two packets (48 SCKI cycles total) from SDO0,
SDO2, SDO4, and SDO6 provides data for analog input
channels 0 and 1, 2 and 3, 4 and 5, and 6 and 7, respectively, using four output lanes. Similarly, capturing the first
four packets (96 SCKI cycles total) from SDO0 and SDO4
provides data for analog input channels 0 to 3 and 4 to
7, respectively, using two output lanes. If only one lane
can be accommodated, capturing the first eight packets
(192 SCKI cycles total) from SDO0 provides data for all
analog input channels. As shown in Table 2, full 200ksps
per channel throughput can be achieved with a 90MHz
SCKI frequency in the four lane case, but the maximum
CMOS SCKI frequency of 100MHz limits the throughput
to less than 200ksps per channel in the two lane and one
lane cases. Finally, note that in choosing the number of
lanes and which lanes to use for data capture, the user is
not restricted to the specific cases mentioned above. Other
choices may be more optimal in particular applications.
Programming the SoftSpan Configuration Register in
CMOS I/O Mode
The internal 24-bit SoftSpan configuration register controls the SoftSpan range for all analog input channels of
the LTC2358-16. The default state of this register after
power-up or resetting the device is all ones, configuring
each channel to convert in SoftSpan 7, the ±2.5 • VREFBUF
range (see Table 1a). The state of this register may be
modified by providing a new 24-bit SoftSpan configuration
word on SDI during the data transaction window shown
in Figure 16. New SoftSpan configuration words are only
accepted within this recommended data transaction window, but SoftSpan changes take effect immediately with
no additional analog input settling time required before
starting the next conversion. Setting a channel’s SoftSpan
code to SS[2:0] = 000 immediately disables the channel,
resulting in a corresponding reduction in tCONV on the next
conversion. Similarly, enabling a previously disabled channel requires no additional analog input settling time before
starting the next conversion. The mapping between the
serial SoftSpan configuration word, the internal SoftSpan
configuration register, and each channel’s 3-bit SoftSpan
code is illustrated in Figure 18.
Table 2. Required SCKI Frequency to Achieve Various Throughputs in Common Output Bus Configurations with Eight Channels Enabled.
Shaded Entries Denote Throughputs That Are Not Achievable in a Given Configuration. Calculated Using fSCKI = (Number of SCKI
Cycles)/(t ACQ(MIN) – tQUIET )
I/O MODE
CMOS
LVDS
NUMBER OF SDO
LANES
NUMBER OF SCKI
CYCLES
8
REQUIRED fSCKI (MHz) TO ACHIEVE THROUGHPUT OF
100ksps/CHANNEL
50ksps/CHANNEL
200ksps/CHANNEL
(tACQ = 570ns)
(tACQ = 5570ns)
(tACQ = 15570ns)
16
30
3
2
8
24
45
5
2
4
48
90
9
4
2
96
Not Achievable
18
7
1
192
Not Achievable
35
13
1
96
180 (360Mbps)
18 (36Mbps)
7 (14Mbps)
Rev A
32
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
CMOS I/O MODE
tSCKIH
tSCKI
SCKI
1
SDI
DON’T CARE
2
S23
3
4
5
6
tSSDISCKI
7 8
tSCKIL
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tHSDISCKI
S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
SoftSpan CONFIGURATION WORD
LVDS I/O MODE
tSCKI
SCKI
(LVDS)
1
2
tSCKIH
3
4
5
6
7
8
9
tSCKIL
SDI
(LVDS)
DON’T CARE
S23
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tSSDISCKI
tSSDISCKI
tHSDISCKI
tHSDISCKI
S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
SoftSpan CONFIGURATION WORD
INTERNAL 24-BIT SoftSpan CONFIGURATION REGISTER
(SAME FOR CMOS AND LVDS)
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CHANNEL 7 SoftSpan CHANNEL 6 SoftSpan CHANNEL 5 SoftSpan CHANNEL 4 SoftSpan CHANNEL 3 SoftSpan CHANNEL 2 SoftSpan CHANNEL 1 SoftSpan CHANNEL 0 SoftSpan
CODE SS[2:0]
CODE SS[2:0]
CODE SS[2:0]
CODE SS[2:0]
CODE SS[2:0]
CODE SS[2:0]
CODE SS[2:0]
CODE SS[2:0]
235816 F18
Figure 18. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan
Configuration Register, and SoftSpan Code for Each Analog Input Channel
If fewer than 24 SCKI rising edges are provided during a data
transaction window, the partial word received on SDI will be
ignored and the SoftSpan configuration register will not be
updated. If exactly 24 SCKI rising edges are provided, the
SoftSpan configuration register will be updated to match
the received SoftSpan configuration word, S[23:0]. The
one exception to this behavior occurs when S[23:0] is all
zeros. In this case, the SoftSpan configuration register
will not be updated, allowing applications to retain the
current SoftSpan configuration state by idling SDI low. If
more than 24 SCKI rising edges are provided during a data
transaction window, each complete 24-bit word received
on SDI will be interpreted as a new SoftSpan configuration
word and applied to the SoftSpan configuration register
as described above. Any partial words are ignored.
Typically, applications will update the SoftSpan configuration register in the manner shown in Figures 16 and 17.
After the opening of a new data transaction window at the
falling edge of BUSY, the user supplies a 24-bit SoftSpan
configuration word on SDI during the first 24 SCKI cycles.
This new word overwrites the internal configuration register
contents following the 24th SCKI rising edge. The user then
holds SDI low for the remainder of the data transaction
window causing the register to retain its contents regardless
of the number of additional SCKI cycles applied. SoftSpan
settings may be retained across multiple conversions by
holding SDI low for the entire data transaction window,
regardless of the number of SCKI cycles applied.
Serial LVDS I/O Mode
In LVDS I/O mode, information is transmitted using positive and negative signal pairs (LVDS+/LVDS−) with bits
differentially encoded as (LVDS+ − LVDS−). These signals
are typically routed using differential transmission lines
Rev A
For more information www.analog.com
33
LTC2358-16
APPLICATIONS INFORMATION
with 100Ω characteristic impedance. Logical 1’s and 0’s
are nominally represented by differential +350mV and
−350mV, respectively. For clarity, all LVDS timing diagrams
and interface discussions adopt the logical rather than
physical convention.
version on the falling edge of BUSY. In the recommended
use case, the data transaction should be completed with
a minimum tQUIET time of 20ns prior to the start of the
next conversion, as shown in Figure 19. New SoftSpan
configuration words are only accepted within this recommended data transaction window, but SoftSpan changes
take effect immediately with no additional analog input
settling time required before starting the next conversion.
It is still possible to read conversion data after starting the
next conversion, but this will degrade conversion accuracy
and therefore is not recommended.
As shown in Figure 19, in LVDS I/O mode the serial data
bus consists of a serial clock differential input, SCKI, serial
data differential input, SDI, serial clock differential output,
SCKO, and serial data differential output, SDO. Communication with the LTC2358-16 across this bus occurs during
predefined data transaction windows. Within a window,
the device accepts 24-bit SoftSpan configuration words
for the next conversion on SDI and outputs 24-bit packets
containing conversion results and channel configuration
information from the previous conversion on SDO. New
data transaction windows open 10ms after powering up
or resetting the LTC2358-16, and at the end of each con-
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SDO is updated with the
latest conversion results from analog input channel 0. Both
rising and falling edges on SCKI serially clock conversion
results and analog input channel configuration information
out on SDO. SCKI is also echoed on SCKO, skew-matched
CS = PD = 0
SAMPLE N + 1
SAMPLE N
t CYC
tCNVH
CNV
(CMOS)
BUSY
(CMOS)
t CNVL
tCONV
t ACQ
tBUSYLH
RECOMMENDED DATA TRANSACTION WINDOW
t SCKI
SCKI
(LVDS)
SDI
(LVDS)
1
2
3
4
t SCKIL
DON’T CARE
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 185 186 187 188 189 190 191 192
t SSDISCKI
t HSDISCKI
t SSDISCKI
t HSDISCKI
S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
t DSDOBUSYL
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
t SKEW
t HSDOSCKI
SCKO
(LVDS)
SDO
(LVDS)
tQUIET
t SCKIH
t DSDOSCKI
DON’T CARE
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
CONVERSION RESULT
0
C2 C1 C0 SS2 SS1 SS0 D15 D14 D13 0
CHANNEL ID SoftSpan
CHANNEL 0
24-BIT PACKET
CONVERSION N
CHANNEL 1
24-BIT PACKET
CONVERSION N
C2 C1 C0 SS2 SS1 SS0 D15
CHANNEL ID SoftSpan
CHANNEL 7
24-BIT PACKET
CONVERSION N
CONVERSION
RESULT
CHANNEL 0
24-BIT PACKET
CONVERSION N
235816 F19
Figure 19. Serial LVDS I/O Mode
Rev A
34
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
to the data on SDO. Whenever possible, it is recommended
that rising and falling edges of SCKO be used to capture
DDR serial output data on SDO, as this will yield the best
robustness to delay variations over supply and temperature. SCKI rising and falling edges also latch SoftSpan
configuration words provided on SDI, which are used to
program the internal 24-bit SoftSpan configuration register.
See the section Programming the SoftSpan Configuration
Register in LVDS I/O Mode for further details. As shown in
Figure 20, the LVDS bus is enabled when CS is low and is
disabled and Hi-Z when CS is high, allowing the bus to be
shared across multiple devices. Due to the high speeds
involved in LVDS signaling, LVDS bus sharing must be
carefully considered. Transmission line limitations imposed
by the shared bus may limit the maximum achievable bus
clock speed. LVDS inputs are internally terminated with a
100Ω differential resistor when CS is low, while outputs
must be differentially terminated with a 100Ω resistor at
the receiver (FPGA). SCKI must idle in the low state in
LVDS I/O mode, including when transitioning CS.
The data on SDO are grouped into 24-bit packets consisting
of a 16-bit conversion result followed by two zeros, 3-bit
analog channel ID, and 3-bit SoftSpan code, all presented
MSB first. As suggested in Figures 19 and 20, SDO outputs
these packets for all analog input channels in a sequential,
circular manner. For example, the first 24-bit packet output
on SDO corresponds to analog input channel 0, followed
by the packets for channels 1 through 7. The data output
on SDO then wraps back to channel 0, and this pattern
repeats indefinitely.
PD = 0
BUSY
(CMOS)
CS
(CMOS)
tEN
tDIS
SCKI
DON’T CARE
(LVDS)
SDI
DON’T CARE
(LVDS)
SCKO
(LVDS)
SDO
(LVDS)
DON’T CARE
NEW SoftSpan CONFIGURATION WORD
(OVERWRITES INTERNAL CONFIG REGISTER)
TWO ALL-ZERO WORDS AND ONE PARTIAL WORD
(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)
DON’T CARE
Hi-Z
Hi-Z
Hi-Z
CHANNEL 0 PACKET
CHANNEL 1 PACKET
CHANNEL 2 PACKET
CHANNEL 3 PACKET
(PARTIAL)
Hi-Z
235816 F20
Figure 20. Internal SoftSpan Configuration Register Behavior. Serial LVDS Bus Response to CS
Rev A
For more information www.analog.com
35
LTC2358-16
APPLICATIONS INFORMATION
Serial LVDS Output Data Capture
As shown in Table 2, full 200ksps per channel throughput
can be achieved with a 180MHz SCKI frequency by capturing eight packets (96 SCKI cycles total) of DDR data from
SDO. The LTC2358-16 supports LVDS SCKI frequencies
up to 250MHz.
Programming the SoftSpan Configuration Register in
LVDS I/O Mode
The internal 24-bit SoftSpan configuration register controls the SoftSpan range for all analog input channels of
the LTC2358-16. The default state of this register after
power-up or resetting the device is all ones, configuring
each channel to convert in SoftSpan 7, the ±2.5 • VREFBUF
range (see Table 1a). The state of this register may be
modified by providing a new 24-bit SoftSpan configuration
word on SDI during the data transaction window shown
in Figure 19. New SoftSpan configuration words are only
accepted within this recommended data transaction window, but SoftSpan changes take effect immediately with
no additional analog input settling time required before
starting the next conversion. Setting a channel’s SoftSpan
code to SS[2:0] = 000 immediately disables the channel,
resulting in a corresponding reduction in tCONV on the next
conversion. Similarly, enabling a previously disabled channel requires no additional analog input settling time before
starting the next conversion. The mapping between the
serial SoftSpan configuration word, the internal SoftSpan
configuration register, and each channel’s 3-bit SoftSpan
code is illustrated in Figure 18.
If fewer than 24 SCKI edges (rising plus falling) are
provided during a data transaction window, the partial
word received on SDI will be ignored and the SoftSpan
configuration register will not be updated. If exactly 24
SCKI edges are provided, the SoftSpan configuration
register will be updated to match the received SoftSpan
configuration word, S[23:0]. The one exception to this
behavior occurs when S[23:0] is all zeros. In this case,
the SoftSpan configuration register will not be updated,
allowing applications to retain the current SoftSpan configuration state by idling SDI low. If more than 24 SCKI
edges are provided during a data transaction window, each
complete 24-bit word received on SDI will be interpreted
as a new SoftSpan configuration word and applied to the
SoftSpan configuration register as described above. Any
partial words are ignored.
Typically, applications will update the SoftSpan configuration register in the manner shown in Figures 19 and 20.
After the opening of a new data transaction window at
the falling edge of BUSY, the user supplies a 24-bit DDR
SoftSpan configuration word on SDI during the first 12
SCKI cycles. This new word overwrites the internal configuration register contents following the 12th SCKI falling
edge. The user then holds SDI low for the remainder of
the data transaction window causing the register to retain
its contents regardless of the number of additional SCKI
cycles applied. SoftSpan settings may be retained across
multiple conversions by holding SDI low for the entire
data transaction window, regardless of the number of
SCKI cycles applied
Rev A
36
For more information www.analog.com
LTC2358-16
BOARD LAYOUT
To obtain the best performance from the LTC2358-16, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Also minimize the length of the REFBUF to GND (Pin 20)
bypass capacitor return loop, and avoid routing CNV near
signals which could potentially disturb its rising edge.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer
to DC2365, the evaluation kit for the LTC2358-16.
Rev A
For more information www.analog.com
37
LTC2358-16
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2358-16#packaging for the most recent package drawings.
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev A)
7.15 – 7.25
9.00 BSC
5.50 REF
7.00 BSC
48
0.50 BSC
1
2
48
SEE NOTE: 4
1
2
9.00 BSC
5.50 REF
7.00 BSC
7.15 – 7.25
0.20 – 0.30
A
A
PACKAGE OUTLINE
C0.30 – 0.50
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.60
1.35 – 1.45 MAX
11° – 13°
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
11° – 13°
0.09 – 0.20
1.00 REF
0.50
BSC
0.17 – 0.27
0.05 – 0.15
0.45 – 0.75
SECTION A – A
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
XXYY
LTCXXXX
LX-ES
Q_ _ _ _ _ _
e3
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
LX48 LQFP 0113 REV A
PACKAGE IN TRAY LOADING ORIENTATION
Rev A
38
For more information www.analog.com
LTC2358-16
REVISION HISTORY
REV
DATE
DESCRIPTION
A
05/18
Updated max limits for analog input leakage
PAGE NUMBER
1, 3
Rev A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
39
LTC2358-16
TYPICAL APPLICATION
Amplify Differential Signals with Gain of 10
Over a Wide Common Mode Range with Buffered Analog Inputs
ARBITRARY
IN+
24V
+
–
31V
INTERNAL HI-Z BUFFERS
ALLOW OPTIONAL
LTC2057HV kΩ PASSIVE FILTERS
3.65k
BUFFERED
ANALOG
INPUTS
2.49k
COMMON MODE
INPUT RANGE
549Ω
2.2nF
GAIN = 10
2.49k
0.1µF
IN–
–
+
VCC
IN0+
IN0–
LTC2358-16
3.65k
DIFFERENTIAL MODE
INPUT RANGE: ±500mV
0V
31V
VEE REFBUF
LTC2057HV
BW = 10kHz
–7V
ONLY CHANNEL 0 SHOWN FOR CLARITY
0.1µF
–7V
47µF
REFIN
0.1µF
235816 TA02
RELATED PARTS
PART NUMBER
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LTC2358-18
DESCRIPTION
COMMENTS
18-Bit, 200ksps/Ch, Buffered 8-Channel
Simultaneous Sampling, ±3.5LSB INL, Serial ADC
LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous
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LTC2335-18/LTC2335-16 18-/16-Bit, 1Msps, 8-Channel Multiplexed,
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LTC2345-18/LTC2345-16 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous
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LTC2378-20/LTC2377-20/ 20-Bit, 1Msps/500ksps/250ksps,
LTC2376-20
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LTC2338-18/LTC2337-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
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LTC2328-18/LTC2327-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
LTC2326-18
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LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC
±10.24V Buffered SoftSpan Inputs with 30VP-P Common Mode Range,
96.4dB SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
±10.24V SoftSpan Inputs with Wide Common Mode Range, 97dB/94dB
SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
±10.24V SoftSpan Inputs with Wide Common Mode Range, 97dB/94dB
SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
±4.096V SoftSpan Inputs with Wide Common Mode Range, 92dB/91dB
SNR, Serial CMOS and LVDS I/O, 7mm × 7mm QFN-48 Package
2.5V Supply, ±5V Fully Differential Input, 104dB SNR, MSOP-16 and
4mm × 3mm DFN-16 Packages
5V Supply, ±10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package
5V Supply, ±10.24V Pseudo-Differential Input, 95dB SNR,
MSOP-16 Package
5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR,
DGC, 5mm × 5mm QFN-32 Package
LTC2379-18/LTC2378-18/ 18-Bit,1.6Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC, Pin
LTC2377-18/LTC2376-18 Low Power ADC
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, Pin
LTC2377-16/LTC2376-16 Low Power ADC
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2387-18/LTC2387-16 18-/16-Bit, 15Msps SAR ADC
5V Supply, Differential Input, 93.8dB SNR, 5mm × 5mm QFN Package
LTC1859/LTC1858/
16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC ±10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,
LTC1857
SSOP-28 Package
DACs
±1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm
LTC2756/LTC2757
18-Bit, Serial/Parallel IOUT SoftSpan DAC
LQFP-48 Package
LTC2668
16-Channel 16-/12-Bit ±10V VOUT SoftSpan DACs ±4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package
References
LTC6655
LT6657
Amplifiers
LTC2057/LTC2057HV
LT6020
LT1354/LT1355/LT1356
Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8
Package
Precision Low Drift Low Noise Buffered Reference 5V/3V/2.5V, 1.5ppm/°C, 0.5ppm Peak-to-Peak Noise, MSOP-8 Package
High Voltage, Low Noise Zero-Drift Op Amp
Maximum Input Offset: 4.5µV, Supply Voltage Range: 4.75V to 60V
Dual, Micropower, 5V/µs, Rail-to-Rail Op Amp
Maximum Input Offset: 30µV, Maximum Supply Current: 100µA/Amplifier
Single/Dual/Quad 1mA, 12MHz, 400V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads
Rev A
40
D16870-0-5/18(A)
For more information www.analog.com
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