MOTOROLA MCM67M618AFN12 64k x 18 bit burstram synchronous fast static ram Datasheet

MOTOROLA
Order this document
by MCM67M618A/D
SEMICONDUCTOR TECHNICAL DATA
MCM67M618A
Product Preview
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply
Fast Access Times: 9/10/12 ns Max
Byte Writeable via Dual Write Strobes
Internal Input Registers (Address, Data, Control)
Internally Self–Timed Write Cycle
TSP, TSC, and BAA Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
High Board Density 52–PLCC Package
3.3 V I/O Compatible
FN PACKAGE
PLASTIC
CASE 778–02
A6
A7
E
UW
LW
TSC
TSP
BAA
K
G
A8
A9
A10
PIN ASSIGNMENT
DQ9
DQ10
VCC
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
DQ8
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
A5
A4
A3
A2
A1
A0
VSS
VCC
A15
A14
A13
A12
A11
The MCM67M618A is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the MC68040 and PowerPC microprocessors. It is organized as 65,536
words of 18 bits, fabricated using Motorola’s high–performance silicon–gate
BiCMOS technology. The device integrates input registers, a 2–bit counter, high
speed SRAM, and high drive capability outputs onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control signals,
except output enable (G), are clock (K) controlled through positive–edge–
triggered noninverting registers.
Bursts can be initiated with either transfer start processor (TSP) or transfer
start cache controller (TSC) input pins. Subsequent burst addresses are generated internally by the MCM67M618A (burst sequence imitates that of the
MC68040) and controlled by the burst address advance (BAA) input pin. The
following pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory.
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
BAA . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
TSP, TSC . . . . . . . . . . . . . . . . Transfer Start
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be
connected for proper operation of the device.
BurstRAM is a trademark of Motorola, Inc.
PowerPC is a trademark of IBM Corp.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
5/95
 Motorola, Inc. 1994
MOTOROLA
FAST SRAM
MCM67M618A
1
BLOCK DIAGRAM (See Note)
BURST LOGIC
BAA
Q1
K
A1′
BINARY
COUNTER
TSP
D1
A1
EXTERNAL
ADDRESS
A15 – A0
16
Q0
LOAD
TSC
INTERNAL
ADDRESS
A0′
D0
A0
A15 – A2
ADDRESS
REGISTERS
18
16
WRITE
REGISTER
UW
LW
64K x 18
MEMORY
ARRAY
9
DATA–IN
REGISTERS
ENABLE
REGISTER
E
9
OUTPUT
BUFFER
9
9
G
DQ0 – DQ8
DQ9 – DQ17
9
9
NOTE: All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next
burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed
using the new external address. Alternatively, a TSP–initiated two cycle WRITE can be performed by asserting TSP and
a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on
W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After
the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is advanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state
into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST
SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE GRAPH (See Note)
0,0
A1′, A0′ =
1,1
0,1
1,0
NOTE: The external two values for A1 and A0
provide the starting point for the burst
sequence graph. The burst logic advances A1 and A0 as shown above.
MCM67M618A
2
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E
TSP
TSC
BAA
LW or UW
K
Address
Operation
H
L
X
X
X
L–H
N/A
Deselected
H
X
L
X
X
L–H
N/A
Deselected
L
L
X
X
X
L–H
External Address
Read Cycle, Begin Burst
L
H
L
X
L
L–H
External Address
Write Cycle, Begin Burst
L
H
L
X
H
L–H
External Address
Read Cycle, Begin Burst
X
H
H
L
L
L–H
Next Address
Write Cycle, Continue Burst
X
H
H
L
H
L–H
Next Address
Read Cycle, Continue Burst
X
H
H
H
L
L–H
Current Address
Write Cycle, Suspend Burst
X
H
H
H
H
L–H
Current Address
Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
G
I/O Status
Read
L
Data Out
Read
H
High–Z
Write
X
High–Z — Data In
Deselected
X
High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
± 30
mA
Power Dissipation
PD
1.6
W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to +70
°C
Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VCC
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Storage Temperature
MOTOROLA FAST SRAM
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
MCM67M618A
3
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
4.75
Input High Voltage
VIH
2.2
5.25
V
Input Low Voltage
VIL
– 0.5*
0.8
V
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (G = VIH)
Ilkg(O)
—
± 1.0
µA
AC Supply Current (G = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL or VIH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min)
ICCA9
ICCA10
ICCA12
—
275
265
250
mA
AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min)
ISB1
—
95
mA
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
VCC + 0.3**
V
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
3.3
V
NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible 68040 and PowerPC
bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance (All Pins Except DQ0 – DQ17)
Cin
—
4
5
pF
Input/Output Capacitance (DQ0 – DQ17)
CI/O
—
6
8
pF
MCM67M618A
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 3, and 4)
MCM67M618A–9
Parameter
MCM67M618A–10
MCM67M618A–12
Symbol
Min
Max
Min
Max
Min
Max
Unit
Cycle Time
tKHKH
15
—
16.6
—
20
—
ns
Clock Access Time
tKHQV
—
9
—
10
—
12
ns
Output Enable to Output Valid
tGLQV
—
5
—
5
—
6
ns
Clock High to Output Active
tKHQX1
6
—
6
—
6
—
ns
Clock High to Output Change
tKHQX2
3
—
3
—
3
—
ns
Notes
5
Output Enable to Output Active
tGLQX
0
—
0
—
0
—
ns
Output Disable to Q High–Z
tGHQZ
—
6
—
7
—
7
ns
6
Clock High to Q High–Z
tKHQZ
3
6
3
7
3
7
ns
6
Clock High Pulse Width
tKHKL
5
—
5
—
6
—
ns
Clock Low Pulse Width
tKLKH
5
—
5
—
6
—
ns
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tAVKH
tTSVKH
tDVKH
tWVKH
tBAVKH
tEVKH
2.5
—
2.5
—
2.5
—
ns
7
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHTSX
tKHDX
tKHWX
tKHBAX
tKHEX
0.5
—
0.5
—
0.5
—
ns
7
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. A read cycle is defined by UW and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP high
for the setup and hold times.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At
any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever TSP or TSC
is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when
the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled.
AC TEST LOADS
+5V
480 Ω
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
OUTPUT
255 Ω
5 pF
VL = 1.5 V
Figure 1A
MOTOROLA FAST SRAM
Figure 1B
MCM67M618A
5
MCM67M618A
6
MOTOROLA FAST SRAM
t EVKH
t AVKH
t TSVKH
t GLQX
A1
SINGLE READ
Q(A1)
t KHQV
t GLQV
t KHEX
t KHAX
t KHKL
t KHBAX
t WVKH
A2
Q(A2)
t KHQX2
t KLKH
t TSVKH
t GHQZ
t KHKH
Q(A2 + 1)
t KHQV
t BAVKH
t KHWX
t KHTSX
BURST READ
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
(BURST WRAPS AROUND
TO ITS INITIAL STATE)
(BAA SUSPENDS BURST)
NOTE: Q(A2) represents the first output data from the base address A2; Q(A2 + 1) represents the next output data in the burst sequence with A2 as the base address.
DATA OUT
G
BAA
E
LW, UW
ADDRESS
TSC
TSP
K
t KHTSX
READ CYCLES
Q(A2 + 1)
Q(A2 + 2)
t KHQZ
MOTOROLA FAST SRAM
MCM67M618A
7
Q
D
G
BAA
E
LW, UW
A
TSC
TSP
K
BURST READ
Q(An – 1)
t EVKH
t AVKH
t TSVKH
Q(An)
A1
t TSVKH
A2
t KLKH
t KHTSX
SINGLE WRITE
t GHQZ
D(A1)
t KHEX
D(A2)
BURST WRITE
D(A2 + 3)
TSC STARTS NEW BURST
D(A2 + 2)
(WITH A SUSPENDED CYCLE)
D(A2 + 1)
BAA SUSPENDS BURST
D(A2 + 1)
WRITE CYCLES
W IS IGNORED FOR FIRST CYCLE WHEN TSP INITIATES BURST
t KHAX
t KHKL
t KHTSX
t KHKH
D(A3)
t DVKH
t BAVKH
D(A3 + 1)
NEW BURST WRITE
t WVKH
A3
D(A3 + 2)
t KHDX
t KHBAX
t KHWX
COMBINATION READ/WRITE CYCLE (E low, TSC high)
tKHKH
K
tTSVKH
tKHTSX
tKHKL
tKLKH
TSP
tAVKH
ADDRESS
tKHAX
A1
A2
A3
tWVKH
tKHWX
tBAVKH
tKHBAX
LW, UW
BAA
G
tDVKH
tKHQV
DATA IN
tGLQX
tGHQZ
tKHQX2
Q(A3)
Q(A1)
READ
MCM67M618A
8
tGLQV
D(A2)
tKHQX1
DATA OUT
tKHDX
WRITE
Q(A3 + 1)
Q(A3 + 2)
BURST READ
MOTOROLA FAST SRAM
APPLICATION EXAMPLE
DATA BUS
DATA
ADDRESS BUS
ADDRESS
CLOCK
MPC604
(PowerPC)
ADDR
SYSCLK
K
CACHE
CONTROL
LOGIC
K
ADDR
DATA
G
MCM67M618AFN9
TSC
W
BAA
TSP
TS
CONTROL
512K Byte Burstable, Secondary Cache
Using Four MCM67M618AFN9s with a 66 MHz MPC604 PowerPC
MOTOROLA FAST SRAM
MCM67M618A
9
ORDERING INFORMATION
(Order by Full Part Number)
MCM
67M618A XX
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM67M618AFN9
Full Part Numbers — MCM67M618AFN9
XX
Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns)
Package (FN = PLCC)
MCM67M618AFN10
MCM67M618AFN12
MCM67M618AFN10 MCM67M618AFN12
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM67M618A
10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
B
Y BRK
-N-
0.007 (0.180)
M
T L –M
0.007 (0.180)
U
M
S
N
T L –M
S
N
S
0.010 (0.250)
S
S
D
-L-
-M-
52
LEADS
ACTUAL
Z
W
D
1
(NOTE
1)
52
G1
X
VIEW D-D
V
A
0.007 (0.180)
M
T L –M
S
N
S
R
0.007 (0.180)
M
T L –M
S
N
S
T L –M
N
S
S
Z
C
H
0.004 (0.100)
G
J
-T-
F
VIEW S
S
T L –M
S
N
S
K
SEATING
PLANE
0.007 (0.180)
M
T L –M
S
N
S
VIEW S
G1
0.010 (0.250)
M
K1
E
(NOTE
1)
52
0.007 (0.180)
T L –M
S
N
S
NOTES:
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.
2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF
LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
6. CONTROLLING DIMENSION: INCH.
7. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
R AND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
MOTOROLA FAST SRAM
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.785 0.795
0.785 0.795
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
—
0.020
—
0.025
0.750 0.756
0.750 0.756
0.042 0.048
0.042 0.048
0.042 0.056
0.020
—
10°
2°
0.710 0.730
0.040
—
MILLIMETERS
MIN
MAX
19.94 20.19
19.94 20.19
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
—
0.64
—
19.05 19.20
19.05 19.20
1.07
1.21
1.07
1.21
1.07
1.42
—
0.50
2°
10°
18.04 18.54
1.02
—
MCM67M618A
11
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MCM67M618A
12
◊
CODELINE TO BE PLACED HERE
*MCM67M618A/D*
MOTOROLAMCM67M618A/D
FAST SRAM