NTE NTE9672 Integrated circuit high threshold logic (htl) quad, 2-input nand gate Datasheet

NTE9672
Integrated Circuit
High Threshold Logic (HTL)
Quad, 2–Input NAND Gate
Description:
This NTE9672 is a Quad, 2–Input NAND gate with active output pull–up in a 14–Lead DIP style package. The active output arrangement allows the circuit to handle capacitive loads at a higher speed
than is obtainable with a passive pullup configuration. Additionally, the impedance in the high state
is considerably less, and consequently makes this device more immune to electrical noise. The active
output configuration also allows for a more powerful arrangement to interface with discrete components.
Electrical Characteristics: (TA = +25°C unless otherwise specified)
Parameter
Output Voltage
Symbol
Test Conditions
VOL
IOL = 12mA, VIH = 8.5V, VCCL = 14V
VOH
Short–Circuit Current
Reverse Current
Output Leakage Current
Forward Current
Power Drain Current
Total Device
Switching Times
Min
Typ Max Unit
–
–
1.5
V
IOH = –0.03mA, VIL = 6.5V, VCC = 15V,
VCCL = 14V
12.5
–
–
V
ISC
VCCH = 16V
–6.5
–
–15
mA
IR
VR = 16V, VCCL = 14V
–
–
2
µA
VCEX = 16V
–
–
100
µA
VF = 1.5V, VR = 16V, VCCH = 16V
–
–
–1.2
mA
VCCH = 16V
–
–
6
mA
–
–
20
mA
–
–
200
ns
–
–
100
ns
ICEX
IF
ICCL
ICCH
t1–3+
t1+3–
IOL =12mA (Pulse In),
IOH = –0.03mA (Pulse Out), VCC = 15V
Logic Symbol
1
Pin Connection Diagram
3
2
4
6
5
9
8
10
12
Input A1
1
14 VCC
Input B1
2
13 Input B4
Output Y1
3
12 Input A4
Input A2
4
11 Output Y4
Input B2
5
10 Input B3
Output Y2
6
9
Input A3
GND
7
8
Output Y3
11
13
Positive Logic: 3 = 1 D 2
Input Loading Factor = 1
Output Loading Factor = 10
Propagation Delay Time = 110ns Typ
Typical Total Power Dissipation
Input High = 176mW
Inputs Low = 52mW
14
8
1
7
.785 (19.95) Max
.300 (7.62)
.200
(5.08)
Max
.100 (2.45)
.600 (15.24)
.099 (2.5) Min
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