MPS MPQ1924HS 100v, 4a, high frequency half-bridge gate driver Datasheet

MPQ1924
100V, 4A, High Frequency
Half-Bridge Gate Driver
FEATURES
DESCRIPTION
The MPQ1924 is a high-frequency, 100V, halfbridge, N-channel, power MOSFET driver. Its
low-side and high-side driver channels are
independently controlled and matched with less
than 5ns in time delay. Under-voltage lockout
on both high-side and low-side supplies force
their outputs low in case of insufficient supply.
The integrated bootstrap diode reduces
external component count.
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



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

Drives an N-Channel MOSFET Half Bridge
118V VBST Voltage Range
On-Chip Bootstrap Diode
Typical Propagation Delay of 20ns
Gate Drive Matching of Less than 5ns
Drives a 2.2nF Load with 15ns Rise Time
and 12ns Fall Time at 12V VDD
TTL-Compatible Input
Quiescent Current of Less than 150A
UVLO for Both High Side and Low Side
SOIC-8 Package
APPLICATIONS





Motor Drivers
Telecom Half-Bridge Power Supplies
Avionics DC-DC Converters
Two-Switch Forward Converters
Active-Clamp Forward Converters
All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For
MPS green status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks
of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
12V
VDC
VDD
VDD
BST
BST
DRVH
DRVH
INH
INH
SW
M
SW
INL
INL
DRVL
DRVL
MOTOR
DRIVER
VSS
VSS
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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© 2016 MPS. All Rights Reserved.
1
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
ORDERING INFORMATION
Part Number
MPQ1924HS*
Package
SOIC-8
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MPQ1924HS–Z)
For RoHS compliant packaging, add suffix –LF (e.g. MPQ1924HS–LF–Z)
TOP MARKING
MP1924: product code of MPQ1924HS;
LLLLLLLL: lot number;
MPS: MPS prefix;
Y: year code;
WW: week code;
PACKAGE REFERENCE
SOIC-8
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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© 2016 MPS. All Rights Reserved.
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MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply Voltage (VDD)...................... -0.3V to 18V
SW Voltage (VSW) ........................ -5.0V to 105V
BST Voltage (VBST) ...................... -0.3V to 118V
BST to SW ..................................... -0.3V to 18V
DRVH to SW ............. -0.3V to (BST-SW) + 0.3V
DRVL to VSS .................. -0.3V to (VDD + 0.3V)
All Other Pins ..................... -0.3V to (VDD + 0.3V)
(2)
Continuous Power Dissipation (TA = 25°C)
SOIC-8 ......................................................1.3W
Junction Temperature .............................. 150C
Lead Temperature ................................... 260C
Storage Temperature ................. -65°C to 150C
SOIC-8 ................................... 96 ...... 45 ... C/W
Recommended Operating Conditions
(4)
θJA
θJC
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
(3)
Supply Voltage VDD ...................... 9.0V to 16.0V
SW Voltage (VSW) ........................ -1.0V to 100V
SW Slew Rate ...................................... <50V/ns
Operating Junction Temp. (TJ) ... -40C to 125C
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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© 2016 MPS. All Rights Reserved.
3
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
ELECTRICAL CHARACTERISTICS
VDD = VBST-VSW = 12V, VSS = VSW = 0V, No load at DRVH and DRVL, TA = +25C, unless otherwise
noted.
Parameter
Symbol Condition
Supply Currents
VDD quiescent current
IDDQ
INL = INH = 0
VDD operating current
IDDO
fsw = 500kHz
Floating driver quiescent current
IBSTQ
INL = INH = 0
Floating driver operating current
IBSTO
fsw = 500kHz
Leakage current
ILK
BST = SW = 100V
Inputs
INL/INH High
INL/INH Low
INL/INH
internal
pull-down
RIN
resistance
Under Voltage Protection
VDD rising threshold
VDDR
VDD hysteresis
VDDH
(BST-SW) rising threshold
VBSTR
(BST-SW) hysteresis
VBSTH
Bootstrap Diode
Bootstrap diode VF @ 100μA
VF1
Bootstrap diode VF @ 100mA
VF2
Bootstrap diode dynamic R
RD
@ 100mA
Low Side Gate Driver
Low level output voltage
VOLL
IO = 100mA
High level output voltage to rail
VOHL
IO = -100mA
VDRVL = 0V, VDD = 12V
(5)
Source Current
IOHL
VDRVL = 0V, VDD = 16V
VDRVL = VDD = 12V
(5)
Sink Current
IOLL
VDRVL = VDD = 16V
Floating Gate Driver
Low level output voltage
VOLH
IO = 100mA
High level output voltage to rail
VOHH
IO = -100mA
VDRVH = 0V, VDD = 12V
(5)
Source Current
IOHH
VDRVH = 0V, VDD = 16V
VDRVH = VDD = 12V
(5)
Sink Current
IOLH
VDRVH = VDD = 16V
Min
1
Typ
Max
Units
100
9
60
7.5
0.05
150
µA
mA
µA
mA
A
2
1.4
2.4
90
1
185
8.1
6.9
8.4
0.5
7.3
0.55
V
V
k
8.8
7.7
V
V
V
V
0.5
0.95
2
V
V

0.08
0.23
3
4.7
4.5
6
V
V
A
A
A
A
0.08
0.23
2.6
4
4.5
5.9
V
V
A
A
A
A
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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© 2016 MPS. All Rights Reserved.
4
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
ELECTRICAL CHARACTERISTICS (continued)
VDD = VBST-VSW = 12V, VSS = VSW = 0V, No load at DRVH and DRVL, TA = +25C, unless otherwise
noted.
Parameter
Symbol
Switching Spec. --- Low Side Gate Driver
Turn-off propagation delay
TDLFF
INL falling to DRVL falling
Turn-on propagation delay
TDLRR
INL rising to DRVL rising
DRVL rise time
DRVL fall time
Switching Spec. --- Floating Gate Driver
Turn-off propagation delay
TDHFF
INH falling to DRVH falling
Turn-on propagation delay
TDHRR
INH rising to DRVH rising
DRVH rise time
DRVH fall time
Switching Spec. --- Matching
Floating driver turn-off to low
TMON
(5)
side drive turn-on
Low side driver turn-off to floating
TMOFF
(5)
driver turn-on
Minimum input pulse width that
TPW
(5)
changes the output
Bootstrap diode turn-on or turnTBS
(5)
off time
Thermal shutdown
Thermal shutdown hysteresis
Condition
Min
Typ
Max
20
Units
ns
20
CL = 2.2nF
CL = 2.2nF
CL = 2.2nF
CL = 2.2nF
15
9
ns
ns
20
ns
20
ns
15
12
ns
ns
1
5
ns
1
5
ns
50
ns
10
ns
150
25
C
C
Note:
5) Guaranteed by design.
INL
INPUT
(INH, INL)
INH
TDHRR, TDLRR
TDHFF, TDLFF
OUTPUT
(DRVH,
DRVL)
DRVL
TMON
TMOFF
DRVH
Figure 1: Timing Diagram
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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© 2016 MPS. All Rights Reserved.
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MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
PIN FUNCTIONS
SOIC-8
Pin #
Name
1
VDD
2
BST
3
4
DRVH
SW
NC
5
6
INH
INL
VSS,
exposed pad
DRVL
7
8
Description
Supply input. This pin supplies power to all the internal circuitry. Place a decoupling
capacitor to ground close to this pin to ensure stable and clean supply.
Bootstrap. This is the positive power supply for the internal floating high-side
MOSFET driver. Connect a bypass capacitor between this pin and SW pin.
Floating driver output.
Switching node.
No connection.
Control signal input for the floating driver.
Control signal input for the low side driver.
Chip ground. Connect exposed pad to VSS for proper thermal operation.
Low side driver output.
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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© 2016 MPS. All Rights Reserved.
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MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS
VDD =12V, VSS = VSW = 0V, TA = +25C, unless otherwise noted.
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
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MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD =12V, VSS = VSW = 0V, TA = +25C, unless otherwise noted.
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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© 2016 MPS. All Rights Reserved.
8
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD =12V, VSS = VSW = 0V, TA = +25C, unless otherwise noted.
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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© 2016 MPS. All Rights Reserved.
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MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
BLOCK DIAGRAM
Figure 2: Function Block Diagram
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
APPLICATION
The input signals of INH and INL can be
controlled independently. If both INH and INL
control the high-side MOSFET and low-side
MOSFET of the same bridge, then users must
avoid shoot through by
setting sufficient dead time between INH and INL
low, and vice versa. See Figure 3 below. Dead
time is defined as the time interval between INH
low and INL low.
Figure 3: Shoot-Through Timing Diagram
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
REFERENCE DESIGN CIRCUITS
Half Bridge Converter
The MPQ1924 drives the MOSFETS with
alternating signals (with dead time) in half-bridge
converter topology. Therefore, from the PWM
controller drives INH and INL with alternating
signals the input voltage can go up to 100V.
Figure 4: Half Bridge Converter
Two-Switch Forward Converter
In two-switch forward converter topology, both
MOSFETs are turned on and off simultaneously.
The input signal (INH and INL) comes from a
PWM controller that senses the output voltage
(and output current during current-mode control).
The Schottky diodes clamp the reverse swing of
the power transformer and must be rated for the
input voltage. The input voltage can go up to
100V.
Figure 5: Two-Switch Forward Converter
MPQ1924 Rev. 1.0
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12/20/2016
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© 2016 MPS. All Rights Reserved.
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MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
Active-Clamp Forward Converter
In active-clamp forward converter topology, the
MPQ1924 drives the MOSFETs with alternating
signals. The high-side MOSFET, in conjunction
with Creset, is used to reset the power transformer
in a lossless manner.
This topology lends itself well to run at duty
cycles exceeding 50%. The device may not be
able to run at 100V under this topology.
Figure 6 Active-Clamp Forward Converter
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
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MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
PACKAGE OUTLINE DRAWING FOR 8-SOIC
MF-PO-D-0001, revision 3.0
PACKAGE INFORMATION
SOIC-8
0.189(4.80)
0.197(5.00)
8
0.050(1.27)
0.024(0.61)
5
0.063(1.60)
0.150(3.80)
0.157(4.00)
PIN 1 ID
1
0.228(5.80)
0.244(6.20)
0.213(5.40)
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.013(0.33)
0.020(0.51)
0.0075(0.19)
0.0098(0.25)
SEE DETAIL "A"
0.050(1.27)
BSC
SIDE VIEW
FRONT VIEW
0.010(0.25)
x 45o
0.020(0.50)
GAUGE PLANE
0.010(0.25) BSC
0o-8o
0.016(0.41)
0.050(1.27)
DETAIL "A"
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MPQ1924 Rev. 1.0
www.MonolithicPower.com
12/20/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
14