80C286/883 TM High Performance Microprocessor with Memory Management and Protection March 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The Intersil 80C286/883 is a static CMOS version of the NMOS 80286 microprocessor. The 80C286/883 is an advanced, high-performance microprocessor with specially optimized capabilities for multiple user and multi-tasking systems. The 80C286/883 has built-in memory protection that supports operating system and task isolation as well as program and data privacy within tasks. The 80C286/883 includes memory management capabilities that map 230 (one gigabyte) of virtual address space per task into 224 bytes (16 megabytes) of physical memory. • Compatible with NMOS 80286/883 • Static CMOS Design for Low Power Operation - ICCSB = 5mA Maximum - ICCOP = 185mA Maximum (80C286-10/883) - ICCOP = 220mA Maximum (80C286-12/883) • Large Address Space - 16 Megabytes Physical - 1 Gigabyte Virtual per Task • Integrated Memory Management, Four-Level Memory Protection and Support for Virtual Memory and Operating Systems • Two 80C86 Upward Compatible Operating Modes - 80C286/883 Real Address Mode - Protected Virtual Address Mode • Compatible with 80287 Numeric Data Co-Processor The 80C286/883 is upwardly compatible with 80C86 and 80C88 software (the 80C286/883 instruction set is a superset of the 80C86/80C88 instruction set). Using the 80C286/ 883 real address mode, the 80C286/883 is object code compatible with existing 80C86 and 80C88 software. In protected virtual address mode, the 80C286/883 is source code compatible with 80C86 and 80C88 software but may require upgrading to use virtual address as supported by the 80C286/883’s integrated memory management and protection mechanism. Both modes operate at full 80C286/883 performance and execute a superset of the 80C86 and 80C88 instructions. The 80C286/883 provides special operations to support the efficient implementation and execution of operating systems. For example, one instruction can end execution of one task, save its state, switch to a new task, load its state, and start execution of the new task. The segment-not-present exception and restartable instructions. Ordering Information PACKAGE 68 Pin PGA TEMP. RANGE 10MHz 0oC to +70oC - o o -40 C to +85 C IG80C286-10 12.5MHz CG80C286-12 16MHz CG80C286-16 IG80C286-12 20MHz CG80C286-20 25MHz PKG. NO. - G68.B - - - G68.B -55oC to +125oC MG80C286-10/883 MG80C286-12/883 - - - G68.B 5962-9067801MXC 5962-9067802MXC - - - G68.B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 128 FN2948.1 80C286/883 Pinout 68 LEAD PGA, COMPONENT PAD VIEW D15 ERROR D14 D7 D13 D6 D12 D5 D11 D4 D10 D3 D9 D2 D8 D1 A0 D0 VSS As viewed from underside of the component when mounted on the board. 35 37 39 41 43 45 47 49 51 38 40 42 44 46 48 50 53 52 ERROR NC 55 54 NC BUSY NC D0 34 36 32 33 NC A5 A4 26 27 61 60 PEREQ VSS A7 A6 24 25 63 62 READY VCC A8 22 23 65 64 HLDA HOLD A10 20 21 67 66 M/IO COD/INTA A13 A12 18 19 16 14 12 10 8 6 4 2 68 NC LOCK 17 15 13 11 9 7 5 3 1 PIN 1 INDICATOR BHE S0 A23 VSS NC A9 A11 S1 NMI NC 58 PEACK 59 A22 29 A21 28 A19 RESET A17 A3 A20 56 A18 57 A15 31 A16 30 INTR A12 A1 CLK A14 A2 VCC P.C. BOARD VIEW D10 D9 D8 D3 D2 D1 D0 45 43 41 39 37 35 52 53 50 48 46 44 42 40 38 36 34 D0 A0 NC 54 55 33 32 A1 A2 INTR 56 57 31 30 CLK VCC 58 59 29 28 RESET A3 A5 NC VSS D11 D4 47 BUSY D12 D5 49 ERROR D13 D6 51 NC D14 D7 D15 ERROR As viewed from the component side of the P.C. board. 65 23 22 A8 A9 COD/INTA M/IO 66 67 21 20 A10 A11 68 2 4 6 8 10 12 14 16 19 18 A12 A13 1 3 5 7 9 11 13 15 17 PIN 1 INDICATOR NC BHE LOCK A12 64 A14 HLDA A15 HOLD A16 A7 A17 A6 A18 24 A19 25 A20 63 A21 62 VSS READY A22 VCC A23 26 PEACK 27 S0 61 S1 60 A4 NC NMI PEREQ NC NC VSS 129 80C286/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied. . . . . . GND -1.0V to VCC +1.0V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 θJC Thermal Resistance (Typical) θJA PGA Package . . . . . . . . . . . . . . . . . . . . . 35oC/W 6oC/W Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22,500 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC System Clock (CLK) RISE Time (From 1.0V to 3.6V . . . . 8ns (Max) System Clock (CLK) FALL Time (from 3.6V to 1.0V) . . . . 8ns (Max) Input RISE and FALL Time (From 0.8V to 2.0V 80C286-10/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) 80C286-12/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns (Max) TABLE 1. 80C286/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER Input LOW Voltage Input HIGH Voltage CLK Input LOW Voltage CLK Input HIGH Voltage Output LOW Voltage Output HIGH Voltage SYMBOL VIL VIH V ILC VIHC VOL VOH CONDITIONS VCC = 4.5V VCC = 5.5V VCC = 4.5V VCC = 5.5V IOL = 2.0mA, VCC = 4.5V IOH = -2.0mA, VCC = 4.5V LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1, 2, 3 -55oC ≤ TA ≤ +125oC -0.5 0.8 V 1, 2, 3 -55oC ≤ TA ≤ +125oC 2.0 VCC +0.5 V 1, 2, 3 -55oC ≤ TA ≤ +125oC -0.5 1.0 V 1, 2, 3 -55 C ≤ TA ≤ +125 C 3.6 VCC +0.5 V 1, 2, 3 -55oC - 0.4 V 1, 2, 3 -55 C ≤ TA ≤ +125 C o o ≤ TA ≤ o +125oC o IOH = -100µA, VCC = 4.5V Input Leakage Current II 3.0 - V VCC -0.4 - V VIN = GND or VCC , VCC = 5.5V, Pins 29, 31, 57, 59, 61, 63-64 1, 2, 3 -55 C ≤ TA ≤ +125 C -10 10 µA o o Input Sustaining Current LOW IBHL VCC = 4.5V and 5.5V, VIN = 1.0V, Note 1 1, 2, 3 -55oC ≤ TA ≤ +125oC 38 200 µA Input Sustaining Current HIGH IBHH VCC = 4.5V and 5.5V, VIN = 3.0V, Note 2 1, 2, 3 -55oC ≤ TA ≤ +125oC -50 -400 µA Input Sustaining Current on BUSY and ERROR Pins ISH VCC = 4.5V and 5.5V VIN = GND, Note 5 1, 2, 3 -55oC ≤ TA ≤ +125oC -30 -500 µA Output Leakage Current IO VO = GND or VCC VCC = 5.5V, Pins 1, 7-8, 10-28, 32-34 1, 2, 3 -55oC ≤ TA ≤ +125oC -10 10 µA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 185 mA - 220 mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 5 mA Active Power Supply Current ICCOP 80C286-10/883, Note 4 Standby Power Supply Current ICCSB VCC = 5.5V, Note 3 80C286-12/883, Note 4 NOTES: 2. IBHL should be measured after lowering VIN to GND and then raising to 1.0V on the following pins: 36-51, 66, 67. 3. IBHH should be measured after raising V IN to VCC and then lowering to 3.0V on the following pins: 4-6, 36-51, 66-68. 4. ICCSB should be tested with the clock stopped in phase two of the processor clock cycle. VIN = VCC or GND, VCC = 5.5V, outputs unloaded. 5. ICCOP measured at 10MHz for the 80C286-10/883 and 12.5MHz for the 80C286-12/883. VIN = 2.4V or 0.4V, VCC = 5.5V, outputs unloaded. 6. ISH should be measured after raising VIN to VCC and then lowering to 0V on pins 53 and 54. 130 80C286/883 TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device Guaranteed and 100% Tested. 80C286/883 10MHz 12.5MHz SYMBOL CONDITIONS GROUP A SUBGROUPS System Clock (CLK) Period 1 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 50 - 40 - ns System Clock (CLK) Low Time 2 VCC = 4.5V and 5.5V at 1.0V 9, 10, 11 -55oC ≤TA ≤ +125oC 12 - 11 - ns System Clock (CLK) High Time 3 VCC = 4.5V and 5.5V at 3.6V 9, 10, 11 -55oC ≤ TA ≤ +125oC 16 - 13 - ns Asynchronous Inputs SETUP Time (Note 1) 4 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 20 - 15 - ns Asynchronous Inputs HOLD Time (Note 1) 5 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 20 - 15 - ns RESET SETUP Time 6 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 19 - 10 - ns RESET HOLD Time 7 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - ns Read Data SETUP Time 8 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 8 - 5 - ns Read Data HOLD Time 9 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 4 - 4 - ns READY SETUP Time 10 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 26 - 20 - ns READY HOLD Time 11 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤TA ≤ +125oC 25 - 20 - ns Status/PEACK Active Delay, (Note 4) 12A VCC = 4.5V and 5.5V, CL = 100pF IL = |2mA| 9, 10, 11 -55oC ≤ TA ≤ +125oC 1 22 1 21 ns Status/PEACK Inactive Delay (Note 3) 12B VCC = 4.5V and 5.5V, CL = 100pF IL = |2mA| 9, 10, 11 -55oC ≤ TA ≤ +125oC 1 30 1 24 ns Address Valid Delay (Note 2) 13 VCC = 4.5V and 5.5V, CL = 100pF IL = |2mA| 9, 10, 11 -55oC ≤ TA ≤ +125oC 1 35 1 32 ns Write Data Valid Delay, (Note 2) 14 VCC = 4.5V and 5.5V, CL = 100pF IL = |2mA| 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 40 0 31 ns PARAMETER 131 TEMPERATURE MIN MAX MIN MAX UNITS 80C286/883 TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device Guaranteed and 100% Tested. 80C286/883 10MHz PARAMETER SYMBOL HLDA Valid Delay (Note 5) 15 CONDITIONS VCC = 4.5V and 5.5V, CL = 100pF IL = |2mA| 12.5MHz GROUP A SUBGROUPS TEMPERATURE MIN MAX MIN MAX UNITS 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 47 0 25 ns NOTES: 1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure recognition at a specific CLK edge. 2. Delay from 1.0V on the CLK to 0.8V or 2.0V. 3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay). 4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay). 5. Delay from 1.0V on the CLK to 2.0V. TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS 80C286/883 10MHz PARAMETER SYMBOL CLK Input Capacitance CCLK Other Input Capacitance CIN I/O Capacitance CI/O Address/Status/Data Float Delay 15 Address Valid to Status SETUP Time 19 CONDITIONS FREQ = 1MHz FREQ = 1MH FREQ = 1MH NOTES TEMPERATURE 5 TA = o MIN MAX MIN MAX UNITS - 10 - 10 pF 5 TA = +25 C - 10 - 10 pF 5 +25oC TA = - 10 - 10 pF +125oC 0 47 0 32 ns -55oC ≤ TA ≤ +125oC 27 - 20 - ns -55oC 1, 3, 4, 5 IL = | 2.0mA| +25oC 12.5MHz 1, 2, 5 ≤ TA ≤ NOTES: 1. Output Load: C L = 100pF. 2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching 2.0V. 3. Delay from 1.0V on the CLK to Float (no current drive) condition. 4. I L = -6mA (VOH to Float), IL = 8mA (VOL to Float). 5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 1, 7, 9 PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples/5005 1, 7, 9 Group A Group C & D 132 80C286/883 AC Electrical Specifications 82C284 and 82C288 Timing Specifications Are Given For Reference Only, And No Guarantee is Implied. 82C284 Timing 10MHz SYMBOL PARAMETER 12.5MHz MIN MAX MIN MAX UNIT TEST CONDITION TIMING REQUIREMENTS 11 SRDY/SRDYEN Setup Time 15 - 15 - ns 12 SRDY/SRDYEN Hold Time 2 - 2 - ns 13 ARDY/ARDYEN Setup Time 5 - 5 - ns (Note 1) 14 ARDY/ARDYEN Hold Time 30 - 25 - ns (Note 1) 0 20 0 16 ns CL = 75pF, IOL = 5mA, IOH = -1mA TIMING RESPONSES 19 PCLK Delay NOTE: 1. These times are given for testing purposes to ensure a predetermined action. 82C288 Timing 10MHz SYMBOL PARAMETER 12.5MHz MIN MAX MIN MAX UNIT TEST CONDITION TIMING REQUIREMENTS 12 CMDLY Setup Time 15 - 15 - ns 13 CMDLY Hold Time 1 - 1 - ns TIMING RESPONSES 16 ALE Active Delay 1 16 1 16 ns 17 ALE Inactive Delay - 19 - 19 ns 19 DT/R Read Active Delay - 23 - 23 ns CL = 150pF 20 DEN Read Active Delay 0 21 0 21 ns IOL = 16mA Max 21 DEN Read Inactive Delay 3 23 3 21 ns IOH = -1mA Max 22 DT/R Read Inactive Delay 5 24 5 18 ns 23 DEN Write Active Delay - 23 - 23 ns 24 DEN Write Inactive Delay 3 23 3 23 ns 29 Command Active Delay from CLK 3 21 3 21 ns CL = 300pF 30 Command Inactive Delay from CLK 3 20 3 20 ns IOL = 32mA Max 133 80C286/883 AC Specifications 4.0V 3.6V 3.6V CLK INPUT 1.0V 1.0V 0.45V 4.0V 3.6V 3.6V CLK INPUT 1.0V 1.0V 0.45V tSETUP tHOLD 2.4V 2.0V 2.0V 0.8V 0.8V OTHER DEVICE INPUT 0.4V tDELAY (MAX) tDELAY (MIN) 2.0V DEVICE OUTPUT 0.8V NOTE: 1. For AC testing, input rise and fall times are driven at 1ns per volt. FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT 134 80C286/883 135 80C286/883 Waveforms READ CYCLE ILLUSTRATED WITH ZERO WAIT STATES TS TC TI BUS CYCLE TYPE VOH 3 1 φ2 φ2 φ1 WRITE CYCLE ILLUSTRATED WITH ONE WAIT STATE TS TC φ2 φ1 φ2 φ1 READ (TI OR TS) TC φ2 φ1 φ2 φ1 CLK 2 12A 12B VOL S1 • S0 19 19 80C286/883 13 A23 - A0 M/IO, COD INTA 13 VALID ADDRESS VALID ADDRESS 13 VALID CONTROL BHE, LOCK VALID IF TS 13 VALID CONTROL 9 14 15 8 VALID WRITE DATA D15 - D0 VALID READ DATA 11 11 10 10 READY 12 82C284 (SEE NOTE 2) 11 SRDY + SRDYEN 19 14 13 ARDY + ARDYEN 19 19 16 17 20 PCLK ALF 12 13 13 12 13 12 82C288 (SEE NOTE 2) CMDLY 29 30 MWTC 29 30 (SEE NOTE 1) MRDC 19 DT/R 22 20 21 23 DEN NOTES: 1. The modified timing is due to the CMDLY signal being active. 2. 82C254 and 82C288 Timing Waveforms are shown for reference only, and no guarantee is inplied. FIGURE 2. MAJOR CYCLE TIMING 136 24 80C286/883 Waveforms (Continued) BUS CYCLE TYPE VCH TX φ1 VCH φ2 CLK φ2 TX φ1 VCL 19 VCL 19 PCLK (SEE NOTE 1) 7 (SEE NOTE 1) 6 RESET 5 INTR, NMI HOLD, PEREQ (SEE NOTE 2) 4 φ2 φ1 CLK 4 VCH TX φ2 φ1 φ2 CLK VCL 5 7 6 (SEE NOTE 1) RESET ERROR, BUSY (SEE NOTE 2) NOTES: 1. PCLK indicates which processor cycle phase will occur on the next CLK. PCLK may not indicate the correct phase until the first cycle is performed. NOTE: 2. These inputs are asynchronous. The setup and hold times shown assure recognition for testing purposes. 1. When RESET meets the setup time shown, the next CLK will start or repeat φ1 of a processor cycle. FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL TIMING FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSEQUENT PROCESSOR CYCLE PHASE 137 80C286/883 Waveforms (Continued) BUS CYCLE TYPE φ1 VCH TH φ2 TH OR TI φ1 φ2 φ1 TI φ2 φ1 TH φ2 CLK VCL HILDA 16 16 (SEE NOTE 4) 12A (NOTE 3) 80C286/883 S1 • S0 15 (SEE NOTE 3) IF TS 12B 15 PEACK IF NPX TRANSFER BHE, LOCK A23 - A0, M/IO, COD/INTA (SEE NOTE 1) 13 15 (SEE NOTE 5) VALID (SEE NOTE 2) 15 14 D15 - D0 (SEE NOTE 6) 80C284 VALID IF WRITE PCLK NOTES: 1. 2. 3. 4. 5. 6. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown. The data bus will be driven as shown if the last cycle before TI in the diagram was a write TC. The 80C286/883 puts its status pins in a high impedance logic one state during TH. For HOLD request set up to HLDA, refer to Figure 8. BHE and LOCK are driven at this time but will not become valid until TS. The data bus will remain in a high impedance state if a read cycle is performed. FIGURE 5. EXITING AND ENTERING HOLD 138 80C286/883 Waveforms (Continued) BUS CYCLE TYPE VCH TI φ2 TS φ1 φ2 1 TC φ2 TS φ1 φ2 φ1 TC φ2 TI φ1 CLK VCL I/0 READ IF PROC. EXT. TO MEMORY MEMORY READ IF MEMORY TO PROC. EXT S1 • S0 CLK A23 -A0 M/IO, COD INTA MEMORY WRITE IF PROC. EXT. TO MEMORY I/O WRITE IF MEMORY TO PROC. EXT. MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O PORT ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER 12A I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER 12B PEACK (SEE NOTE 1) 5 (SEE NOTE 2) 4 PEREQ NOTES: 1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus operation will be either a memory read at operand address or I/O read at port address 00FA(H). 2. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x 1 - 12A MAX -(4)MIN The actual, configuration dependent, maximum time is: 3 x 1 - 12AMAX - (4)MIN +N x 2 x (1). N is the number of extra TC states added to either the first or second bus operation of the processor extension data operand transfer sequence. FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY BUS CYCLE TYPE VCH φ2 φ1 TX φ2 φ1 TX φ2 TX φ1 φ2 φ1 TI φ2 CLK VCL 6 (SEE NOTE 2) (SEE NOTE 1) AT LEAST 16 CLK PERIODS RESET 6 7 12B S1 • S0 UNKNOWN PEACK 13 A23 - A0 BHE UNKNOWN 13 M/IO COD/INTA UNKNOWN 13 LOCK UNKNOWN 15 (SEE NOTE 3) DATA 16 HILDA UNKNOWN NOTES: 1. Setup time for RESET ↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later. 2. Setup and hold times for RESET ↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2. 3. The data bus is only guaranteed to be in a high impedance state at the time shown. FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET BUS HOLD ACKNOWLEDGE BUS HOLD ACKNOWLEDGE WRITE CYCLE BUS CYCLE TYPE TH φ1 CLK TH φ2 φ1 TS TH φ2 φ1 φ2 φ1 TC φ2 φ1 TC φ2 φ1 TC φ2 φ1 139 (SEE NOTE 5) TI φ2 φ1 TH φ2 φ1 φ2 80C286/883 Die Characteristics DIE DIMENSIONS: 286 x 283 x 19 ±1mils METALLIZATION: Type: Si-Al Thickness: 8kÅ GLASSIVATION: Type: Nitrox Thickness: 10kÅ WORST CASE CURRENT DENSITY: 2 X 105A/cm2 LEAD TEMPERATURE: (10s Soldering): ≤ 300oC Metallization Mask Layout 80C286/883 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Spec Number 140