Cypress CY7C1543KV18 72-mbit qdrâ®ii sram 4-word burstarchitecture (2.0 cycle read latency) Datasheet

CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
®
72-Mbit QDR II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
Configurations
■
Separate independent read and write data ports
❐ Supports concurrent transactions
With Read Cycle Latency of 2.0 cycles:
■
450 MHz clock for high bandwidth
CY7C1556KV18 – 8M x 9
■
4-word burst for reducing address bus frequency
CY7C1543KV18 – 4M x 18
■
Double Data Rate (DDR) interfaces on both read and write
ports (data transferred at 900 MHz) at 450 MHz
CY7C1545KV18 – 2M x 36
■
Available in 2.0 clock cycle latency
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■
Data valid pin (QVLD) to indicate valid data on the output
■
Single multiplexed address input bus latches address inputs
for read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
QDR® II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
■
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency, providing most current data
■
Core VDD = 1.8V± 0.1V; IO VDDQ = 1.4V to VDD [1]
❐ Supports both 1.5V and 1.8V IO supply
■
HSTL inputs and variable drive HSTL output buffers
■
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Phase-Locked Loop (PLL) for accurate data placement
CY7C1541KV18 – 8M x 8
Functional Description
The CY7C1541KV18, CY7C1556KV18, CY7C1543KV18, and
CY7C1545KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common IO devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C1541KV18), 9-bit words (CY7C1556KV18), 18-bit
words (CY7C1543KV18), or 36-bit words (CY7C1545KV18) that
burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
450 MHz
400 MHz
375 MHz
333 MHz
Unit
450
400
375
333
MHz
x8
760
690
660
600
mA
x9
760
690
660
600
Maximum Operating Frequency
Maximum Operating Current
x18
780
710
680
620
x36
1100
1000
950
850
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
Cypress Semiconductor Corporation
Document Number: 001-15700 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 31, 2009
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Logic Block Diagram (CY7C1541KV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
2M x 8 Array
K
CLK
Gen.
Write
Reg
2M x 8 Array
K
Write
Reg
2M x 8 Array
Address
Register
Write
Reg
2M x 8 Array
A(20:0)
21
8
Write Add. Decode
D[7:0]
21
A(20:0)
RPS
Control
Logic
Read Data Reg.
CQ
32
VREF
WPS
16
Control
Logic
Reg.
16
NWS[1:0]
Reg.
CQ
Reg. 8
8
8
8
8
Q[7:0]
QVLD
Logic Block Diagram (CY7C1556KV18)
DOFF
Address
Register
Read Add. Decode
K
CLK
Gen.
Write
Reg
2M x 9 Array
K
Write
Reg
2M x 9 Array
Address
Register
Write
Reg
2M x 9 Array
21
Write
Reg
2M x 9 Array
A(20:0)
9
Write Add. Decode
D[8:0]
21
A(20:0)
RPS
Control
Logic
Read Data Reg.
CQ
36
VREF
WPS
18
Control
Logic
BWS[0]
18
Reg.
Reg.
Reg. 9
9
9
9
CQ
9
Q[8:0]
QVLD
Document Number: 001-15700 Rev. *F
Page 2 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Logic Block Diagram (CY7C1543KV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
1M x 18 Array
K
CLK
Gen.
Write
Reg
1M x 18 Array
K
Write
Reg
1M x 18 Array
Address
Register
Write
Reg
1M x 18 Array
A(19:0)
20
18
Write Add. Decode
D[17:0]
20
A(19:0)
RPS
Control
Logic
Read Data Reg.
CQ
72
VREF
WPS
36
Control
Logic
Reg.
36
BWS[1:0]
Reg.
CQ
Reg. 18
18
18
18
18
Q[17:0]
QVLD
Logic Block Diagram (CY7C1545KV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
512K x 36 Array
K
CLK
Gen.
Write
Reg
512K x 36 Array
K
Write
Reg
512K x 36 Array
Address
Register
Write
Reg
512K x 36 Array
A(18:0)
19
36
Write Add. Decode
D[35:0]
19
A(18:0)
RPS
Control
Logic
Read Data Reg.
CQ
144
VREF
WPS
72
Control
Logic
BWS[3:0]
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q[35:0]
QVLD
Document Number: 001-15700 Rev. *F
Page 3 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Pin Configuration
The pin configurations for CY7C1541KV18, CY7C1556KV18, CY7C1543KV18, and CY7C1545KV18 follow.[2]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1541KV18 (8M x 8)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
A
A
WPS
NWS1
K
NC/144M
RPS
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
NWS0
A
NC
NC
Q3
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D3
D
NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q7
A
A
QVLD
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
CY7C1556KV18 (8M x 9)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
A
A
WPS
NC
K
NC/144M
RPS
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
BWS0
A
NC
NC
Q4
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D4
D
NC
D5
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
NC
D3
Q3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q2
D2
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D1
N
NC
D8
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q8
A
A
QVLD
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-15700 Rev. *F
Page 4 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Pin Configuration
The pin configurations for CY7C1541KV18, CY7C1556KV18, CY7C1543KV18, and CY7C1545KV18 follow.[2] (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1543KV18 (4M x 18)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/144M
A
WPS
BWS1
K
NC/288M
RPS
A
A
CQ
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
NC
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
QVLD
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
CY7C1545KV18 (4M x 36)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/288M
A
WPS
BWS2
K
BWS1
RPS
A
NC/144M
CQ
B
Q27
Q18
D18
A
BWS3
K
BWS0
A
D17
Q17
Q8
C
D27
Q28
D19
VSS
A
NC
A
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
QVLD
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Document Number: 001-15700 Rev. *F
Page 5 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
InputData Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CY7C1541KV18 − D[7:0]
CY7C1556KV18 − D[8:0]
CY7C1543KV18 − D[17:0]
CY7C1545KV18 − D[35:0]
WPS
InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
NWS0,
NWS1,
InputNibble Write Select 0, 1 − Active LOW (CY7C1541KV18 Only). Sampled on the rising edge of the K
Synchronous and K clocks when write operations are active. Used to select which nibble is written into the device
during the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
InputByte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1556KV18 − BWS0 controls D[8:0]
CY7C1543KV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1545KV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],
BWS2 controls D[26:18] and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8M x 8 (4 arrays each of 2M x 8) for CY7C1541KV18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1556KV18,
4M x 18 (4 arrays each of 1M x 18) for CY7C1543KV18 and 2M x 36 (4 arrays each of 512K x 36) for
CY7C1545KV18. Therefore, only 21 address inputs are needed to access the entire memory array of
CY7C1541KV18 and CY7C1556KV18, 20 address inputs for CY7C1543KV18 and 19 address inputs for
CY7C1545KV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
OutputsData Output Signals. These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tri-stated.
CY7C1541KV18 − Q[7:0]
CY7C1556KV18 − Q[8:0]
CY7C1543KV18 − Q[17:0]
CY7C1545KV18 − Q[35:0]
RPS
InputRead Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the K clock. Each read access consists of a burst of four sequential transfers.
QVLD
Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0].
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 23.
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 23.
Document Number: 001-15700 Rev. *F
Page 6 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Pin Definitions
Pin Name
(continued)
IO
Pin Description
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The
timings in the PLL turned off operation differs from those listed in this data sheet. For normal operation,
this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in
QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up
to 167 MHz with QDR I timing.
TDO
Output
TCK
Input
TCK Pin for JTAG
TDI
Input
TDI Pin for JTAG
TMS
Input
TMS Pin for JTAG
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
VREF
VDD
VSS
VDDQ
InputReference
TDO for JTAG
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Power Supply Power Supply Inputs to the Core of the Device
Ground
Ground for the Device
Power Supply Power Supply Inputs for the Outputs of the Device
Document Number: 001-15700 Rev. *F
Page 7 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Functional Overview
The CY7C1541KV18, CY7C1556KV18, CY7C1543KV18,
CY7C1545KV18 are synchronous pipelined Burst SRAMs
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and flows out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
By having separate read and write ports, the QDR II+ completely
eliminates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 8-bit data transfers in the case of
CY7C1541KV18, four 9-bit data transfers in the case of
CY7C1556KV18, four 18-bit data transfers in the case of
CY7C1543KV18, and four 36-bit data transfers in the case of
CY7C1545KV18, in two clock cycles.
These devices operate with a read latency of two cycles when
DOFF pin is tied HIGH. When DOFF pin is set LOW or connected
to VSS then device behaves in QDR I mode with a read latency
of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) outputs pass through output registers controlled
by the rising edge of the input clocks (K and K) as well.
All synchronous control (RPS, WPS, NWS[x:0], BWS[x:0]) inputs
pass through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1543KV18 is described in the following sections. The
same basic descriptions apply to CY7C1541KV18,
CY7C1556KV18 and CY7C1545KV18.
Read Operations
The CY7C1543KV18 is organized internally as four arrays of 1M
x 18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto
the Q[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q[17:0]. The requested data is valid
0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
Document Number: 001-15700 Rev. *F
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
When the read port is deselected, the CY7C1543KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the positive input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also stored
into the write data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device can not be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the positive input clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1543KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Concurrent Transactions
The read and write ports on the CY7C1543KV18 operates
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows
a write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Page 8 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Read access and write access must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations can not be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
can not be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in alternating read or write operations being initiated, with the first
access being a read.
Depth Expansion
The CY7C1543KV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM, the allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are
synchronized to the input clock of the QDR II+. The timing for the
echo clocks is shown in the Switching Characteristics on page
23.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
PLL
These chips use a PLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the PLL is locked after 20 μs
of stable clock. The PLL can also be reset by slowing or stopping
the input clocks K and K for a minimum of 30 ns. However, it is
not necessary to reset the PLL to lock to the desired frequency.
The PLL automatically locks 20 μs after a stable clock is
presented. The PLL may be disabled by applying ground to the
DOFF pin. When the PLL is turned off, the device behaves in
QDR I mode (with one cycle latency and a longer access time).
For information refer to the application note PLL Considerations
in QDRII/DDRII/QDRII+/DDRII+.
Application Example
Figure 1 shows two QDR II+ used in an application.
Figure 1. Application Example
Vt
R
DATA IN
DATA OUT
Address
ZQ
SRAM #1 CQ/CQ
Q
D
A RPS WPS BWS K K
RQ = 250 ohms
SRAM #2
RQ = 250 ohms
CQ/CQ
Q
RPS WPS BWS K K
D
A
R
R
BUS MASTER RPS
(CPU or ASIC) WPS
ZQ
Vt
Vt
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
Source K
Source K
R
Document Number: 001-15700 Rev. *F
R = 50ohms, Vt = VDDQ /2
Page 9 of 27
[+] Feedback
CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Truth Table
The truth table for CY7C1541KV18, CY7C1556KV18, CY7C1543KV18, and CY7C1545KV18 follows. [3, 4, 5, 6, 7, 8]
Operation
K
RPS WPS
[9]
DQ
DQ
DQ
DQ
[10]
D(A) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑
Write Cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
L-H
H
Read Cycle:
(2.0 cycle Latency)
Load address on the rising
edge of K; wait two cycles;
read data on two consecutive K and K rising edges.
L-H
L [10]
X
Q(A) at K(t + 2)↑ Q(A + 1) at K(t + 2)↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 3)↑
NOP: No Operation
L-H
H
H
D=X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
Stopped
X
X
Previous State
Previous State
Previous State
Previous State
Standby: Clock Stopped
L
Write Cycle Descriptions
The write cycle description table for CY7C1541KV18 and CY7C1543KV18 follows. [3, 11]
BWS0/ BWS1/
K
K
L
L–H
–
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
NWS0
NWS1
L
Comments
During the data portion of a write sequence:
CY7C1541KV18 − both nibbles (D[7:0]) are written into the device.
CY7C1543KV18 − both bytes (D[17:0]) are written into the device.
L-H During the data portion of a write sequence:
CY7C1541KV18 − both nibbles (D[7:0]) are written into the device.
CY7C1543KV18 − both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence:
CY7C1541KV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1543KV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence:
CY7C1541KV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1543KV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence:
CY7C1541KV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1543KV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence:
CY7C1541KV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1543KV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
11. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-15700 Rev. *F
Page 10 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Write Cycle Descriptions
The write cycle description table for CY7C1556KV18 follows. [3, 11]
BWS0
K
K
Comments
L
L–H
–
During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
–
L–H
During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L–H
–
No data is written into the device during this portion of a write operation.
H
–
L–H
No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1545KV18 follows. [3, 11]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
Document Number: 001-15700 Rev. *F
L–H During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
–
During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L–H During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
–
During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L–H During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
–
During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L–H During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
–
During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L–H During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Page 11 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively
be connected to VDD through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 14. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The section Boundary Scan Order on page 18 shows the order
in which the bits are connected. Each bit corresponds to one of
the bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-15700 Rev. *F
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Page 12 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advantage
of the BYPASS instruction is that it shortens the boundary scan
path when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered up, and also
when the TAP controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
Document Number: 001-15700 Rev. *F
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 13 of 27
[+] Feedback
CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [12]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
0
0
1
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-15700 Rev. *F
Page 14 of 27
[+] Feedback
CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
108
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range [13, 14, 15]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 μA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 μA
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65VDD VDD + 0.3
GND ≤ VI ≤ VDD
V
–0.3
0.35VDD
V
–5
5
μA
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
14. Overshoot: VIH(AC) < VDDQ + 0.35V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3V (Pulse width less than tCYC/2).
15. All Voltage referenced to Ground.
Document Number: 001-15700 Rev. *F
Page 15 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
TAP AC Switching Characteristics
Over the Operating Range [16, 17]
Parameter
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
50
ns
20
MHz
Setup Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [17]
Figure 2. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
1.8V
50Ω
0.9V
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
16. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-15700 Rev. *F
Page 16 of 27
[+] Feedback
CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Identification Register Definitions
Instruction Field
Value
CY7C1541KV18
CY7C1556KV18
CY7C1543KV18
CY7C1545KV18
000
000
000
000
Revision Number
(31:29)
Description
Version number.
Cypress Device ID 11010010101000100 11010010101001100 11010010101010100 11010010101100100 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
00000110100
00000110100
00000110100
1
1
1
1
ID Register
Presence (0)
Allows unique
identification of
SRAM vendor.
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-15700 Rev. *F
Page 17 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
11
10N
39
11D
67
1C
95
3M
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
108
Internal
24
9K
52
8A
80
1F
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document Number: 001-15700 Rev. *F
Page 18 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Power Up Sequence in QDR II+ SRAM
QDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ.
❐ Apply VDDQ before VREF or at the same time as VREF.
❐ Drive DOFF HIGH.
■
Provide stable DOFF (HIGH), power and clock (K, K) for 20 μs
to lock the PLL.
PLL Constraints
■
PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■
The PLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 μs of stable clock to
relock to the desired clock frequency.
~
~
Power Up Waveforms
K
K
~
~
Unstable Clock
> 20Ps Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
Document Number: 001-15700 Rev. *F
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to VDDQ)
Page 19 of 27
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CY7C1543KV18, CY7C1545KV18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Neutron Soft Error Immunity
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
Parameter
Description
Test
Conditions
Typ
Max*
Unit
LSBU
Logical
Single-Bit
Upsets
25°C
197
216
FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25°C
0
0.01
FIT/
Mb
SEL
Single
Event
Latchup
85°C
0
0.1
FIT/
Dev
DC Applied to Outputs in High Z ........ –0.5V to VDDQ + 0.3V
DC Input Voltage [14] .............................. –0.5V to VDD + 0.3V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015). > 2,001V
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature (TA)
VDD [18]
VDDQ [18]
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
–40°C to +85°C
* No LMBU or SEL events occurred during testing; this column represents a
statistical χ2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [15]
Parameter
VDD
VDDQ
VOH
VOL
VOH(LOW)
VOL(LOW)
VIH
VIL
IX
IOZ
VREF
Description
Power Supply Voltage
IO Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Input Reference Voltage [21]
Test Conditions
Note 19
Note 20
IOH = −0.1 mA, Nominal Impedance
IOL = 0.1 mA, Nominal Impedance
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
Typical Value = 0.75V
Min
Typ
Max
Unit
1.7
1.8
1.9
V
1.4
1.5
VDD
V
VDDQ/2 – 0.12
VDDQ/2 + 0.12 V
VDDQ/2 – 0.12
VDDQ/2 + 0.12 V
VDDQ – 0.2
VDDQ
V
VSS
0.2
V
VREF + 0.1
VDDQ + 0.15
V
–0.15
VREF – 0.1
V
−2
2
μA
−2
2
μA
0.68
0.75
0.95
V
Notes
18. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
19. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
20. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
21. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.
Document Number: 001-15700 Rev. *F
Page 20 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Electrical Characteristics
(continued)
DC Electrical Characteristics
Over the Operating Range [15]
Parameter
IDD
[22]
Description
VDD Operating Supply
Test Conditions
VDD = Max,
450 MHz
IOUT = 0 mA,
f = fMAX = 1/tCYC
(x8)
(x9)
(x18)
(x36)
400 MHz (x8)
(x9)
(x18)
(x36)
375 MHz (x8)
Max
760
760
780
1100
690
690
710
1000
660
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
(x36)
660
680
950
600
600
620
850
340
340
340
340
320
320
320
320
310
310
310
310
290
290
290
290
333 MHz
ISB1
Automatic Power down
Current
Max VDD,
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC,
Inputs Static
450 MHz
400 MHz
375 MHz
333 MHz
Min
Typ
Unit
mA
mA
mA
mA
mA
mA
mA
mA
AC Electrical Characteristics
Over the Operating Range [14]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
VREF + 0.2
–
VDDQ + 0.24
V
VIL
Input LOW Voltage
–0.24
–
VREF – 0.2
V
Note
22. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15700 Rev. *F
Page 21 of 27
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CY7C1543KV18, CY7C1545KV18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
CO
Output Capacitance
Test Conditions
Max
Unit
2
pF
3
pF
Test Conditions
165 FBGA
Package
Unit
Test conditions follow standard test methods and procedures
for measuring thermal impedance, in accordance with
EIA/JESD51.
13.7
°C/W
3.73
°C/W
TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
RL = 50Ω
VREF = 0.75V
ZQ
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
RQ =
250Ω
(a)
0.75V
INCLUDING
JIG AND
SCOPE
5 pF
[23]
0.25V
Slew Rate = 2 V/ns
RQ =
250Ω
(b)
Note
23. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
Document Number: 001-15700 Rev. *F
Page 22 of 27
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CY7C1543KV18, CY7C1545KV18
Switching Characteristics
Over the Operating Range [23, 24]
Cypress Consortium
Parameter Parameter
tPOWER
tCYC
tKH
tKHKH
tKHKL
tKLKH
tKHKH
Description
VDD(Typical) to the First Access [25]
K Clock Cycle Time
450 MHz
400 MHz
375 MHz
333 MHz
Min Max Min Max Min Max Min Max
1
1
1
1
2.2 8.4 2.5 8.4 2.66 8.4 3.0 8.4
Unit
ms
ns
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
K Clock Rise to K Clock Rise
(rising edge to rising edge)
0.4
0.4
0.94
–
–
–
0.4
0.4
1.06
–
–
–
0.4
0.4
1.13
–
–
–
0.4
0.4
1.28
–
–
–
ns
ns
ns
Address Setup to K Clock Rise
0.275
–
0.4
–
0.4
–
0.4
–
ns
Control Setup to K Clock Rise (RPS, WPS)
DDR Control Setup to Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.275
0.22
–
–
0.4
0.28
–
–
0.4
0.28
–
–
0.4
0.28
–
–
ns
ns
D[X:0] Setup to Clock (K/K) Rise
0.22
–
0.28
–
0.28
–
0.28
–
ns
Address Hold after K Clock Rise
Control Hold after K Clock Rise (RPS, WPS)
DDR Control Hold after Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.275
–
0.4
–
0.4
–
0.4
–
ns
0.275
0.22
–
–
0.4
0.28
–
–
0.4
0.28
–
–
0.4
0.28
–
–
ns
ns
D[X:0] Hold after Clock (K/K) Rise
0.22
–
0.28
–
0.28
–
0.28
–
ns
K/K Clock Rise to Data Valid
Data Output Hold after Output K/K Clock Rise
(Active to Active)
–
0.45
–
0.45
–
0.45
–
0.45
–0.45 – –0.45 – –0.45 – –0.45 –
ns
ns
tCQOH
tCQD
tCQDOH
tCQH
tCQHCQH
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
tCQHCQH
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH [26]
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge) [26]
–
0.45
–
0.45
–
0.45
–
0.45
–0.45 – –0.45 – –0.45 – –0.45 –
0.15
0.20
0.20
0.20
–0.15 – –0.20 – –0.20 – –0.20 –
0.85
–
1.0
–
1.08
–
1.25
–
0.85
–
1.0
–
1.08
–
1.25
–
ns
ns
ns
ns
ns
ns
tCHZ
tCHQZ
Clock (K/K) Rise to High Z
(Active to High Z) [27, 28]
tCLZ
tQVLD
tCHQX1
Clock (K/K) Rise to Low Z [27, 28]
Echo Clock High to QVLD Valid [29]
tKL
tKHKH
Setup Times
tSA
tAVKH
tSC
tSCDDR
tIVKH
tIVKH
tSD
tDVKH
Hold Times
tHA
tKHAX
tHC
tKHIX
tHCDDR
tKHIX
tHD
tKHDX
Output Times
tCHQV
tCO
tCHQX
tDOH
tCCQO
tCQHQVLD
PLL Timing
tKC Var
tKC Var
tKC lock
tKC lock
tKC Reset tKC Reset
Clock Phase Jitter
PLL Lock Time (K)
K Static to PLL Reset [30]
–
0.45
–
0.45
–
0.45
–
0.45
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.15 0.15 –0.20 0.20 –0.20 0.20 –0.20 0.20
–
20
30
0.15
–
–
20
30
0.20
–
–
20
30
0.20
–
–
20
30
0.20
–
ns
ns
ns
ns
μs
ns
Notes
24. When a part with a maximum frequency above 333 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
25. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be
initiated.
26. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
27. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms” on page 22. Transition is measured ± 100 mV from steady-state
voltage.
28. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
29. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
30. Hold to >VIH or <VIL.
Document Number: 001-15700 Rev. *F
Page 23 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Switching Waveforms
Read/Write/Deselect Sequence [31, 32, 33]
Figure 3. Waveform for 2.0 Cycle Read Latency
NOP
1
READ
2
WRITE
3
READ
4
NOP
6
WRITE
5
7
8
K
t KH
t CYC
t KL
t KHKH
K
RPS
t SC
tHC
t SC
t HC
WPS
A
A0
A1
A3
A2
t HD
t SA t HA
t SD
D
t HD
t SD
D10
D11
D12
D13
D30
D31
D32
D33
t QVLD
t QVLD
QVLD
t CLZ
Q
tDOH
t
CO
Q00
(Read Latency = 2.0 Cycles)
tCQDOH
tCQD
Q01
Q02
Q03
Q20
Q21
Q22
tCHZ
Q23
tCCQO
tCQOH
CQ
t CQH
t CQHCQH
tCQOH
t CCQO
CQ
DON’T CARE
UNDEFINED
Notes
31. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
32. Outputs are disabled (High Z) one clock cycle after a NOP.
33. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note
applies to the whole diagram.
Document Number: 001-15700 Rev. *F
Page 24 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://app.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=
201&PageID=230.
Table 2. Ordering Information
Speed
(MHz)
450
Ordering Code
CY7C1543KV18-450BZC
Package
Diagram
Package Type
Operating
Range
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1545KV18-450BZC
CY7C1543KV18-450BZI
CY7C1545KV18-450BZXI
400
CY7C1543KV18-400BZC
165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1545KV18-400BZC
CY7C1543KV18-400BZI
CY7C1545KV18-400BZXI
Document Number: 001-15700 Rev. *F
165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Page 25 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Package Diagram
Figure 4. 165-Ball FBGA (13 x 15 x 1.4 mm)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.50 -0.06
(165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
E
F
F
G
G
H
J
14.00
E
15.00±0.10
15.00±0.10
10
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
A
1.00
5.00
10.00
B
B
13.00±0.10
13.00±0.10
0.15 C
1.40 MAX.
0.53±0.05
0.25 C
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
0.35±0.06
0.36
SEATING PLANE
C
Document Number: 001-15700 Rev. *F
51-85180-*A
Page 26 of 27
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CY7C1541KV18, CY7C1556KV18
CY7C1543KV18, CY7C1545KV18
Document History Page
Document Title: CY7C1541KV18/CY7C1556KV18/CY7C1543KV18/CY7C1545KV18, 72-Mbit QDR®II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Document Number: 001-15700
Rev.
ECN
Submission
Date
Orig. of
Change
**
1103943
See ECN
NXR
*A
1246904
See ECN
Description of Change
New datasheet
VKN/AESA Removed 300 MHz speed bin
Added footnote# 2
*B
1739283
See ECN
VKN/AESA Converted from Advance Information to Preliminary
*C
1922548
See ECN
VKN/AESA Corrected typo in the tCYC(min) and tKHKH(min) spec for 333 MHz speed bin
Added footnote # 22 related to IDD
Changed PLL lock time from 2048 cycles to 20 μs
Corrected typo in footnote # 26
*D
2612383
11/25/08
VKN/AESA Changed JTAG ID [31:29] from 001 to 000,
Updated Power up sequence waveform and it’s description,
Included Thermal Resistance values,
Changed the package size from 15 x 17 x 1.4 mm to 13 x 15 x 1.4 mm.
Updated data sheet template.
*E
2697841
04/24/09
VKN
Moved to external web
*F
2746858
07/31/09
VKN
Converted from preliminary to final
For 450 MHz speed, changed tCO, tCCQO, tCHZ from 370 ps to 450 ps
and tDOH, tCQOH, tCLZ from -370 ps to -450 ps
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information
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Document Number: 001-15700 Rev. *F
Revised July 31, 2009
Page 27 of 27
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
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