CY22801 Universal Programmable Clock Generator (UPCG) Features Benefits ■ Integrated Phase-Locked Loop (PLL) ■ ■ Field Programmable Inventory of only one device, CY22801, used in various applications ■ Input Frequency Range: ❐ Crystal: 8 to 30 MHz ❐ CLKIN: 1 to 133 MHz ■ In-house programming of sample and prototype quantities is made available using the CY36800 InstaClock kit ■ Input and output frequencies are customized to suit your needs ■ High-performance PLL is tailored for multiple applications ■ Critical timing requirements met in complex system designs ■ Application compatibility enabled ■ LVCMOS Output Frequency: ❐ 1 to 200 MHz (Commercial Grade) ❐ 1 to 166.6 MHz (Industrial Grade) ■ Low Jitter, High Accuracy Outputs ■ 3.3V Operation ■ Commercial and Industrial Temperature Ranges ■ 8-Pin SOIC Package Logic Block Diagram CLKA XIN/CLKIN XTAL OSC OUTPUT DIVIDERS PLL XOUT CLKB CLKC Pin Configuration Figure 1. CY22801 8-Pin SOIC 8 XOUT 2 7 CLKC 3 6 CLKA 4 5 CLKB XIN/CLKIN 1 VDD NC VSS Table 1. Pin Definition Name Pin Number Description XIN 1 Reference Input: Crystal or External Clock VDD 2 3.3V Voltage Supply NC 3 No Connect; leave this pin floating VSS 4 Ground CLKB 5 Clock Output B CLKA 6 Clock Output A CLKC 7 Clock Output C XOUT 8 Reference Output: Connect to external crystal. When the reference is an external clock signal (applied to pin 1), this pin is not used and must be left floating. Cypress Semiconductor Corporation Document #: 001-15571 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 26, 2009 [+] Feedback CY22801 General Description Output Clock Frequencies The CY22801 is a flash-programmable clock generator that supports various applications in consumer and communications markets. The device uses a Cypress proprietary PLL to drive up to three configurable outputs in an 8-pin SOIC. The CY22801 is a very flexible clock generator with up to three individual outputs, generated from an integrated PLL. Details are shown in Figure 2. The CY22801 is programmed with an easy-to-use programmer dongle, the CY36800, in conjunction with the CyClocksRT™ software. This enables fast sample generation of prototype builds for user-defined frequencies. Field Programming the CY22801 The CY22801 is programmed using the CY36800 USB programmer dongle. The CY22801 is flash-technology based, so the parts are reprogrammed up to 100 times. This enables fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. The output of the PLL runs at high frequency and is divided down to generate the output clocks. Two programmable dividers are available for this purpose. Thus, although the output clocks may be different frequencies, they must be related, based on the PLL frequency. It is also possible to direct the reference clock input to any of the outputs, thereby bypassing the PLL. Lastly, the reference clock may be passed through either divider. Figure 2. Basic PLL Block Diagram REF (XIN/CLKIN) /Q PFD CyClocksRT is an easy-to-use software application that enables the user to custom-configure the CY22801. Users can specify the XIN/CLKIN frequency, crystal load capacitance, and output frequencies. CyClocksRT then creates an industry standard JEDEC file, which is used to program the CY22801. When needed, an advanced mode is available that enables users to override the automatically generated VCO frequency and output divider values. CyClocksRT is a component of the CyberClocks™ software, which is downloaded free of charge from the Cypress website at http://www.cypress.com. CY36800 InstaClock™ Kit The Cypress CY36800 InstaClock Kit comes with everything needed to design the CY22801 and program samples and small prototype quantities. The CyClocksRT software is used to quickly create a JEDEC programming file, which is then downloaded directly to the portable programmer that is included in the CY36800 InstaClock Kit. The JEDEC file can also be saved for use in a production programming system for larger volumes. The CY36800 also comes with five samples of the CY22800, which are programmed with preconfigured JEDEC files using the InstaClock software. Document #: 001-15571 Rev. *B Post Divider 1N CLKA Samples and small prototype quantities are programmed using the CY36800 programmer. Cypress’s value added distribution partners and third party programming systems from BP Microsystems, HiLo Systems, and others, are available for large production quantities. CyClocksRT Software VCO /P Post Divider 2N Crosspoint Switch Matrix CLKB CLKC Reference Crystal Input The input crystal oscillator of the CY22801 is an important feature because of the flexibility it allows the user in selecting a crystal as a reference clock source. The oscillator inverter has programmable gain, enabling maximum compatibility with a reference crystal, based on manufacturer, process, performance, and quality. Input load capacitors are placed on the CY22801 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when nonlinear load capacitance is affected by load, bias, supply, and temperature changes. The value of the input load capacitors is determined by eight bits in a programmable register. Total load capacitance is determined by the formula: CapLoad = (CL – CBRD – CCHIP)/0.09375 pF In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22801. Applications Controlling Jitter Jitter is defined in many ways, including: ■ Phase noise ■ Long-term jitter ■ Cycle-to-cycle jitter ■ Period jitter ■ Absolute jitter ■ Deterministic jitter Page 2 of 7 [+] Feedback CY22801 These jitter terms are usually given in terms of RMS, peak-to-peak, or in the case of phase noise, dBC/Hz with respect to the fundamental frequency. Actual jitter is dependent on Reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. Reducing the total number of active outputs also reduces jitter in a linear fashion. However, it is better to use two outputs to drive two loads than one output to drive two loads. ■ XIN jitter and edge rate ■ Number of active outputs ■ Output frequencies ■ Supply voltage ■ Temperature Cypress Programmable Clocks ■ Output load Cypress offers a wide range of programmable clock synthesizers that can generate any other frequencies not covered by the CY22801. Table 2 summarizes all Cypress programmable devices including CY22801. For additional information, refer to the application note, Jitter in PLL-based Systems: Causes, Effects, and Solutions, available at http://www.cypress.com. Power supply noise and clock output loading are two major system sources of clock jitter. Power supply noise is mitigated by proper power supply decoupling (0.1-μF ceramic cap) of the clock and ensuring a low impedance ground to the chip. Table 2. Cypress Programmable Clocks[1] No. of PLL Input Freq. Output Freq. Package No. of Outputs Spread Spectrum VCXO I2C CY22800 1 0.5–100 1–200 8-SOIC Up to 3 Yes Yes No CY22801 1 1–133 1–200 8-SOIC Up to 3 No No No CY22050 1 1–133 0.08–200 16-TSSOP Up to 6 No No No CY22150 1 1–133 0.08–200 16-TSSOP Up to 6 No No Yes CY25100 1 8–166 3–200 8-SOIC/TSSOP Up to 2 Yes No No CY25200 1 3–166 3–200 16-TSSOP Up to 6 Yes No No CY241V08 1 27/13.5 27/13.5 8-SOIC Up to 2 No Yes No CY22392 3 1–166 1–200 16-TSSOP Up to 6 No No No Part # CY22381 3 1–166 1–200 8-SOIC Up to 3 No No No CY22393 3 1–166 1–200 16-TSSOP Up to 6 No No Yes CY22394/5 3 1–166 1–200 16-TSSOP Up to 5 No No No CY22388/89/91 4 1–100 4.2–166 16/20-TSSOP, 32-QFN Up to 8 No Yes No Note 1. The CY22800 and CY22801 are programmed using the programming dongle included in the CY36800 InstaClock Kit. The CY3672 programmer are used to program all other Cypress Programmable Clocks. Document #: 001-15571 Rev. *B Page 3 of 7 [+] Feedback CY22801 Absolute Maximum Conditions Parameter Description Min Max Unit VDD Supply Voltage –0.5 4.6 V TS Storage Temperature –65 150 °C TJ Junction Temperature VIO Input and Output Voltage ESD Electro-Static Discharge Voltage per MIL-STD-833, Method 3015 – 125 °C VSS – 0.5 VDD + 0.5 V 2000 – V Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature, Commercial Grade Ambient Temperature, Industrial Grade CLOAD Max. Load Capacitance on the CLK output tPU Power up time for VDD to reach minimum specified voltage (power ramps must be monotonic) Min Typ Max Unit 3.14 3.3 3.47 V 0 – 70 °C –40 -- 85 °C – – 15 pF 0.05 – 500 ms Min Typ Max Unit 8 – 30 MHz Recommended Crystal Specifications Parameter Name Description FNOM Nominal Crystal Frequency Parallel resonance, fundamental mode, and AT cut CLNOM Nominal Load Capacitance 6 – 30 pF R1 Equivalent Series Resistance Fundamental mode (ESR) – 35 50 Ω DL Crystal Drive Level – 0.5 2 mW Min Typ Max Unit 12 24 – mA No external series resistor assumed DC Electrical Specifications[2] Parameter Name Description IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V (source) IOL Output Low Current VOL = 0.5, VDD = 3.3V (sink) 12 24 – mA VIH Input High Voltage 0.7*VDD – VDD + 0.3 V VIL Input Low Voltage VSS – 0.3 – 0.3*VDD V CIN1 Input Capacitance All input pins except XIN and XOUT – – 7 pF CIN2 Input Capacitance XIN and XOUT pins IDD[3, 4] VDD Supply Current – 24 – pF – 70 – mA Notes 2. Not 100% tested, guaranteed by design. 3. IDD current specified for three CLK outputs running at 100 MHz. 4. Use CyClocksRT to calculate actual IDD for specific output frequency configurations. Document #: 001-15571 Rev. *B Page 4 of 7 [+] Feedback CY22801 AC Electrical Characteristics[2] Parameter Name Description Min Typ Max Unit fREFC Reference Frequency crystal 8 – 30 MHz fREFD Reference Frequency - driven 1 – 133 MHz fOUT Output Frequency, Commercial Grade 1 – 200 MHz Output Frequency, Industrial Grade 1 – 166.6 MHz DC Output Duty Cycle Duty Cycle is defined in Figure 4, 50% of VDD 45 50 55 % t3 Output Rising Edge Slew Rate 20% - 80% of VDD 0.8 1.4 – V/ns t4 Output Falling Edge Slew Rate 80% - 20% of VDD 0.8 1.4 – V/ns t5[5] Skew Output-output skew between related outputs – – 250 ps t6[6] Clock Jitter Peak-to-peak period jitter – 250 – ps t10 PLL Lock Time – – 3 ms Test Circuit Timing Definitions Figure 3. Test Circuit Diagram Figure 4. Duty Cycle Definition; DC = t2/t1 VDD 0.1μF OUTPUTS CLKout CLOAD t1 t2 CLK GND 50% 50% Figure 5. Rise and Fall Time Definitions t3 t4 80% CLK 20% Notes 5. Skew value guaranteed when outputs are generated from the same divider bank. 6. Jitter measurement may vary. Actual jitter is dependent on input jitter and edge rate, number of active outputs, input and output frequencies, supply voltage, temperature, and output load. For more information, refer to the application note, Jitter in PLL-based Systems: Causes, Effects, and Solutions. Document #: 001-15571 Rev. *B Page 5 of 7 [+] Feedback CY22801 Ordering Information Ordering Code Package Type [7] Operating Range Operating Voltage CY22801FXC 8-Pin SOIC Commercial, 0°C to 70°C 3.3V CY22801FXI[7] 8-Pin SOIC Industrial, – 40°C to 85°C 3.3V CY22801SXC-xxx[7, 8] 8-Pin SOIC Commercial, 0°C to 70°C 3.3V CY22801SXC-xxxT[7, 8] 8-Pin SOIC-Tape and Reel Commercial, 0°C to 70°C 3.3V CY22801KFXC 8-Pin SOIC Commercial, 0°C to 70°C 3.3V CY22801KFXCT 8-Pin SOIC-Tape and Reel Commercial, 0°C to 70°C 3.3V CY22801KFXI 8-Pin SOIC Industrial, – 40°C to 85°C 3.3V 8-Pin SOIC-Tape and Reel Industrial, – 40°C to 85°C 3.3V CY22801KSXC-xxx 8-Pin SOIC Commercial, 0°C to 70°C 3.3V CY22801KSXC-xxxT[8] 8-Pin SOIC-Tape and Reel Commercial, 0°C to 70°C 3.3V CY22801KSXI-xxx[8] 8-Pin SOIC Industrial, – 40°C to 85°C 3.3V CY22801KSXI-xxxT[8] 8-Pin SOIC-Tape and Reel Industrial, – 40°C to 85°C 3.3V CY22801KFXIT [8] Package Diagram Figure 6. 8-Pin (150-Mil) SOIC SZ08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85066-*C Notes 7. Not recommended for new designs. 8. Ordering codes with “xxx” are factory-programmed configurations. Factory programming is available for high volume orders. For more details, contact your local Cypress field application engineer or Cypress sales representative. Document #: 001-15571 Rev. *B Page 6 of 7 [+] Feedback CY22801 Document History Page Document Title: CY22801 Universal Programmable Clock Generator (UPCG) Document Number: 001-15571 REV. ECN NO. Orig. of Change Submission Date ** 1058080 KVM/ KKVTMP 05/10/07 New data sheet *A 2440787 AESA 05/16/08 Updated template. Added Note 7 and 8. Added existing part numbers CY22801FXCT, CY22801FXI, CY22801FXIT, CY22801SXC-xxx and CY22801SXC-xxxT in ordering information table. Added new part numbers CY22801KFXC, CY22801KFXCT, CY22801KFXI, CY22801KFXIT, CY22801KSXC-xxx and CY22801KSXC-xxxT. *B 2724806 KVM/ AESA 6/26/09 Add Industrial Grade Ambient Temperature to Recommended Operating Conditions. Add separate Fout max limit for industrial temp. Add temperature ranges to the Ordering Information Table. Remove CY22801FXCT and CY22801FXIT from Ordering Information Table. Add CY22801KSXI-xxx and CY22801KSXI-xxxT to Ordering Information Table. Correct package reference from S8 to SZ08. Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-15571 Rev. *B Revised March 12, 2009 Page 7 of 7 CyClocksRT, CyberClocks, and InstaClock are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback