[ /Title (CD74 HC174 , CD74 HCT17 4) /Subject (High Speed CMOS Logic Hex DType FlipFlop CD74HC174, CD74HCT174 Data sheet acquired from Harris Semiconductor SCHS159 High Speed CMOS Logic Hex D-Type Flip-Flop with Reset August 1997 Features Description • Buffered Positive Edge Triggered Clock The Harris CD74HC174 and CD74HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR input, when low, sets all outputs to a low state. • Asynchronous Common Reset • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times Each output can drive ten low power Schottky TTL equivalent loads. The CD74HCT174 is functional as well as, pin compatible to the 74LS174. • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V Ordering Information • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE CD74HC174E -55 to 125 16 Ld PDIP E16.3 CD74HCT174E -55 to 125 16 Ld PDIP E16.3 CD74HC174M -55 to 125 16 Ld SOIC M16.15 CD74HCT174M -55 to 125 16 Ld SOIC M16.15 CD74HCT174W -55 to 125 Wafer NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout CD74HC174, CD74HCT174 (PDIP, SOIC) TOP VIEW MR 1 16 VCC Q0 2 15 Q5 D0 3 14 D5 D1 4 13 D4 Q1 5 12 Q4 D2 6 11 D3 Q2 7 10 Q3 GND 8 9 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 1 File Number 1608.1 CD74HC174, CD74HCT174 Functional Diagram CP CP D R D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 MR TRUTH TABLE INPUTS OUTPUT RESET (MR) CLOCK CP DATA Dn Qn L X X L H ↑ H H H ↑ L L H L X Q0 NOTE: H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established Logic Diagram 3 (4, 6, 11, 13, 14) Dn D CL CL p p n n CL CL CL CL p p n n CL CL R ONE OF SIX F/F CL CL Q 2 (5, 7, 10, 12, 15) Qn CP 8 16 1 MR TO OTHER FIVE F/F VCC 9 CP TO OTHER FIVE F/F 2 CD74HC174, CD74HCT174 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) High Level Input Voltage VIH - Low Level Input Voltage VIL 25oC IO (mA) VCC (V) -40oC TO +85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V HC TYPES High Level Output Voltage CMOS Loads VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - - 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD74HC174, CD74HCT174 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC IO (mA) VCC (V) -40oC TO +85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 4. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS CP 0.80 MR 0.55 D 0.15 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. Prerequisite For Switching Function PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns HC TYPES Clock Pulse Width MR Pulse Width tw tw - - 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 4 CD74HC174, CD74HCT174 Prerequisite For Switching Function PARAMETER SYMBOL Setup Time, Data to Clock (Continued) TEST CONDITIONS VCC (V) tSU Hold Time, Data to Clock Removal Time, MR to Clock Clock Frequency MAX MIN MAX MIN MAX UNITS 2 60 - 75 - 90 - ns 4.5 12 - 15 - 18 - ns 6 10 - 13 - 15 - ns 2 5 - 5 - 5 - ns 4.5 5 - 5 - 5 - ns 6 5 - 5 - 5 - ns 2 5 - 5 - 5 - ns 4.5 5 - 5 - 5 - ns 6 5 - 5 - 5 - ns 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz - tREM - fMAX -40oC TO 85oC -55oC TO 125oC MIN - tH 25oC - HCT TYPES Clock Pulse Width tw - 4.5 20 - 25 - 30 - ns MR Pulse Width tw - 6 25 - 31 - 38 - ns Setup Time, Data to Clock tSU - 4.5 16 - 20 - 24 - ns Hold Time, Data to Clock tH - 6 5 - 5 - 5 - ns Removal Time, MR to Clock tREM - 4.5 12 - 15 - 18 - ns Clock Frequency fMAX - 6 25 - 20 - 17 - MHz Switching Specifications PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 165 205 250 ns 4.5 - 33 41 50 ns 6 - 28 35 43 ns CL = 15pF 5 13 - - - ns CL = 50pF 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 - 26 33 38 ns CL = 15pF 5 12 - - - ns CL = 50pF 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns HC TYPES Propagation Delay, Clock to Q Propagation Delay, MR to Q Output Transition Times tPLH, tPHL tTLH, tTHL Input Capacitance CIN - - - 10 10 10 pF Power Dissipation Capacitance (Notes 5, 6) CPD - 5 38 - - - pF 5 CD74HC174, CD74HCT174 Switching Specifications PARAMETER Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPLH, tPHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS CL = 50pF 4.5 - 40 50 60 ns CL = 15pF 5 17 - - - ns CL = 50pF 4.5 - 44 55 66 ns CL = 15pF 5 18 - - - ns CL = 50pF 4.5 - 15 19 22 ns HCT TYPES Propagation Delay, Clock to Q Propagation Delay, MR to Q tPLH, tPHL Output Transition Times tTLH, tTHL Input Capacitance CIN - - - 10 10 10 pF Power Dissipation Capacitance (Notes 5, 6) CPD - 5 44 - - - pF NOTES: 5. CPD is used to determine the dynamic power consumption, per flip-flop. 6. PD = VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms CLOCK INPUT trCL tfCL trCL VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET 1.3V 0.3V tH(L) DATA INPUT 3V 2.7V CLOCK INPUT 50% 10% tfCL CL 50pF FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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