128M GDDR2 SDRAM K4N26323AE-GC 128Mbit GDDR2 SDRAM 1M x 32Bit x 4 Banks GDDR2 SDRAM with Differential Data Strobe and DLL Revision 1.7 January 2003 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Revision History Revision 1.7 (January 23, 2003) - Changed the device name from GDDR-II to GDDR2 Revision 1.6 (December 18, 2002) - Typo corrected Revision 1.5 (December 4, 2002) - Typo corrected Revision 1.4 (November 12, 2002) - Changed the device name from DDR-II to GDDR-II - Typo corrected Revision 1.3 (November 8, 2002) - Typo corrected Revision 1.2 (November 5, 2002) - Typo corrected - Changed the Icc6 from 3mA to 7mA Revision 1.1 (October 30, 2002) - Typo corrected Revision 1.0 (September 30, 2002) - Changed tCK(max) from 4.5ns to 4.0ns Revision 0.7 (September 12, 2002) - Added IBIS curve in the spec - Defined DC spec - Typo corrected - Defined Burst Write with AP (AL=0) Table. - Defined On-die Termination Status of 2Banks System Table. - Changed CIN1,CIN2,CIN3,Cout and CiN4 from 3.5pF to 3.0pF - Removed CL(Cas Latency) 8 from the spec - Changed VDD form 2.5V + 5% to 2.5V + 0.1V - Changed speed bin from 500/400/333MHz to 500/450/400MHz - Changed EMRS table Revision 0.6 (February 28, 2002) - Changed WL(write latency) from RL(read latency) -1 to AL(additive latency) +1 - Changed tIH/tSS during EMRS from 5ns to 0.5tCK - Changed tRCDWR - Changed package ball location of CK, /CK, CKE - 2 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Revision 0.5 (January 2002) - Eliminated DLLEN pin - Power-up sequence Revision 0.4 (January 2002) - Changed EMRS Table - Changed Self-Refresh exit mode - Changed On-die Termination Control - Changed OCD Control method - Power-up sequence Revision 0.3 (December 2001) - Noted the ball names changed from DDR-1 and exchanged DQS and /DQS ball location. - Added On-die termination control - Changed OCD align mode entry / exit timing - Added target value of Data & DQS input/output capacitance(DQ0~DQ31) - Added Table for auto precharge control - Typo corrected. Revision 0.2 (November 2001) - Data Strobe Scheme is changed from DQS separation of Read DQS, Write DQS to Differential and Bi-directional DQS - OCD adjustment - Controlled DQ is changed from DQ0, WDQS2 to DQ23, DQS2 and /DQS2 Revision 0.1 (October 2001) - Data Strobe Scheme is changed from Bi-directional DQS to DQS separation to Read DQS, Write DQS - Package Ball layout is changed for mirror package. - OCD adjustment Controlled DQ is changed from DQ0, DQS0 to DQ23, WDQS2 - Added DM descriptions - 1bank, 2bank system - Added System Selection mode in EMRS table. Revision 0.0 (August 2001) - 3 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC 1M x 32Bit x 4 Banks GDDR2 Synchronous DRAM with Differential Data Strobe FEATURES • 2.5V + 0.1V power supply for device operation • Differential Data Strobes for Data-in, Date out ; • 1.8V + 0.1V power supply for I/O interface - 4 DQS and /DQS(one differential strobe per byte) • On-Die Termination for all inputs except CKE,ZQ - Single Data Strobes by EMRS. • Output Driver Strength adjustment by EMRS • Edge aligned data & data strobe output • SSTL_18 compatible inputs/outputs • Center aligned data & data strobe input • 4 banks operation • DM for write masking only • MRS cycle with address key programs • Auto & Self refresh • 32ms refresh period (4K cycle) - CAS latency : 5, 6, 7 (clock) - Burst length : 4 only (16ms is under consideration) - Burst type : sequential only • 144 Ball FBGA • Additive latency (AL): 0,1(clock) • Maximum clock frequency up to 500MHz • Read latency(RL) : CL+AL • Maximum data rate up to 1Gbps/pin • Write latency(WL) : AL+1 • DLL for Address, CMD and outputs ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4N26323AE-GC20 500MHz 1000Mbps/pin K4N26323AE-GC22 450MHz 900Mbps/pin K4N26323AE-GC25 400MHz 800Mbps/pin Interface Package SSTL_18 144 Ball FBGA GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank GDDR2 SDRAM The 4Mx32 GDDR2 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,976 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 4 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC PIN CONFIGURATION Normal Package (Top View) 2 3 4 5 6 7 8 9 10 11 12 13 B DQS0 /DQS0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ /DQS3 DQS3 C DQ4 DM0 VDDQ VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ VDDQ DM3 DQ27 D DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 E DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24 F DQ17 DQ16 VDDQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSSQ VDDQ DQ15 DQ14 G DQ19 DQ18 VDDQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSSQ VDDQ DQ13 DQ12 H DQS2 /DQS2 NC VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSSQ NC /DQS1 DQS1 J DQ20 DM2 VDDQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSSQ VDDQ DM1 DQ11 K DQ21 DQ22 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ10 L DQ23 A3 VDD VSS RFU2 VDD VDD RFU1 VSS VDD A4 DQ8 M VREF A2 A10 /RAS NC CKE NC ZQ /CS A9 A5 VREF N A0 A1 A11 BA0 /CAS CK /CK /WE BA1 A8/AP A6 A7 NOTE : 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. (M,13) VREF for CMD and ADDRESS 4. (M,2) VREF for Data input - 5 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC PIN CONFIGURATION Mirror Package (Top View) 2 3 4 5 6 7 8 9 10 11 12 13 B DQS3 /DQS3 VSSQ DQ28 DQ29 DQ31 DQ0 DQ2 DQ3 VSSQ /DQS0 DQS0 C DQ27 DM3 VDDQ VDDQ DQ30 VDDQ VDDQ DQ1 VDDQ VDDQ DM0 DQ4 D DQ25 DQ26 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ5 DQ6 E DQ24 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ7 F DQ14 DQ15 VDDQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSSQ VDDQ DQ16 DQ17 G DQ12 DQ13 VDDQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSSQ VDDQ DQ18 DQ19 H DQS1 /DQS1 NC VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSSQ NC /DQS2 DQS2 J DQ11 DM1 VDDQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSSQ VDDQ DM2 DQ20 K DQ10 DQ9 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ22 DQ21 L DQ8 A4 VDD VSS RFU1 VDD VDD RFU2 VSS VDD A3 DQ23 M VREF A5 A9 /CS ZQ NC CKE NC /RAS A10 A2 VREF N A7 A6 A8/AP BA1 /WE /CK CK /CAS BA0 A11 A1 A0 * Under consideration - 6 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function Input Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM0 ~DM3 Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM pins are input only, the DM loading matches the DQ and DQS loading. BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Input Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands. CK, CK A0 A11 DQ Input/ Data Input/ Output: Bi-directional data bus. Output Data Strobe: output with read data, input with write data for source synchronous operation.Edge-aligned with read data, centered in write data. DQS0~ DQS3 DQS0~ DQS3 Input/ Output NC/ RFU DQS Scheme Differential DQS per byte DQS0, DQS0 DQS0 for DQ0-DQ7 DQS1, DQS1 DQS1 for DQ8-DQ15 DQS2, DQS2 DQS2 for DQ16-DQ23 DQS3, DQS3 DQS3 for DQ24-DQ31 No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.8V ± 0.1V VSSQ Supply DQ Ground VDD Supply Power Supply: 2.5V ± 0.1V VSS Supply Ground VREF Supply Reference voltage: half Vddq , 2 Pins : (M,2) for Data input , (M,13) for CMD and ADDRESS ZQ input Resistor connection pin for On-die termination. The value of Resistor = 2 X (target value (Rterm) of termination resistance of DQ pin of each chip) - 7 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank) DQS , DQS Input Buffer CK, CK 32 Input DLL Input Buffer I/O Control Data Input Register Serial to parallel Bank Select LWE LDMi 128 1M x 32 32 Output Buffer 1M x 32 128 4-bit prefetch Sense AMP Row Decoder Refresh Counter Row Buffer ADDR Address Register iCK 1M x 32 x32 DQi 1M x 32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length LRAS LCBR Strobe Gen. Programming Register LCKE Output DLL DQS, DQS LWE LCAS LWCBR CK,CK LDMi Timing Register iCK CKE CS RAS CAS WE DMi * iCK : internal clock - 8 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC FUNTIONAL DESCRIPTION Simplified State Diagram Power Applied Power On DLL Enable Self Refresh Precharge PREALL REFS REFSX MRS EMRS MRS Auto Refresh REFA Idle CKEL CKEH Active Power Down ACT Precharge Power Down CKEH CKEL Row Active Read Write Write A Write Write Read A Read Read Read A Write A Read A PRE Write A PRE PRE PRE Read A Precharge PREALL Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge - 9 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Power-Up Sequence GDDR2 SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Power Up Sequence - Apply Power and Keep CKE at low state. (All other inputs may be undefined) - Apply VDD before VDDQ. - Apply VDDQ before VREF. - Start low frequency clock(100MHz) and maintain stable condition for minimum 200us. - The minimum of 200us after stable power and clock (CK, /CK), apply NOP and take CKE to be high. - Issue precharge command for all banks of the device ( tS/tH =0.5tCK). - Issue EMRS command to initialize DRAM with DLL OFF and On-die Termination OFF( tS/tH=0.5tCK) . BA1 BA0 A11 0 1 0 A10 A9 A8 X A7 A6 X A5 0 A4 X A3 A2 0 0 A1 Address Bus A0 Extended Mode Register X - Issue EMRS command to control DLL and decide on-die termination state. Within 100 clocks after issuing EMRS command for DLL on, stable high frequency clock should be supplied to DRAM. BA1 BA0 A11 0 1 0 A10 A9 A8 V A7 A6 V A5 1 A4 V A3 A2 V V A1 Address Bus A0 Extended Mode Register V (V=Valid value) - The additional 1ms clock cycles are required to lock the DLL and determine value of on-die termination after issuing EMRS command or supplying stable clock from a controller. Apply NOP during Locking DLL to protect invalid command. - Issue precharge command for all banks of the device. - Issue EMRS command - Issue at least 10 or more Auto refresh command to update the value of on-die termination. - Issue a MRS command to initialize the mode register. - Issue any command. Power up & Initialization Sequence CKE 200 us < 100tCK 1ms CK,CK low freq. (> 100Mhz) stable high freq. tRP tMRD tRFC 4 Clock min. tRFC ~ CMD tRP NOP Precharge all banks NOP EMRS1 NOP EMRS2 NOP Precharge all banks EMRS 1st Auto Refresh 10th Auto Refresh MRS Any Command * Minimum setup/hold time tIS, tIHmin = 0.5tCK at the Low frequency without DLL * Within 100 tCK after issuing EMRS2, PLL(DLL) of controller should be enabled. * During changing clock frequency, the changing rate should be smaller than 100ps/30tCK - 10 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of GDDR2 SDRAM. It programs CAS latency, addressing mode, test mode and various vendor specific options to make GDDR2 SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR2 SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum four clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is used for test mode. A9 ~ A11 are used for tWR. Refer to the table for specific codes for various addressing modes and CAS latencies. BA1 BA0 0 0 A11 A10 A9 tWR A8 A7 0 TM A6 A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length Address Bus Mode Register * Burst Length Test Mode A7 BA0 mode An ~ A0 0 Normal 0 MRS 1 Test 1 EMRS A2 A1 A0 0 1 0 Burst Length 4 Burst Type 0 tWR *1 A3 Burst Type 0 Sequential CAS Latency A11 A10 MRS Select A6 A5 A4 Latency 0 0 A9 0 Reserved 0 0 0 Reserved 0 0 1 Reserved 0 0 1 Reserved 0 1 0 3 0 1 0 Reserved 0 1 1 4 0 1 1 Reserved 1 0 0 5 1 0 0 Reserved 1 0 1 Reserved 1 0 1 5 1 1 0 Reserved 1 1 0 6 1 1 1 Reserved 1 1 1 7 *1. BL 4, Sequential Only - 11 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA0 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. Four clock cycles are required to complete the write operation in the extended mode register. 8 kinds of the output driver strength are supported by EMRS (A9, A8, A7) code. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific codes. BA1 BA0 0 1 A11 0 A10 ODT.R A9 A8 A7 Output driver strength A6 A5 A4 A3 DLL DQS A.L ODT control DLL *1 BA0 An ~ A0 0 MRS 1 EMRS A6 DLL 0 DLLOFF 1 DLLON DQS*2 A10 mode 0 ON 1 OFF A9 A8 A7 Ron[ohm] 0 0 0 60 0 0 1 55 0 1 0 50 0 1 1 45 1 0 0 40 1 0 1 35 1 1 0 30 1 1 1 25 Address Bus A0 ODT option Extended Mode Register On-die Termination option for CMD & ADDR*1 A1 A0 Value 0 0 OFF 0 1 X1 DQS 1 0 X2 Differential 1 1 X4 1 Single Additive Latency Output Driver Strength Option A1 0 A5 ODT of DQs @ RD A2 A4 Latency 0 0 1 1 OFF : On-die Termination of CMD and ADDR pins on DRAM is off X1 : On-die Termination value of CMD and ADD pins are same as the value of DQ X2 : 2 times of the value of DQ X4 : 4 times of the value of DQ On-Die Termination Mode *1 A3 A2 0 0 ODT OFF Value 0 1 ODT Cal. ON 1 0 Rterm=60 1 1 Rterm=120 *1. DLL control,ODT control,and ODT option command should be issued at low frequency clock(<100Mhz) with tIS/tIH=0.5tCK *2. When single DQS is selected, 4 /DQS pins should be connected to VREF. - 12 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC DQS 500MHz 450MHZ Differential DQS 400MHz Differential DQS Single DQS Differential DQS * To support existing DDR-I user , single DQS is supported under 400MHz by EMRS option, When single DQS is selected, 4 /DQS pins should be connected to VREF. Differntial DQS Timing (CL5, BL4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 13 14 15 16 17 18 19 20 CK, CK CMD WRITE READ DQS DQS DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 Single DQS Timing (CL5, BL4) 0 1 2 3 4 5 6 7 8 9 10 11 12 CK, CK CMD WRITE READ DQS DQS DQ Vref Level Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 - 13 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA0 and BA1 are used to select the desired bank. The row address A0 through A11 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the GDDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of (0,1) are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC), which is equal to tRAS + tRP. The minimum time interval between Bank Activate commands, Bank 0,1, 2, 3 (in any order), is the Bank to Bank delay time (tRRD). Bank Activate Command Cycle : CL=7, tRCD=9, AL=1, tRP=8, tRRD=5, tCCD=2, tRAS=19 0 1 2 3 4 5 8 Bank B Activate Post CAS Read A 9 13 14 15 16 17 18 19 24 27 Bank A Precharge Bank B Precharge Bank A Activate CK, CK tRRD = 5 CMD Bank A Activate Post CAS Read B Additive Latency tRP = 8 Additive Latency tRCD = 9 DQS tRAS = 19 CAS Latency Dout0 Dout1 Dou2 Dout3 DQ internal Read Command Start (Bank A) internal Read Command Start (Bank B) Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock’s rising edge. The WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). A new burst access must not interrupt the previous 4 bit burst operation. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles. Write Latency The Write Latency(WL) is always defined as AL(Additive Latency)+1 where Read Latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). - 14 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in GDDR2 SDRAM. In this operation, the GDDR2 SDRAM allows a CAS read or write command to be issued tRCDmin or 1 tCK earlier than tRCDmin after the RAS bank activate command. The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMRS. Examples of posted CAS operation Example 1 Read followed by a write to the same bank [AL = 1, tRCD = 9, CL = 7, RL = (AL + CL) = 8, WL = (AL + 1) = 2] 0 7 8 13 14 15 16 17 18 19 20 21 22 23 21 22 CK, CK CMD Active A-Bank Write A-Bank Read A-Bank tRL DQS tWL Dout0 Dout1 DQ Dou2 Dout3 Din0 Din1 Din2 Din3 tHZ tHZ > 1 tCK Example 2 Read followed by a write to the same bank [AL = 0, tRCD = 9, CL = 7, RL = (AL + CL) = 7, WL = (AL + 1) = 1] 0 1 8 9 14 15 16 17 18 19 20 CK, CK CMD Active A-Bank Read A-Bank Write A-Bank RL DQS tRCD tWL Dout0 Dout1 Dout2 Dout3 DQ - 15 - Din0 Din1 Din2 Din3 Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the Extended Mode Register Set (EMRS). Burst Read Operation: RL = 8 (AL = 1, CL = 7) 0 1 2 7 8 9 10 11 12 13 Posted CAS READ A NOP Post CAS Read A NOP NOP NOP NOP NOP NOP NOP CK, CK CMD DQS tDQSCK AL =1 CL = 7 RL = 8 DQs DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTA4 DOUTA5 DOUTA6 DOUTA7 internal Read Command Start (Bank A) Burst Read Operation: RL = 7 (AL = 0 and CL = 7) 0 1 2 Posted CAS READ A NOP Post CAS Read A 7 8 9 10 11 12 13 NOP NOP NOP NOP NOP NOP NOP CK, CK CMD NOP DQS tDQSCK CL = 7 RL = 7 DQs DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTA4 DOUTA5 DOUTA6 DOUTA7 internal Read Command Start (Bank A) - 16 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Burst Read followed by Burst Write : AL = 1, CL = 7, RL = 8, WL = (AL+1) = 2 0 1 6 7 8 9 10 Post CAS READ A NOP NOP NOP NOP NOP 11 12 13 NOP NOP NOP CK, CK CMD Post CAS Write A DQS RL =8 tHZ DQ’s DOUTA0 DOUTA1 DOUTA2 DINA0 DOUTA3 DINA1 DINA2 DINA3 WL = 2 tHZ > 1 tCK Seamless Burst Read Operation: CL = 7, AL = 1, RL = 8 0 1 2 NOP Post CAS READ A4 7 8 9 10 11 NOP NOP NOP NOP NOP CK, CK CMD Post CAS READ A0 NOP DQS AL = 1 CL =7 RL = 8 DQ’s DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTA4 DOUTA5 DOUTA6 The seamless burst read operation is supported by enabling a read command at every other clock. This operation is allowed regardless of same or different banks as long as the banks are activated. - 17 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Burst Write Operation The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by an Additive Latency(AL) plus one and is equal to (AL + 1). The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the clock and at the first falling edge of the clock. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the clock until the burst length of 4 is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR). Burst Write Operation : AL= 1, CL = 7, WL = 2, tWR = 5 0 1 2 3 4 NOP NOP NOP 5 6 9 CK, CK Posted CAS WRITE A CMD NOP NOP NOP Precharge DQS WL =2 DQ DINA0 DINA1 DINA2 DINA3 tWR = 5 Burst Write followed by Burst Read : RL = 7 (AL=0, CL=7), WL = 1, tCDLR = 4 1 0 2 3 7 14 15 16 NOP NOP NOP CK, CK Write to Read Latency = WL + 2 + t CDLR =7 CMD Post CAS WRITE A NOP NOP NOP NOP Post CAS READ A NOP NOP DQS CL = 7 tWL = 1 > = tCDLR DQ DINA0 DINA1 DINA2 DINA3 DOUTA0 DOUTA1 DOUTA2 DOUTA3 The minimum number of clock from the burst write command to the burst read command is WL+2+a write-toread-turn-around-time(tCDLR). - 18 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Seamless Burst Write Operation : AL = 1, CL = 7, WL = AL + 1 = 2 0 1 2 3 7 8 9 10 11 Post CAS WRITE A NOP Post CAS WRITE B NOP NOP NOP NOP NOP NOP DINA0 DINA2 CK, CK CMD DQS WL = 2 DQ’s DINA1 DINA3 DINB0 DINB1 DINB2 DINB3 The seamless burst write operation is supported by enabling a write command every other clock. This operation is allowed regardless of same or different banks as long as the banks are activated - 19 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A8, BA0 and BA1 are used to define which bank to precharge when the command is issued. Bank Selection for Precharge by Address Bits A8 BA1 BA0 Precharged Bank(s) LOW LOW LOW Bank 0 only LOW LOW HIGH Bank 1 only LOW HIGH LOW Bank 2 only LOW HIGH HIGH Bank 3 only HIGH DON’T CARE DON’T CARE All Banks 0 ~ 3 Burst Read Operation Followed by Precharge For the earliest possible precharge, the precharge command may be issued on the rising edge which is CAS latency (CL) clock cycles before the end of the read burst. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied. Burst Read Operation Followed by Precharge: RL = 7 (AL=0, CL=7), tRP= 8 0 2 3 4 5 6 7 Post CAS READ A Precharge NOP NOP NOP NOP NOP 8 9 10 11 CK, CK CMD NOP NOP Bank A Active NOP DQS > = tRP CL =7 DQ DOUTA0 DOUTA1 DOUTA2 - 20 - DOUTA3 Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Burst Read Operation Followed by Precharge: RL = 8 (AL=1, CL=7, tRP =8) 0 3 Posted CAS READ A Precharge A 7 8 9 10 11 12 13 CK, CK CMD NOP NOP NOP Bank A Activate NOP NOP NOP DQS > = tRP RL = 8 DQ’s DOUTA0 DOUTA1 DOUTA2 DOUTA3 Burst Write followed by Precharge For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay, as GDDR2 SDRAM does not support any burst interrupt operation. Burst Write followed by Precharge: AL = 1, CL = 7, WL = AL + 1 = 2, tWR = 5 0 1 2 3 4 5 6 Posted CAS WRITE A NOP NOP NOP NOP NOP 9 CK, CK CMD NOP NOP Precharge A DQS WL = 2 DQ’s tWR = 5 DINA0 DINA1 DINA2 DINA3 - 21 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC DM FUNCTION The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle. When the Data Mask is activated (DM high) during write operation the write data is masked immediately (DM to Data-mask Latency is zero). DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge. 0 1 2 3 4 5 6 Posted CAS WRITE A NOP NOP NOP NOP NOP 9 CK, CK CMD NOP NOP Precharge A DQS tWR = 5 WL = 2 DQ’s DINA0 DINA1 DINA2 DINA3 DM masked by DM=H Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the GDDR2 SDRAM, the CAS timing accepts one extra address, column address A8, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A8 is low when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A8 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. - 22 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Burst Read with Auto Precharge If A8 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The GDDR2 SDRAM starts an Auto Precharge operation on the rising edge which is (AL + BL/2)cycles later from the read with Auto Precharge command, when tRAS(min) is satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto Precharge operation will be delayed until tRAS(min) is satisfied. A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. When the Read with Auto-Precharge command is issued, new command (Read, Read with Auto Precharge or precharge) of same bank can be asserted tCCD=2 clock cycles later. Burst Read with Auto Precharge Followed by Same Bank Activation : RL = 8 (AL = 1, CL = 7, internal tRP = 8) 0 3 7 8 9 10 11 12 NOP NOP NOP NOP Bank A Activate NOP CK, CK CMD A8 = 1 Post CAS READ A NOP NOP NOP Auto Precharge Begins DQS > = tRP RL = 8 DQ’s DOUTA0 DOUTA1 DOUTA2 DOUTA3 Burst Read with Auto Precharge (AL=0) For same bank For different bank Asserted command 1 2 3 4 1 2 3 4 READ Illegal Legal Illegal Illegal Illegal Legal Legal Legal READ with Auto Precharge Illegal Legal Illegal Illegal Illegal Legal Legal Legal Active Illegal Illegal Illegal Illegal Legal Legal Legal Legal Precharge Illegal Legal Illegal Illegal Legal Legal Legal Legal *When AL(Additive Latency) is 1, a precharge command for same bank can be issued at 3th cycle only and others are same with AL=0. - 23 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Burst Write with Auto-Precharge If A8 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The GDDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). Interruption of the Write with Auto-Precharge function is prohibited. Active command of same bank can be issued WL+tWR+tRP+BL/2 cycles later from the Write with Auto-Precharge command. The bank undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. Burst Write with Auto-Precharge : AL = 0, WL = 1, tWR = 5, tRP=8(for the same bank) 1 0 2 3 4 NOP NOP 7 8 9 16 CK, CK A8 = 1 CMD Post CAS WRITE A NOP NOP NOP NOP Bank A Active NOP Auto Precharge Begins DQS > = tWR WL=1 DQs DINA0 DINA1 DINA2 > = tRP DINA3 Burst Write with Auto-Precharge (AL=0) For same bank For different bank Asserted command 1~7 8 9 ~ 15 16 1 2~6 7 WRITE Illegal Illegal Illegal Illegal Illegal Legal Legal WRITE with Auto Precharge Illegal Illegal Illegal Illegal Illegal Legal Legal READ Illegal Illegal Illegal Illegal Illegal Illegal Legal READ with Auto Precharge Illegal Illegal Illegal Illegal Illegal Illegal Legal Active Illegal Illegal Illegal Legal Legal Legal Legal Precharge Illegal Illegal Illegal Illegal Legal Legal Legal All Bank Precharge Illegal Legal Legal Legal - *When AL(Additive Latency) is 1, a active command for same bank can be issued from 17th cycle , a READ or READ with Auto Precharge command for different bank can be issued from 8th cycle and others are same with AL=0. * All Bank Precharge command can be issued from 8th cycle. - 24 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Automatic Refresh Command (CAS Before RAS Refresh) When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the GDDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the GDDR2 SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the Auto Refresh cycle time (tRFC). CK, CK High CKE CMD > = tRFC > = tRP Precharge NOP Bank Activate CBR NOP NOP Self Refresh Command The GDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the Self Refresh Command is registered, CKE must be held low to keep the device in Self Refresh mode and NOP command should be issued or CS should be held high to ensure stable self refresh operation for next four cycles after the Self Refresh Command. When the GDDR2 SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. After CKE is brought high, an internal timer is started to insure CKE is held high for approximately 10ns before registering the Self Refresh exit command. The purpose of this circuit is to filter out noise glitches on the CKE input which may cause the GDDR2 SDRAM to erroneously exit Self Refresh operation. Once the Self Refresh exit command is registered, a delay equal or longer than the tXSA (>20000 tck) must be satisfied before any command can be issued to the device. CKE must remain high for the entire Self Refresh exit period (tXSA > 20000tCK) and commands must be gated off with CS held high. Alternatively, NOP commands may be registered on each positive clock edge during the Self Refresh exit interval. (See Figure.) CK, CK tXSA (> 20000tCK) CKE > = 4clk CMD Self Refresh NOP NOP ANY Command *After self refresh entry, NOP or chip deselect command should be issued during more than 4 cycles and chip deselet command should be issued for tXSA after self refresh exit. - 25 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Power-Down Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. During 4 cycles after power down mode issued, NOP should be issued or CS must be held high. In Power Down mode, CKE Low and a stable clock signal must be maintained at the inputs of the GDDR2 SDRAM, and all other input signals are “Don’t Care” except first 4 cycles after power down mode issued. Power-down duration is limited by the refresh requirements of the device. The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or CS hold high). A valid, executable command may be applied four clock cycles later. Power Down CK, CK tIS CKE CMD tIS 4tck VALID NOP*1 NOP No column access in progress NOP NOP NOP NOP VALID Exit power down mode Enter Power Down mode ( Read or Write operation must not be in progress) Don’t Care *1. NOP or CS held high should be issued more than 4 cycles. *CL + 2tCK after read or CL after last data in, a power-down command can be issued. Burst Interruption Interruption of a burst read or write cycle is prohibited. No Operation Command The No Operation Command should be used in cases when the GDDR2 SDRAM is in an idle or a wait state. The purpose of the No Operation Command is to prevent the GDDR2 SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high at the rising edge of the clock, the RAS, CAS, and WE signals become don’t cares. - 26 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC On-Die Termination All pins except ZQ, CKE Pins adopt on-die termination to improve signal integrity of channel. The On-Die Termination should be controlled by EMRS command at low frequency clock (<100Mhz). The On-Die Termination control command should be issued before issuing DLLON command by EMRS or simultaneously to guarantee stable channel condition of /CK and CK pins. If A3, A2 = 0, 0, the On-Die Termination of all pins will be deactivated. If A3, A2 = 0, 1, the On-Die Termination will be self-calibrated by detecting the external Resistor on ZQ pin. If A3, A2 = 1, 0, the value of the On-Die Termination of CK, /CK, 32 DQ’s, 4 DM’s, 4 /DQS’s and 4DQS pins will be the fixed value, 60ohm. If A3, A2 = 1, 1, the value of the On-Die Termination of CK, /CK, 32 DQ’s, 4 DM’s, 4 /DQS’s and 4DQS pins will be the fixed value,120ohm. If A3, A2 = 0, 1 is issued by EMRS, the value of the on-die termination of each pin is determined by monitoring the value of a external resistor which is connected between ZQ pin and VSSQ, and updated every CBR refresh cycle to compensate variation of voltage and temperature. The value of On-Die Termination of CMD and ADD (/RAS, /CAS, /WE, /CS, BA0, BA1 and A0 ~ A11) pins of each DRAM depend on EMRS code (A1, A0). If A1, A0 = 0, 0 , the On-die Termination of CMD and ADD pins will be deactivated. If A1, A0 = 0, 1, the value of the On-die Termination of CMD and ADD pins will be same value as the value of DQ pins. If A1, A0 = 1, 0, the value of the On-Die Termination of CMD and ADD pins will be two times of the value of DQ pins. If A1, A0 = 1, 1, the value of the On-Die Termination of CMD and ADD pins will be four times of the value of DQ pins. The On-Die Termination for one bank system with self-calibration code (A3, A2 = 0, 1) The value of external resistor (Rref) at external one bank system is 2 times of target termination value of DQ’s on channel (Rterm). Then the value of On-Die Termination of CK, /CK, 32 DQ’s, 4 DM’s, 4 /DQS’s and 4DQS pins is half value of the external resistor. The value of On-Die Termination of CMD and ADD ( /RAS, /CAS, /WE, /CS, BA0, BA1 and A0 ~ A11) pins of each DRAM depend on EMRS code (A2, A0). The following figure shows the typical external one bank system having on-die termination. Block Diagram of 1 Bank System Front Side DRAMs CK,/CK ADD /RAS,/CAS,/WE,/CS DM’s, DQ’S, DQS’s,/DQS’s CK,/CK CK,/CK ZQ ADD Rref=2 X Rterm /RAS,/CAS,/WE,/CS DM’s, DQ’S, DQS’s,/DQS’s CK,/CK VSSQ ZQ ADD 2XRterm Controller /RAS,/CAS,/WE,/CS DM’s, DQ’S, DQS’s,/DQS’s CK,/CK /CS /RAS,/CAS,/WE DM’s, DQ’S, DQS’s,/DQS’s CK,/CK VSSQ DM’s, DQ’S, DQS’s,/DQS’s CK,/CK ZQ ADD 2XRterm /RAS,/CAS,/WE,/CS DM’s, DQ’S, DQS’s,/DQS’s CK,/CK VSSQ ZQ ADD 2XRterm /RAS,/CAS,/WE,/CS DM’s, DQ’S, DQS’s,/DQS’s DM’s, DQ’S, DQS’s,/DQS’s - 27 - VSSQ Where Rterm is the termination value on charnnel Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC The On-die Termination on/off status on DRAM is in accompany with DRAM operation mode. Power consumption by On-die termination can be reduced by issuing power down mode. On-Die Termination (ODT) Status of 1 Bank System Mode Pin ODT of DRAM Self_refresh All OFF CK, /CK ON Other pins OFF All ON Power Down Active All banks idle A10=1 READ A10=0 CK, /CK, ADD’s, CMD ON DQ’s, DQS’s, /DQS’s, DM’s ON CK, /CK, ADD’s, CMD, DM,s ON DQ’s, DQS’s, /DQS’s OFF CK, /CK, ADD’s, CMD, DM,s ON DQ’s, DQS’s, /DQS’s ON * A10 in EMRS code is used for On-Die Termination of DQ’s off when Read data comes out - 28 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC The On-die Termination for external two bank system with self-calibration code (A3, A2 = 0, 1) The external resistor (Rref) is equal to 2X the number of shared DRAM’s on one channel X target termination value of DQ channel. The following figure is represented the typical two bank system having on-die termination. 4 DRAM’s share one channel for CMD and ADD pins and 2 DRAM’s share one channel for DQ’s and CLK pins. The external resistor (Rref) is 4 times of target termination value on channel. The On-die Termination value of CK, /CK, 32 DQ’s, 4 DM’s, 4 /DQS’s and 4DQS pins on channel is half value of the external resistor (Rref). Block Diagram of 2 Banks System Front Side DRAM’s CK, /CK ADD /RAS, /CAS, /WE, /CS DM’s, DQ’s, DQS’s, /DQS’s ADD /RAS, /CAS, /WE, /CS DM’s, DQ’s, DQS’s, /DQS’s ZQ 4 X Rterm CK, /CK CK, /CK Controller Back Side DRAM’s CK, /CK CK, /CK CK, /CK ADD /RAS, /CAS, /WE, /CS DM’s, DQ’s, DQS’s, /DQS’s DM’s, DQ’s, DQS’s, /DQS’s ZQ 4 X Rterm CK, /CK CK, /CK /CS DM’s, DQ’s, DQS’s, /DQS’s ZQ 4 X Rterm CK, /CK CK, /CK DM’s, DQ’s, DQS’s, /DQS’s ZQ 4 X Rterm ZQ 4 X Rterm VSSQ ZQ ADD /RAS, /CAS, /WE, /CS DM’s, DQ’s, DQS’s, /DQS’s CK, /CK ADD /RAS, /CAS, /WE, /CS DM’s, DQ’s, DQS’s, /DQS’s Rref = 4 X Rterm VSSQ ADD /RAS, /CAS, /WE, /CS DM’s, DQ’s, DQS’s, /DQS’s CK, /CK ADD /RAS, /CAS, /WE, /CS DM’s, DQ’s, DQS’s, /DQS’s /RAS, /CAS, /WE, /CS ZQ ADD /RAS, /CAS, /WE, /CS DM’s, DQ’s, DQS’s, /DQS’s 4 X Rterm VSSQ ZQ ADD /RAS, /CAS, /WE, /CS DM’s, DQ’s, DQS’s, /DQS’s 4 X Rterm VSSQ Self-refresh and power down mode in two bank system should be issued for all DRAM’s at the same time to keep suitable On-die termination condition on channel. . Mode DRAM Pin M1 Self_refresh Self_refresh All Self_refresh Other States All Power down Power down Power down Remarks M2 M1 M2 OFF OFF *1 Illegal CK,/CK ON ON Other pins OFF OFF Other States *1 Illegal CK, /CK, ADD’s, CMD ON ON DQ’s, DQS’s, /DQS’s, DM’s ON ON CK, /CK, ADD’s, CMD ON ON DQ’s, DQS’s, /DQS’s, DM’s ON OFF CK, /CK, ADD’s, CMD ON ON DQ’s, DQS’s, /DQS’s, DM’s ON ON CK, /CK, ADD’s, CMD ON ON DQ’s, DQS’s, /DQS’s, DM’s ON OFF Active All Banks idle A10=1 Read A10=0 A10=1 Active Read CK, /CK, ADD’s, CMD ON ON DQ’s, DQS’s, /DQS’s, DM’s ON ON A10=0 1. With these case, the system couldn’t have suitable Rterm. Because the On-Die termination value on channel is two times than the target value. - 29 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC 4. Command Truth Table. CKE Function CS RAS CAS WE DM X L L L L X BA0 = 0 and MRS OP Code 1 H X L L L L X BA0 = 1 and EMRS OP Code 1 Auto (CBR) Refresh H H L L L H X X X X X 1 Entry Self Refresh H L L L L H X X X X X 1 L H H X X X X X X X X 1 L H L H H H X X X X X Single Bank Precharge H X L L H L X BA X L X 1,2 Precharge all Banks H X L L H L X X X H X 1 Bank Activate H X L L H H X BA Write H X L H L L X BA Write with Auto Precharge H X L H L L X Read H X L H L H Read with Auto-Precharge H X L H L DM H X X X H X L H X H Previous Cycle Current Cycle Mode Register Set H Extended Mode Register Set BA0/BA1 A11 - A9 A8 A7 - A0 Notes Exit Self Refresh Row Address 1,2 X L Column 1,2,3, BA X H Column 1,2,3, X BA X L Column 1,2,3 H X BA X H Column 1,2,3 X X DM X X X X 6 H H H X X X X X 1 H X X X X X X X X 1 L H X X X X X X X X 1,4,5 H L L H H H X X X X X L H H X X X X X X X X L H L H H H X X X X X No Operation Power Down Mode Entry 1,4,5 Power Down Mode Exit All of the GDDR2 SDRAM operations are defined by states of CS, WE, RAS, and CAS at the positive rising edge of the clock. Bank Select (BA0,1), determine which bank is to be operated upon. Burst read or write cycle may not be terminated. The Power Down Mode does not perform any refresh operations, therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. Four clock delay is required for mode entry and exit. 5. If CS is low, then when CKE returns high, no command is registered into the chip for one clock cycle. 6. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 1. 2. 3. 4. (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) - 30 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC 5. Clock Enable (CKE) Truth Table CKE Current State Self Refresh Power Down All Banks Idle Any State other than listed above Command Action Notes Previous Cycle Current Cycle CS RAS CAS WE BA1, BA0, A11 - A0 H X X X X X X L H H X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X Exit Self Refresh with No Operation 2 L H L ILLEGAL 2 L L X X X X X Maintain Self Refresh H X X X X X X INVALID 1 L H H X X X X Power Down mode exit, all banks idle 2 L H L H H H X Exit Power Down mode with No Operation 2 L H L ILLEGAL 2 L L X X X X H H H X X X H H L H L H H L L H L L L L H H X X H L X L H L L Command Address Command Address Command X X X Address X Command except selfrefresh command INVALID 1 Maintain Power Down Mode Device Deselect 3 Refer to the Current State Truth Table 3 Power Down X ILLEGAL H X Entry Self Refresh X X X Refer to operations in the Current State Truth Table X X X X Power Down X X X X X Power Down X X X X X Power Down 4 5 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied before any command other than self refresh exit. 3. The inputs (BA1, BA0, A11 - A0) depend on the command that is issued. See the Current State Truth Table for more information. 4. The Auto Refresh, Self Refresh Mode, and the Mode Register Set modes can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table. - 31 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature Voltage on any pin relative to Vss TSTG -55 ~ +150 °C Power dissipation PD 4.5 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_18 In/Out) Recommended operating conditions (Voltage referenced to VSS=0V, Tj=0 to 100°C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage VDD 2.4 2.5 2.6 V 1 Output Supply voltage VDDQ 1.7 1.8 1.9 V 1 Reference voltage VREF 0.49*VDDQ - 0.51*VDDQ V 2 DC Input logic high voltage VIH (DC) VREF+0.125 - VDDQ+0.30 V 4 DC Input logic low voltage VIL (DC) -0.30 - VREF-0.125 V 5 AC Input logic high voltage VIH(AC) VREF+0.25 - - V AC Input logic low voltage VIL(AC) - - VREF-0.25 V Output logic high voltage VOH Vtt+0.4 - - V 6 Output logic low voltage VOL - - Vtt-0.4 V 6 Input leakage current IIL -5 - 5 uA 7 Output leakage current IOL -5 - 5 uA 7 Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. Output logic high voltage and low voltage is depend on channel condition.(Ract , Ron) 7. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V - 32 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, Tj=0 to 100°C) Version Parameter Symbol Test Condition Unit Note -20 -22 -25 Operating Current (One Bank Active) ICC1 Burst Lenth=4 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 590 540 500 mA Precharge Standby Current in Power-down mode ICC2P CKE ≤ VIL(max), tCC= tCC(min) 110 100 95 mA Precharge Standby Current in Non Power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) 230 210 190 mA Active Standby Current power-down mode ICC3P CKE ≤ VIL(max), tCC= tCC(min) 110 100 95 mA Active Standby Current in in Non Power-down mode ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) 510 470 430 mA Operating Current ( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. 1200 1100 990 mA Refresh Current ICC5 tRC≥ tRFC 370 350 330 mA Self Refresh Current ICC6 CKE ≤ 0.2V Operating Current (4Bank interleaving) ICC7 Burst Lenth=4 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 7 1400 1 2 mA 1300 1180 mA Note : 1. Measured with outputs open & On-Die termination off. 2. Refresh period is 16ms. AC INPUT OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS=0V, VDD=2.5V ± 0.1V, VDDQ=1.8V ± 0.1V, Tj=0 to 100 °C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ VIH VREF+0.25 - - V 1 Input Low (Logic 0) Voltage; DQ VIL - - VREF-0.25 V 2 Clock Input Differential Voltage ; CK and CK VID 0.5 - VDDQ+0.6 V 3 Clock Input Crossing Point Voltage ; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V 4 Note : 1. VIH(Max) = 4.2V. The overshoot voltage duration is < 3ns at VDD. VIH level should be met at the pin of DRAM when ODT=ON. 2. VIL(Min) = -1.5V. The undershoot voltage duration is < 3ns at VSS. VIL level should be met at the pin of DRAM when ODT=ON. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same VDDQ DRAM ODT of DRAM Controller Input level should be measured at this point - 33 - VSSQ Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC AC OPERATING TEST CONDITIONS (VDD=2.5V±0.1V, Tj= 0 to 100 °C) Parameter Value Unit Input reference voltage for CK(for single) 0.50*VDDQ V CK and CK signal maximum peak swing 1.5 V CK signal minimum slew rate 1.0 V/ns VREF+0.25/VREF-0.25 V VREF V Output timing measurement reference level 1/2 VDDQ V Output load condition See Fig.1 Input Levels(VIH/VIL) Input timing measurement reference level Output Z0=60Ω Note VREF =0.5*VDDQ CLOAD=10pF (Fig. 1) Output Load Circuit CAPACITANCE (VDD=2.5V, TA= 25°C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance ( CK, CK ) CIN1 3.0 5 pF Input capacitance (A0~A10, BA0~BA1) CIN2 3.0 5 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) CIN3 3.0 5 pF Data & DQS input/output capacitance(DQ0~DQ31) COUT 3.0 5 pF Input capacitance(DM0 ~ DM3) CIN4 3.0 5 pF - 34 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC AC CHARACTERISTICS Parameter CL=7 CL=6 CL=5 CK cycle time -20 (GF1000) Min Max 2.0 4.0 0.45 0.55 0.45 0.55 -0.35 0.35 -0.225 0.225 0.85 1.15 0.35 0.65 0.45 0.55 0.45 0.55 0.5 0.5 - Symbol tCK CK high width CK low width DQS out access time from CK Data strobe edge to Dout edge Read preamble Read postamble DQS in/out high level DQS in/out low level Address and Control input setup Address and Control input hold Write command to first DQS latching transition Write preamble setup time Write postamble Write preamble DQ_in and DM setup time to DQS DQ_in and DM hold time to DQS Clock half period Data output hold time from DQS Jitter over 1-6 clock cycles of CK Cycle to Cycle duty cycle error Rise and fall times of CK tCH tCL tDQSCK tDQSQ tRPRE tRPST tDQSH tDQSL tIS tIH -22 (GF900) Min Max 2.22 4.0 0.45 0.55 0.45 0.55 -0.45 0.45 -0.25 0.25 0.88 1.12 0.38 0.62 0.45 0.55 0.45 0.55 0.55 0.55 - tDQSS WL - 0.15 WL + 0.15 tWPRES tWPST tWPRE tDS tDH tHP tQH tJ *1 tDC,ERR tR, tF 0 0.4 0.35 0.25 0.25 tCL/H min tHP-0.225 - 0.6 50 50 400 -25 (GF800) Min Max 2.5 4.0 0.45 0.55 0.45 0.55 -0.45 0.45 -0.28 0.28 0.9 1.1 0.4 0.6 0.45 0.55 0.45 0.55 0.6 0.6 - Unit ns ns ns tCK tCK ns ns tCK tCK tCK tCK ns ns WL - 0.15 WL + 0.15 WL - 0.15 WL + 0.15 tCK 0 0.4 0.35 0.27 0.27 tCL/H min tHP-0.25 - ps tCK tCK ns ns ns ns ps ps ps 0.6 55 55 450 0 0.4 0.35 0.3 0.3 tCL/H min tHP-0.28 - 0.6 65 65 500 1. The cycle to cycle jitter and 2~6 cycle short term jitter. Simplified Timing @ BL=4, CL=7, AL=0 0 1 2 6 7 8 9 10 11 12 CK, CK CMD Post CAS READ A NOP NOP NOP NOP NOP NOP Post CAS NOP Write A NOP DQS RL = 7 DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 DIN A0 DIN A1 DIN A2 DIN A3 WL = 1 WDQS - 35 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Note 1 : - The JEDEC DDR-II specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL7, BL4) tHP 0 1 6 7 8 9 CK, CK CS DQS tDQSQ(max) tQH tDQSQ(max) Da0 DQ COMMAND Da1 Da2 Da3 READA - 36 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC AC CHARACTERISTICS (I) Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to any command Power down exit time Refresh interval time Symbol tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tWR tCDLR tCCD tMRD tDAL tXSA tPDEX tREF -20 (GF1000) Min Max 22 27 15 100K 8 5 7 5 5 4 2 4 - -22 (GF900) Min Max 21 25 14 100K 8 5 7 5 5 4 2 4 - -25 (GF800) Min Max 18 22 12 100K 7 4 6 4 4 4 2 4 - Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK 12 - 12 - 10 - tCK 20000 4tCK+tIS 7.8 - 20000 4tCK+tIS 7.8 - 20000 4tCK+tIS 7.8 - tCK ns us Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM - 37 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC PACKAGE DIMENSIONS (FBGA) A1 INDEX MARK 13.0 13.0 <Top View> 0.8x11=8.8 A1 INDEX MARK 0.10 Max 0.8 B C D E F G H J K L M N 0.40 0.8x11=8.8 0.45 ± 0.05 0.8 13 12 11 10 9 8 7 6 5 4 3 2 0.25 ± 0.05 0.40 1.40 Max <Bottom View> Unit : mm - 38 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC IBIS: I/V Characteristics for Input and Output Buffers The termination resistor of the controller must be set to a appropriate value to satisfy output voltage level if the ODT of DRAM is on. 30 ohm Driver @ ODT OFF 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 30 ohm@ODT OFF variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 35 Maximum 30 Iout(mA) 25 Typical 20 15 Minimum 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Figure a : Pulldown Charateristics Vout(V) 3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 30 ohm@ODT OFF variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. 0 -5 Iout(mA) -10 -15 Minumum -20 Typical -25 -30 Maximum -35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Vout(V) Figure b : PulluP Charateristics 5. The 30 ohm@ODT OFF variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 30 ohm@ODT OFF variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from 0 to VDDQ/2 - 39 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Minimum Maximum Typical 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 4.4 3.0 6.3 -3.6 -2.5 -4.9 Minimum Maximum 0.2 8.1 5.5 11.8 -6.9 -4.6 -9.3 0.3 11.2 7.6 16.4 -9.7 -6.6 -13.3 0.4 13.8 9.3 20.4 -12.2 -8.2 -17.0 0.5 15.9 10.6 23.5 -14.3 -9.6 -20.1 0.6 17.4 11.5 25.9 -16.1 -10.7 -22.7 0.7 18.4 12.1 27.5 -17.4 -11.6 -24.6 0.8 19.0 12.4 28.4 -18.4 -12.3 -26.0 0.9 19.4 12.6 29.0 -19.1 -12.8 -27.1 1.0 19.7 12.8 29.3 -19.7 -13.2 -28.0 1.1 19.8 12.9 29.5 -20.3 -13.6 -28.7 1.2 20.0 13.0 29.7 -20.7 -13.9 -29.3 1.3 20.1 13.1 29.9 -21.1 -14.2 -29.8 1.4 20.2 13.1 30.0 -21.5 -14.5 -30.3 1.5 20.2 13.2 30.1 -21.8 -14.7 -30.7 1.6 20.3 13.2 30.2 -22.1 -14.9 -31.1 1.7 20.4 13.3 30.3 -22.4 -15.1 -31.4 1.8 20.4 13.3 30.3 -22.6 -15.3 -31.8 1.9 20.5 13.5 30.4 -22.9 -15.5 -32.1 Temperature (Tj) Typical Minimum Maximum 50 °C 100 °C 0 °C Vdd/Vddq Typical Minimum Maximum 2.5V 2.4V 2.6V The above characteristics are specified under best, worst and normal process variation/conditions - 40 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC 30 ohm Driver @ ODT 60 ohm Fix. 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 30 ohm@ODT 60 ohm Fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 60 Maximum 50 Iout(mA) 40 Typical 30 Minimum 20 10 0 -10 -20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Figure a : Pulldown Charateristics Vout(V) 3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 30 ohm@ODT 60 ohm Fix variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. 20 10 Iout(mA) 0 -10 -20 -30 Minumum -40 Typical -50 Maximum -60 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Vout(V) Figure b : PulluP Charateristics 5. The 30 ohm@ODT 60 ohm fix variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 30 ohm@ODT 60 ohm fix variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from 0 to VDDQ/2 - 41 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Minimum Maximum Typical Minimum Maximum 0.0 -14.4 -11.5 -17.1 14.9 11.9 18.0 0.1 -8.5 -7.1 -9.0 9.7 8.1 11.4 0.2 -3.2 -3.3 -1.8 4.8 4.6 5.1 0.3 1.6 0.2 4.7 0.4 1.3 -0.8 0.4 5.8 3.3 10.4 -3.7 -1.7 -6.2 0.5 9.5 5.9 15.4 -7.4 -4.4 -11.2 0.6 12.7 8.2 19.7 -10.8 -6.9 -15.6 0.7 15.3 10.2 23.1 -13.7 -9.2 -19.4 0.8 17.5 11.9 25.9 -16.4 -11.2 -22.6 0.9 19.6 13.5 28.3 -18.8 -13.2 -25.6 1.0 21.5 15.1 30.5 -21.0 -15.0 -28.3 1.1 23.3 16.6 32.6 -23.2 -16.8 -30.9 1.2 25.1 18.1 34.7 -25.3 -18.5 -33.4 1.3 26.8 19.6 36.7 -27.3 -20.2 -35.8 1.4 28.6 21.0 38.7 -29.4 -21.8 -38.1 1.5 30.3 22.4 40.7 -31.3 -23.5 -40.4 1.6 32.0 23.9 42.7 -33.3 -25.1 -42.7 1.7 33.7 25.3 44.6 -35.2 -26.6 -44.9 1.8 35.4 26.7 46.6 -37.1 -28.2 -47.1 1.9 37.1 28.1 48.5 -39.0 -29.8 -49.3 Temperature (Tj) Typical Minimum Maximum 50 °C 100 °C 0 °C Vdd/Vddq Typical Minimum Maximum 2.5V 2.4V 2.6V The above characteristics are specified under best, worst and normal process variation/conditions - 42 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC 30 ohm Driver @ODT 120 ohm Fix. 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 30 ohm@ODT 120 ohm Fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 50 Maximum Iout(mA) 40 Typical 30 Minimum 20 10 0 -10 0 0.2 0.4 0.6 0.8 1 1.2 Figure a : Pulldown Charateristics 1.4 1.6 1.8 Vout(V) 3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 30 ohm@ODT 120 ohm Fix variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. 10 0 Iout(mA) -10 -20 Minumum -30 Typical -40 Maximum -50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Vout(V) Figure b : PulluP Charateristics 5. The 30 ohm@ODT 120 ohm fix variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 30 ohm@ODT 120 ohm fix variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from 0 to VDDQ/2 - 43 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Minimum Maximum Typical Minimum Maximum 0.0 -7.2 -5.8 -8.6 7.6 6.1 9.1 0.1 -2.1 -2.1 -1.4 3.1 2.9 3.4 0.2 2.5 1.1 5.0 -0.9 0.1 -2.0 0.3 6.4 3.9 10.6 -4.6 -2.5 -6.9 0.4 9.8 6.3 15.4 -7.9 -4.9 -11.5 0.5 12.7 8.3 19.5 -10.8 -6.9 -15.5 0.6 15.1 9.9 22.8 -13.4 -8.8 -19.1 0.7 16.9 11.2 25.3 -15.5 -10.3 -21.9 0.8 18.3 12.2 27.2 -17.3 -11.7 -24.3 0.9 19.5 13.1 28.7 -18.9 -12.9 -26.3 1.0 20.6 14.0 30.0 -20.4 -14.1 -28.1 1.1 21.6 14.8 31.2 -21.7 -15.2 -29.7 1.2 22.6 15.6 32.3 -23.0 -16.2 -31.3 1.3 23.5 16.4 33.4 -24.2 -17.2 -32.7 1.4 24.5 17.1 34.5 -25.4 -18.1 -34.2 1.5 25.4 17.9 35.5 -26.6 -19.1 -35.5 1.6 26.3 18.6 36.5 -27.7 -20.0 -36.9 1.7 27.1 19.4 37.6 -28.8 -20.9 -38.2 1.8 28.0 20.1 38.6 -29.9 -21.8 -39.5 1.9 28.9 20.9 39.6 -31.0 -22.7 -40.7 Temperature (Tj) Typical Minimum Maximum 50 °C 100 °C 0 °C Vdd/Vddq Typical Minimum Maximum 2.5V 2.4V 2.6V The above characteristics are specified under best, worst and normal process variation/conditions - 44 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC 45 ohm @ ODT OFF 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 45 ohm@ ODT OFF variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 35 Maximum 30 Iout(mA) 25 Typical 20 Minimum 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Figure a : Pulldown Charateristics Vout(V) 3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 45 ohm@ODT OFF variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. 0 -5 Iout(mA) -10 -15 Minumum -20 Typical -25 -30 Maximum -35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Vout(V) Figure b : PulluP Charateristics 5. The 45 ohm@ODT OFF variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 45 ohm@ODT OFF variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from 0 to VDDQ/2 - 45 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Minimum Maximum Typical 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 2.8 1.9 4.0 -2.2 -1.5 -3.0 Minimum Maximum 0.2 5.2 3.5 7.5 -4.2 -2.8 -5.7 0.3 7.2 4.9 10.5 -6.0 -4.0 -8.2 0.4 8.8 5.9 13.0 -7.5 -5.0 -10.4 0.5 10.1 6.8 15.0 -8.8 -5.9 -12.3 0.6 11.1 7.3 16.5 -9.8 -6.6 -13.9 0.7 11.7 7.7 17.5 -10.6 -7.1 -15.1 0.8 12.1 7.9 18.1 -11.2 -7.5 -15.9 0.9 12.4 8.0 18.4 -11.7 -7.8 -16.6 1.0 12.5 8.1 18.7 -12.1 -8.1 -17.1 1.1 12.6 8.2 18.8 -12.4 -8.3 -17.5 1.2 12.7 8.3 18.9 -12.7 -8.5 -17.9 1.3 12.8 8.3 19.0 -12.9 -8.7 -18.2 1.4 12.8 8.4 19.1 -13.1 -8.8 -18.5 1.5 12.9 8.4 19.2 -13.3 -9.0 -18.8 1.6 12.9 8.4 19.2 -13.5 -9.1 -19.0 1.7 13.0 8.5 19.3 -13.7 -9.2 -19.2 1.8 13.0 8.5 19.3 -13.8 -9.4 -19.4 1.9 13.1 8.6 19.4 -14.0 -9.5 -19.6 Temperature (Tj) Typical Minimum Maximum 50 °C 100 °C 0 °C Vdd/Vddq Typical Minimum Maximum 2.5V 2.4V 2.6V The above characteristics are specified under best, worst and normal process variation/conditions - 46 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC 45 ohm Driver @ODT 120 ohm Fix. 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 45 ohm@ODT 120 ohm Fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 35 30 Maximum Iout(mA) 25 20 Typical 15 Minimum 10 5 0 -5 -10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Figure a : Pulldown Charateristics Vout(V) 3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 45 ohm@ODT 120 ohm Fix variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. 10 5 0 Iout(mA) -5 -10 -15 -20 Minumum -25 Typical -30 Maximum -35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Vout(V) Figure b : PulluP Charateristics 5. The 45 ohm@ODT 120 ohm fix variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 45 ohm@ODT 120 ohm fix variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from 0 to VDDQ/2 - 47 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Minimum Maximum Typical Minimum Maximum 0.0 -7.3 -5.8 -8.6 7.6 6.1 9.2 0.1 -3.7 -3.2 -3.7 4.6 3.9 5.3 0.2 -0.5 -0.9 0.7 1.8 1.9 1.6 0.3 2.4 1.2 4.6 -0.8 0.0 -1.8 0.4 4.8 2.9 8.0 -3.2 -1.7 -4.9 0.5 7.0 4.4 11.0 -5.3 -3.2 -7.8 0.6 8.8 5.7 13.5 -7.1 -4.6 -10.3 0.7 10.2 6.8 15.4 -8.8 -5.8 -12.4 0.8 11.4 7.7 16.9 -10.2 -7.0 -14.2 0.9 12.5 8.6 18.2 -11.5 -8.0 -15.8 1.0 13.5 9.4 19.3 -12.7 -9.0 -17.3 1.1 14.4 10.7 20.5 -13.9 -9.9 -18.6 1.2 15.4 10.9 21.5 -15.0 -10.8 -19.9 1.3 16.3 11.6 22.6 -16.0 -11.7 -21.2 1.4 17.1 12.4 23.6 -17.1 -12.5 -22.4 1.5 18.0 13.1 24.6 -18.1 -13.4 -23.7 1.6 18.9 13.8 25.6 -19.1 -14.2 -24.8 1.7 19.8 14.6 26.6 -20.1 -15.0 -16.0 1.8 20.6 15.3 27.6 -21.1 -15.8 -27.2 1.9 21.5 16.0 28.6 -22.1 -16.7 -28.3 Temperature (Tj) Typical Minimum Maximum 50 °C 100 °C 0 °C Vdd/Vddq Typical Minimum Maximum 2.5V 2.4V 2.6V The above characteristics are specified under best, worst and normal process variation/conditions - 48 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC 60 ohm @ODT OFF 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 60 ohm@ODT OFF variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 16 Maximum 14 Iout(mA) 12 10 Typical 8 6 Minimum 4 2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Figure a : Pulldown Charateristics Vout(V) 3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 60 ohm@ODT OFF variation in drive pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. 0 -2 Iout(mA) -4 -6 Minumum -8 -10 Typical -12 -14 Maximum -16 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Vout(V) Figure b : PulluP Charateristics 5. The 60 ohm@ODT OFF variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 60 ohm@ODT OFF variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from 0 to VDDQ/2 - 49 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Minimum Maximum Typical 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 2.0 1.4 2.9 -1.6 -1.1 -2.2 0.2 3.7 2.5 5.4 -3.1 -2.1 -4.2 0.3 5.1 3.5 7.5 -4.4 -2.9 -6.0 0.4 6.3 4.2 9.3 -5.5 -3.7 -7.6 Minimum Maximum 0.5 7.3 4.8 10.7 -6.4 -4.3 -9.0 0.6 7.9 5.2 11.8 -7.2 -4.8 -10.1 0.7 8.4 5.5 12.5 -7.7 -5.2 -11.0 0.8 8.7 5.7 12.9 -8.2 -5.5 -11.6 0.9 8.8 5.8 13.2 -8.5 -5.7 -12.1 1.0 8.9 5.8 13.3 -8.8 -5.9 -12.4 1.1 9.0 5.9 13.4 -9.0 -6.0 -12.7 1.2 9.1 5.9 13.5 -9.2 -6.2 -13.0 1.3 9.1 5.9 13.6 -9.4 -6.3 -13.2 1.4 9.2 6.0 13.6 -9.5 -6.4 -13.5 1.5 9.2 6.0 13.7 -9.7 -6.5 -13.6 1.6 9.2 6.0 13.7 -9.8 -6.6 -13.8 1.7 9.3 6.0 13.8 -9.9 -6.7 -14.0 1.8 9.3 6.1 13.8 -10.1 -6.8 -14.1 1.9 9.3 6.2 13.8 -10.2 -6.9 -14.3 Temperature (Tj) Typical Minimum Maximum 50 °C 100 °C 0 °C Vdd/Vddq Typical Minimum Maximum 2.5V 2.4V 2.6V The above characteristics are specified under best, worst and normal process variation/conditions - 50 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC 60 ohm Driver @ODT 120 ohm Fix. 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. Iout(mA) 2. The 60 ohm@ODT 120 ohm fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 25 Maximum 20 Typical 15 Minimum 10 5 0 -5 -10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Figure a : Pulldown Charateristics Vout(V) 3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 60 ohm@ODT 120 ohm fix variation in drive pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. 10 5 Iout(mA) 0 -5 -10 -15 Minumum -20 Typical Maximum -25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Vout(V) Figure b : PulluP Charateristics 5. The 60 ohm@ODT 120 ohm fix variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 60 ohm@ODT 120 ohm fix variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from 0 to VDDQ/2 - 51 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Minimum Maximum Typical Minimum Maximum 0.0 -7.3 -5.8 -8.7 7.6 6.1 9.2 0.1 -4.5 -3.7 -4.9 5.2 4.3 6.1 0.2 -2.0 -1.9 -1.4 2.9 2.7 3.2 0.3 0.3 -0.2 1.6 0.8 1.1 0.5 0.4 2.3 1.2 4.3 -1.1 -0.3 -2.1 0.5 4.1 2.5 6.7 -2.9 -1.6 -4.4 0.6 5.6 3.6 8.7 -4.5 -2.8 -6.5 0.7 6.9 4.6 10.4 -5.9 -3.9 -8.3 0.8 8.0 5.5 11.7 -7.1 -4.9 -9.9 0.9 9.0 6.3 12.9 -8.3 -5.9 -11.3 -12.6 1.0 9.9 7.0 14.0 -9.4 -6.8 1.1 10.8 7.8 15.1 -10.5 -7.6 -13.9 1.2 11.7 8.5 16.1 -11.5 -8.5 -15.1 1.3 12.6 9.3 17.1 -12.5 -9.3 -16.3 1.4 13.5 10.0 18.1 -13.5 -10.1 -17.4 1.5 14.2 10.7 19.1 -14.5 -10.9 -18.5 1.6 15.2 11.4 20.1 -15.5 -11.7 -19.7 1.7 16.1 12.1 21.1 -16.4 -12.5 -20.8 1.8 16.9 12.8 22.1 -17.4 -13.3 -21.0 1.9 17.8 13.6 23.1 -18.3 -14.1 -23.0 Temperature (Tj) Typical Minimum Maximum 50 °C 100 °C 0 °C Vdd/Vddq Typical Minimum Maximum 2.5V 2.4V 2.6V The above characteristics are specified under best, worst and normal process variation/conditions - 52 - Rev. 1.7 (Jan. 2003)