AD AD8385 10-bit, 12-channel decimating Datasheet

10-Bit, 12-Channel Decimating
LCD DECDRIVER® with Level Shifters
AD8385
FEATURES
GENERAL DESCRIPTION
The AD8385 provides a fast, 10-bit, latched decimating digital
input that drives 12 high voltage outputs. 10-bit input words are
loaded into 12 separate high speed, bipolar DACs sequentially.
Flexible digital input format allows several AD8385s to be used
in parallel in high resolution displays. The output signal can be
adjusted for dc reference, signal inversion, and contrast for
maximum flexibility. Integrated level shifters convert timing
signals from a 3 V timing controller to high voltage for LCD
panel timing inputs. Two, serial, 8-bit DACs are integrated to
provide dc reference signals. A 3-wire serial interface controls
overload protection, output mode, and the serial DACs.
FUNCTIONAL BLOCK DIAGRAM
BYP
VRH
VRH
VRL
DB(0:9)
R/L
CLK
STSQ
XFR
BIAS
3
/
SCALING
CONTROL
10
2-STAGE
LATCH
/
4
12
DACs
/
SEQUENCE
CONTROL
/
INV
CONTROL
INV
V1
V2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID8
VID9
VID10
VID11
TSTM
SDI
SCL
SEN
SVRH
SVRL
SVRL
DYIN
DXIN
DIRYIN
DIRXIN
NRGIN
ENBX1I
ENBX2I
ENBX3I
ENBX4I
CLXIN
CLYIN
3
/
12-BIT
SHIFT
REGISTER
VAO1
DUAL
DAC
VAO2
3
/
9
9
/
/
2
CLX
CLY
2
CLXN
CLYN
/
2
/
DY
DX
DIRY
DIRX
NRG
ENBX1
ENBX2
ENBX3
ENBX4
/
R
MONITI
MONITO
S
AD8385
Figure 1.
The AD8385 is fabricated on ADI’s fast bipolar, 26 V XFHV
process, which provides fast input logic, bipolar DACs with
trimmed accuracy and fast settling, high voltage, precision drive
amplifiers on the same chip.
The AD8385 dissipates 1.84 W nominal static power.
The AD8385 is offered in a 100-lead, 14 mm × 14 mm TQFP
E-pad package and operates over the commercial temperature
range of 0°C to 85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
04514-0-001
High voltage drive to within 1.3 V of supply rails
Output short-circuit protection
High update rates
Fast, 100 Ms/s 10-bit input data update rate
Static power dissipation: 1.84 W
Voltage controlled video reference (brightness), offset,
and full-scale (contrast) output levels
INV bit reverses polarity of video signal
3.3 V logic, 9 V to 18 V analog supplies
Level shifters for panel timing signals
High accuracy voltage outputs
Laser trimming eliminates the need for adjustments or
calibration
Flexible logic
STSQ/XFR allow parallel AD8385 operation
Fast settling into capacitive loads
30 ns settling time to 0.25% into 150 pF load
Slew rate 460 V/µs
Available in 100-lead 14 mm × 14 mm TQFP E-pad
AD8385
TABLE OF CONTENTS
Specifications..................................................................................... 3
Reference and Control Input .................................................... 16
DECDRIVER Section .................................................................. 3
Output Operating Mode............................................................ 17
Level Shifters ................................................................................. 4
Overload Protection................................................................... 17
Level Shifting Edge Detector ...................................................... 5
Serial DACs ................................................................................. 17
Serial Interface .............................................................................. 5
Theory of Operation ...................................................................... 18
Power Supplies .............................................................................. 6
Transfer Function and Analog Output Voltage ...................... 18
Operating Temperature ............................................................... 6
Accuracy ...................................................................................... 18
Absolute Maximum Ratings............................................................ 7
Applications..................................................................................... 19
ESD Caution.................................................................................. 7
Optimized Reliability with the Thermal Switch..................... 19
Overload Protection..................................................................... 8
Operation in High Ambient Temperature .............................. 20
Exposed Paddle............................................................................. 8
Power Supply Sequencing ......................................................... 20
Maximum Power Dissipation ..................................................... 8
VBIAS Generation—V1, V2 Input Pin Functionality ........... 20
Operating Temperature Range ................................................... 8
Applications Circuit ................................................................... 21
Pin Configuration and Function Descriptions............................. 9
PCB Design for Optimized Thermal Performance ............... 21
Block Diagrams and Timing Diagrams ....................................... 11
Thermal Pad Design .................................................................. 21
DECDRIVER Section ................................................................ 11
Thermal Via Structure Design.................................................. 21
Level Shifters ............................................................................... 13
AD8385 PCB Design Recommendations ............................... 22
Level Shifting Edge Detector .................................................... 14
Outline Dimensions ....................................................................... 23
Serial Interface ............................................................................ 15
Ordering Guide .......................................................................... 23
Functional Description .................................................................. 16
REVISION HISTORY
1/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8385
SPECIFICATIONS
DECDRIVER SECTION
@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted.
Table 1.
Parameter
VIDEO DC PERFORMANCE1
VDE
VCME
VIDEO OUTPUT DYNAMIC PERFORMANCE
Data Switching Slew Rate
Invert Switching Slew Rate
Data Switching Settling Time to 1%
Data Switching Settling Time to 0.25%
Invert Switching Settling Time to 1%
Invert Switching Settling Time to 0.25%
Invert Switching Overshoot
CLK and Data Feedthrough2
All-Hostile Crosstalk3
Amplitude
Glitch Duration
DAC Transition Glitch Energy
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage—Grounded Mode
Data Switching Delay: t94
INV Switching Delay: t105
INV to CLK Setup Time: t27
Output Current
Output Resistance
REFERENCE INPUTS
V1 Range
V2 Range
V1 Input Current
V2 Input Current
VRL Range
VRH Range
VRH to VRL Range
VRH Input Resistance
VRL Bias Current
VRH Input Current
RESOLUTION
Coding
Conditions
TMIN to TMAX
DAC Code 450 to 800
DAC Code 450 to 800
TMIN to TMAX , VO = 5 V step, CL = 150 pF
20% to 80%
20% to 80%
Min
–7.5
–3.5
460
560
19
30
75
250
100
10
Max
Unit
+7.5
+3.5
mV
mV
24
50
120
500
200
10
30
0.3
DAC Code 511 to 512
AVCC – VOH, VOL – AGND
50 % of VIDx
50 % of VIDx
Typ
10
13
0.5 fCLK
1.1
0.25
12
15
mV p-p
ns
nV-s
1.3
14
17
5.5 fCLK
100
22
V2 ≥ (V1 – 0.25 V)
V2 ≥ (V1 – 0.25 V)
5
5
AVCC – 4
AVCC – 4
–5
–27
VRH ≥ VRL
VRH ≥ VRL
VFS =2 × (VRH – VRL)
To VRL
V1 – 0.5
VRL
0
Binary
10
Rev. 0 | Page 3 of 24
AVCC – 1.3
AVCC
2.75
20
–0.2
125
V/µs
V/µs
ns
ns
ns
ns
mV
mV p-p
V
V
ns
ns
ns
mA
Ω
V
V
µA
µA
V
V
V
kΩ
µA
µA
Bits
AD8385
Parameter
DIGITAL INPUT CHARACTERISTICS
Max. Input Data Update Rate
Data Setup Time: t1
STSQ Setup Time: t3
XFR Setup Time: t5
Data Hold Time: t2
STSQ Hold Time: t4
XFR Hold Time: t6
CLK High Time: t7
CLK Low Time: t8
CIN
IIH
IIL
VIH
VIL
VTH
Conditions
Input tr, tf = 2 ns
Min
Typ
Max
Unit
100
0
0
0
3
3
3
3
2.5
Ms/s
ns
ns
ns
ns
ns
ns
ns
ns
pF
µA
µA
V
V
V
3
0.05
–0.6
2
0.8
1.65
1
VDE = differential error voltage; VCME = common-mode error voltage; VFS = full-scale output voltage = 2 × (VRH – VRL). See the Accuracy section.
Measured on two outputs differentially as CLK and DB(0:9) are driven and XFR is held low.
3
Measured on two outputs differentially as the other four are transitioning by 5 V. Measured for both states of INV.
4
Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV.
5
Measured from 50% of rising CLK edge that follows a valid XFR to 50% of output change. Refer to Figure 6 for the definition.
2
LEVEL SHIFTERS
@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted.
Table 2.
Parameter
LEVEL SHIFTER LOGIC INPUTS
CIN
IIH
IIL
VTH
VIH
VIL
LEVEL SHIFTER OUTPUTS
VOH
VOL
LEVEL SHIFTER DYNAMIC PERFORMANCE
Output Rise, Fall Times—tr, tf
DX, CLX, CLXN, ENBX[1–4]
DY, CLY, CLYN
DIRX, DIRY
NRG
NRG
Propagation Delay Times—t11, t12, t13, t14
DX, CLX, CLXN, ENBX[1–4]
DY, CLY, CLYN
DIRX, DIRY
NRG
NRG
Output Skew
ENBX[1-4]—t15, t16
DX to ENBX[1–4]—t16
DX to CLX—t15, t16, t17, t18
DY, CLY, CLYN—t15, t16, t17, t18
Conditions
Min
Typ
–2
0.05
–0.6
1.65
2.0
DGND
Max
Unit
3
2
pF
µA
µA
V
V
V
DVCC
0.8
RL > 10 kΩ
AVCC – 0.25
0.25
V
V
TA MIN to TA MAX
CL = 40 pF
CL = 40 pF
CL = 40 pF
CL = 200 pF
CL = 300 pF
18.5
40
102
43
61
30
70
200
50
100
ns
ns
ns
ns
ns
CL = 40 pF
CL = 40 pF
CL = 40 pF
CL = 200 pF
CL = 300 pF
20
29
70
30
37
50
50
100
100
ns
ns
ns
ns
ns
2
2
10
20
ns
ns
ns
ns
CL = 40 pF
CL = 40 pF
CL = 40 pF
CL = 40 pF
Rev. 0 | Page 4 of 24
AD8385
LEVEL SHIFTING EDGE DETECTOR
@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted.
Table 3.
Parameter
VIL
VIH
VTH LH
VTH HL
VOH
VOL
IIH
IIL
t19
∆t19
t20
∆t20
tr
tf
Conditions
Input Low Voltage
Input High Voltage
Input Rising Edge Threshold Voltage
Input Falling Edge Threshold Voltage
Output High Voltage
Output Low Voltage
Input Current High State
Input Current Low State
Input Rising Edge Propagation Delay Time
t19 Variation with Temperature
Input Falling Edge Propagation Delay Time
t20 Variation with Temperature
Output Rise Time
Output Fall Time
Min
AGND
AVCC – 0.7
–2.5
CL = 10 pF
CL = 10 pF
10% to 90%
10% to 90%
Typ
AGND + 1
AVCC – 1
DVCC − 0.25
0.25
1.2
–1.2
16
2
12
2
5
6
Max
AGND + 0.75
AVCC
2.5
Unit
V
V
V
V
V
V
µA
µA
ns
ns
ns
ns
ns
ns
SERIAL INTERFACE
@ 25 C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, SVFS = 5 V, SVRL = 4 V, SVRH = 9 V, unless otherwise noted.
Table 4.
Parameter
SERIAL DAC REFERENCE INPUTS
SVRH Range
SVRL Range
SVFS Range
SVRH Input Current
SVRL Input Current
SVRH Input Resistance
SERIAL DAC ACCURACY
DNL
INL
Output Offset Error
Scale Factor Error
SERIAL DAC LOGIC INPUTS
CIN
IIN LOW Low Level Input Current
IIN HIGH High Level Input Current
VTH Input Threshold Voltage
VIH Input High Voltage
VIL Input Low Voltage
SERIAL DAC OUTPUTS
Maximum Output Voltage
Minimum Output Voltage
VAO1—Grounded Mode
IOUT
CLOAD Low Range1
CLOAD High Range1
Conditions
SVFS = (SVRH – SVRL)
SVRL ≤ SVRH
SVRL ≤ SVRH
SVFS = 5 V
SVFS = 5 V
Min
SVRL + 1
AGND + 1.5
1
–2.8
SVFS = 5 V, RL = ∞
SVFS = 5 V, RL = ∞
Typ
125
–2.5
40
–1.0
–1.5
–2.0
–3
Max
Unit
AVCC – 3.5
SVRH – 1
8
150
V
V
V
µA
mA
kΩ
+1.0
+1.5
+2.0
+3
LSB
LSB
LSB
LSB
3
pF
µA
µA
V
V
V
Input tr, tf = 10 ns
–0.6
0.05
1.65
2.0
DGND
DVCC
0.8
SVRH – 1 LSB
SVRL
0.1
±30
0.002
0.047
Rev. 0 | Page 5 of 24
V
V
V
mA
µF
µF
AD8385
Parameter
SERIAL INTERFACE DYNAMIC PERFORMANCE
SEN to SCL Setup Time, t20
SCL, High Level Pulse Width, t21
SCL, Low Level Pulse Width, t22
SDI Setup Time, t24
SDI Hold Time, t25
SCL to SEN Hold Time, t23
VAO1, VAO2 Settling Time, t26
VAO1, VAO2 Settling Time, t26
1
Conditions
Min
Typ
Max
Unit
2
15
ns
ns
ns
ns
ns
ns
ms
ms
10
10
10
10
10
10
SVFS = 5 V, to 0.5%, CL = 100 pF
SVFS = 5 V, to 0.5%, CL = 33 µF
1
Outputs VAO1 and VAO2 are designed to drive very high capacitive loads. For proper operation of these outputs, load capacitance must be ≤0.002 µF or ≥0.047 µF.
Load capacitance in the range of 0.002 µF to 0.047 µF causes the output overshoot to exceed 100 mV.
POWER SUPPLIES
@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, SVFS = 5 V, SVRL = 4 V, SVRH = 9 V, unless otherwise noted.
Table 5.
AD8385 Power Supplies
DVCC, Operating Range
DVCC, Quiescent Current
AVCC Operating Range
Total AVCC Quiescent Current
Min
3
Typ
3.3
56
9
Max
3.6
18
111
Unit
V
mA
V
mA
OPERATING TEMPERATURE
@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, SVFS = 5 V, SVRL = 4 V, SVRH = 9 V, unless otherwise noted.
Table 6.
Parameter
Ambient Temperature Range, TA1
Ambient Temperature Range, TA2
Min
0
0
1
Typ
Max
75
85
Unit
°C
°C
Operation at high ambient temperature requires a thermally-optimized PCB layout (see the Applications section), input data update rate not exceeding 85 MHz, blackto-white transition ≤ 4 V and CL ≤ 150 pF. In systems with limited or no airflow, the maximum ambient operating temperature is limited to 75°C with the overload
protection enabled. For operation above 75°C, see Endnote 2.
2
In addition to the requirements stated in Endnote 1, operation at 85°C ambient temperature requires 200 lfm airflow or the overload protection disabled.
Rev. 0 | Page 6 of 24
AD8385
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Supply Voltage
AVCCx – AGNDx
DVCC – DGND
Input Voltage
Maximum Digital Input Voltage
Minimum Digital Input Voltage
Maximum Analog Input Voltage
Minimum Analog Input Voltage
Internal Power Dissipation1
TQFP E-Pad Package @ TA = 25°C
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering, 10 sec)
Rating
18 V
4.5 V
DVCC + 0.5 V
DGND – 0.5 V
AVCC + 0.5 V
AGND – 0.5 V
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the
absolute maximum ratings for extended periods may reduce
device reliability.
1
100-lead TQFP E-pad package: θJA = 20°C/W (still air),
JEDEC STD, 4-layer PCB in still air.
5.00 W
0°C to 85°C
–65°C to 125°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 24
AD8385
OVERLOAD PROTECTION
OPERATING TEMPERATURE RANGE
The AD8385 employs a 2-stage overload protection circuit with
an enable/disable function that is programmable through the
3-wire serial interface. It consists of an output current limiter
and a thermal shut down.
The maximum operating junction temperature is 150°C. The
junction temperature trip point of the overload protection is
165°C. Production test guarantees a minimum junction
temperature trip point of 125°C.
When enabled, the maximum current at any one output of the
AD8385 is, on average, internally limited to 100 mA. In the
event of a momentary short circuit between a video output and
a power supply rail (VCC or AGND), the output current limit is
sufficiently low to provide temporary protection.
Consequently, the maximum guaranteed operating junction
temperature is 125°C with the overload protection enabled, and
150°C with the overload protection disabled.
EXPOSED PADDLE
To ensure optimal thermal performance, the exposed paddle
must be electrically connected to an external plane such as
AVCC or GND, as described in the Applications Circuit section.
PDMAX ≈
(T
JMAX
− TA )
(θ JA − 0.9 × 3 Airflow in lfm )
3.0
MAXIMUM POWER DISSIPATION (W)
The thermal shutdown debiases the output amplifier when the
junction temperature reaches the internally set trip point. In the
event of an extended short circuit between a video output and a
power supply rail, the output amplifier current continues to
switch between 0 mA and 100 mA typ, with a period determined by the thermal time constant and the hysteresis of the
thermal trip point. Thermal shutdown provides long-term
protection by limiting the average junction temperature to a
safe level. When disabled, no overload protection is present.
To ensure operation within the specified operating temperature
range, the maximum power dissipation must be limited:
STILL AIR
100MHz
2.5
200 lfm
60Hz XGA
500 lfm
2.0
QUIESCENT
The junction temperature limits the maximum power that can
be safely dissipated by the AD8385. The maximum safe junction
temperature for plastic encapsulated devices, determined by the
glass transition temperature of the plastic, is approximately
150°C. Exceeding this limit can cause a temporary shift in the
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
1.5
*65
**90
70
95
75
100
80
105
85
110
90
115
95
120
100
125
105
130
04514-0-002
*OVERLOAD PROTECTION ENABLED
**OVERLOAD PROTECTION DISABLED
MAXIMUM POWER DISSIPATION
AMBIENT TEMPERATURE (°C)
AD8385 on a 4-layer JEDEC PCB with a thermally optimized landing pattern,
as described in the Applications Circuit section.
Figure 2. Maximum Power Dissipation vs. Temperature
Note that the quiescent power dissipation of the AD8385 is
1.84 W when operating under the conditions specified in this
data sheet. When driving a 12-channel XGA panel with an input
capacitance of 150 pF, the AD8385 dissipates a total of 2.3 W
when displaying 1 pixel wide alternating white and black
vertical lines generated by a standard 60 Hz XGA input video.
When the frequency of the pixel clock is raised to 100 MHz, the
total power dissipation increases to 2.54 W. These specific
power dissipations are shown in Figure 2 for reference.
Rev. 0 | Page 8 of 24
AD8385
NC
V1
VRH
VRH
VRL
V2
AVCCD
NC
NC
AGNDD
DB0
DB2
DB1
DB5
DB4
DB3
DB6
DB7
DB8
DB9
CLK
STSQ
XFR
INV
R/L
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DVCC 1
DGND 2
75 AGND0
PIN 1
IDENTIFIER
74 VID0
SDI 3
73 AVCC0,2
SEN 4
72 VID2
SCL 5
71 AGND2,4
BYP 6
70 VID4
TSTM 7
69 AVCC4,6
AGNDS 8
68 VID6
AGNDS 9
67 AGND6,8
SVRL 10
66 VID8
SVRL 11
AD8385
SVRH 12
TOP VIEW
(Not to Scale)
100L
14mm x 14mm
TQFP E-PAD
VAO1 13
VAO2 14
AVCCS 15
65 AVCC8,10
64 VID10
63 AGND10,1
62 VID1
61 AVCC1,3
NC 16
60 VID3
DIRX 17
59 AGND3,5
DIRY 18
58 VID5
DY 19
57 AVCC5,7
CLY 20
56 VID7
CLYN 21
55 AGND7,9
DIRXIN 22
54 VID9
DIRYIN 23
53 AVCC9,11
DYIN 24
52 VID11
CLYIN 25
51 AGND11
04514-0-003
DVCC
DGND
TSTA
DGND
CLX
CLXN
NC
ENBX4
ENBX3
ENBX1
ENBX2
CLXIN
DX
ENBX4I
ENBX2I
ENBX3I
ENBX1I
MONITO
DXIN
NC
MONITI
AGNDL
NRG
NC =
NO CONNECT
AVCCL
NRGIN
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 3. 100-Lead TQFP Package
Table 8. Pin Function Descriptions
Pin Name
DB(0:9)
CLK
STSQ
Function
Data Input
Clock
Start Sequence
R/L
Right/Left Select
XFR
Data Transfer
VID0–VID11
V1, V2
Analog Outputs
Reference Voltages
VRH, VRL
Full-Scale
References
Invert
INV
DVCC
DGND
AVCCx
AGNDx
BYP
SVRH, SVRL
Digital Power Supply
Digital Ground
Analog Power
Supplies
Analog Ground
Bypass
Serial DAC Reference
Voltages
Description
10-Bit Data Input. MSB = DB9.
Clock Input. Data is acquired on both edges of the CLK.
A new data loading sequence begins on the rising edge of CLK when this input was high on the
preceding rising edge of CLK.
A new data loading sequence begins on the left, with Channel 0, when this input is low; a new
data loading sequence begins on the right, with Channel 11 when this input is high.
Data is transferred to the video outputs on the next rising edge of CLK when this input is high on
the rising edge of CLK.
These pins are directly connected to the analog inputs of the LCD panel.
The voltage applied between V1 and AGND sets the white video level during INV = low. The
voltage applied between V2 and AGND sets the white video level during INV = high.
The voltage applied between these pins sets the full-scale video output voltage.
When this input is high, the analog output voltages are above V2. When low, the analog outputs
voltages are below V1.
Digital Power Supply.
This pin is normally connected to the digital ground plane.
Analog Power Supplies.
Analog Supply Returns.
A 0.1 µF capacitor connected between this pin and AGND ensures optimum settling time.
Reference Voltages for the Output Amplifiers of the Serial DACs.
Rev. 0 | Page 9 of 24
AD8385
Pin Name
SCL
SDI
Function
Serial Interface Data
Clock
Serial Interface Data
Input
SEN
Serial Interface
Enable
VAO1, VAO2
Serial DAC Voltage
Output
Test Mode
TSTM
TSTA
MONITI
MONITO
DYIN, DIRYIN,
DIRXIN, DXIN,
NRGIN,
ENBX(1–4)IN
DX, DY, DIRX,
DIRY, NRG,
ENBX(1–4)
CLXIN, CLYIN
CLX, CLXN,
CLY, CLYN,
Test Pin
Monitor Input
Monitor Output
Inverting Level
Shifter Inputs
Inverting Level
Shifter Outputs
Complementary
Level Shifter Inputs
Complementary
Level Shifter
Outputs
Description
Clock for the Serial Interface.
While the SEN input is low, one 12-bit serial word is loaded into the serial interface on the rising
edges of SCL. The first four bits select the function; the following eight bits are the data used in the
serial DACs.
A falling edge of this input initiates a loading cycle. While this input is held low, the serial interface
is enabled and data is loaded on every rising edge of SCL. The selected functions are updated on
the rising edge of this input. While this input is held high, the serial interface is disabled.
These output voltages are updated on the rising edge of the SEN input.
When this input is low, the overload protection and output mode are determined by the function
programmed into the serial interface. While this input is held high, the overload protection is
forced to enabled and the output mode is forced to normal, regardless of function programmed
into the serial interface.
Connect this pin to DGND.
Logic Input of the Level Shifting Inverting Edge Detector.
Output of the Level Shifting Inverting Edge Detector.
Logic Input of the Inverting Level Shifters.
While the corresponding input voltage of these level shifters is below the threshold voltage, the
output voltage at these pins is at VOH. While the corresponding input voltage of these level
shifters is above the threshold voltage, the output voltage at these pins is at VOL.
Logic Input of the Complementary Level Shifters.
While the corresponding input voltage of these level shifters is below the threshold voltage, the
voltage at the noninverting output pins is at VOH and the voltage at the inverting outputs is at
VOL. While the corresponding input voltage of these level shifters is above the threshold voltage,
the voltage at the noninverting output pins is at VOL and the voltage at the inverting outputs is at
VOH.
Rev. 0 | Page 10 of 24
AD8385
BLOCK DIAGRAMS AND TIMING DIAGRAMS
DECDRIVER SECTION
10
10
AD8385
BYP
CLK
STSQ
XFR
R/L
INV
10 2-STAGE 10
LATCH
DAC
VID0
10 2-STAGE 10
LATCH
DAC
VID2
10 2-STAGE 10
LATCH
DAC
VID4
10 2-STAGE 10
LATCH
DAC
VID6
10 2-STAGE 10
LATCH
DAC
VID8
10 2-STAGE 10
LATCH
DAC
VID10
10 2-STAGE 10
LATCH
DAC
VID1
10 2-STAGE 10
LATCH
DAC
VID3
10 2-STAGE 10
LATCH
DAC
VID5
10 2-STAGE 10
LATCH
DAC
VID7
10 2-STAGE 10
LATCH
DAC
VID9
10 2-STAGE 10
LATCH
DAC
VID11
BIAS
SEQUENCE
CONTROL
INV CONTROL
SCALING
CONTROL
VRH VRL
Figure 4. Block Diagram
Rev. 0 | Page 11 of 24
V1
V2
04514-0-004
DB(0:9)
AD8385
tr
tr
t8
CLK
VTH
t7
t1
t1
t2
t2
VTH
DB(0:9)
t3
t4
t5
t6
VTH
04514-0-005
STSQ
VTH
XFR
Figure 5. Input Timing
CLK
DB(0:9)
–9 –8 –7 –6 –5 –4 –3 –2 –1 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
STSQ
XFR
INV
V2+VFS
50%
V2
t9
t27 MAX
t27 MIN
t9
V1
t10
PIXELS –12, –11, –10, –9, –8, –7, –6, –5, –4, –3, –2, –1
PIXELS 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
V1–VFS
04514-0-006
VID(0:11)
Figure 6. Output Timing (R/L = Low)
Table 9.
Parameter
t1
Data Setup Time
t2
Data Hold Time
t3
STSQ Setup Time
t4
STSQ Hold Time
t5
XFR Setup Time
t6
XFR Hold Time
t7
CLK High Time
t8
CLK Low Time
t9
Data Switching Delay
t10
Invert Switching Delay
t27
INV to CLK Setup Time
Conditions
Input tr, tf = 2 ns
Rev. 0 | Page 12 of 24
Min
0
3
0
3
0
3
3
2.5
10
13
0.5/fCLK
Typ
Max
12
15
14
17
5.5/fCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD8385
DYIN
DXIN
DIRYIN
DIRXIN
NRGIN
ENBX1I
ENBX2I
ENBX3I
ENBX4I
DY
DX
DIRY
DIRX
NRG
ENBX1
ENBX2
ENBX3
ENBX4
CLX
CLY
04514-0-007
CLXIN
CLYIN
CLXN
CLYN
04514-0-008
LEVEL SHIFTERS
Figure 8. Level Shifter—Complementary
Figure 7. Level Shifter—Inverting
INPUTS
t11
t12
INVERTING
OUTPUTS
t15
NONINVERTING
OUTPUTS
t13
t14
04514-0-009
t16
t18
t17
Figure 9. Inverting and Complementary Level Shifter Timing
Table 10. Level Shifter Timing
Parameter
Output Rise, Fall Times, tr, tf
DX, CLX, CLXN, ENBX[1–4]
DY, CLY, CLYN
DIRX, DIRY
NRG
Propagation Delay Times—t11, t12, t13, t14
DX, CLX, CLXN, ENBX[1–4]
DY, CLY, CLYN
DIRX, DIRY
NRG
Propagation Delay Skew—t15, t16, t17, t18
ENBX[1–4]—t15, t16
DX to ENBX[1–4]—t16
DX to CLX—t15, t16, t17, t18
DY, CLY, CLYN—t15, t16, t17, t18
Conditions
TA MIN to TA MAX
CL = 40 pF
CL = 200 pF
CL = 300 pF
TA MIN to TA MAX
CL = 40 pF
CL = 200 pF
CL = 300 pF
TA MIN to TA MAX, CL = 40 pF
Rev. 0 | Page 13 of 24
Min
Typ
Max
Unit
18.5
40
102
43
61
30
70
200
50
100
ns
ns
ns
ns
ns
20
29
70
30
37
50
50
100
100
ns
ns
ns
ns
ns
2
2
10
20
ns
ns
ns
AD8385
LEVEL SHIFTING EDGE DETECTOR
MONITO
S
04514-0-010
R
MONITI
Figure 10. Level Shifting Edge Detector Block Diagram
AVCC
MONITI
AGND
t19
t20
VOH
04514-0-011
MONITO
VOL
Figure 11. Level Shifting Edge Detector Timing
Table 11. Level Shifting Edge Detector, AVCC = 15.5 V, DVCC = 3.3 V, CL = 10 pF, TA MIN = 25°C, TA MAX = 85°C
Parameter
VIL
VIH
VTH LH
VTH HL
VOH
VOL
IIH
IIL
t19
∆t19
Input Low Voltage
Input High Voltage
Input Rising Edge Threshold Voltage
Input Falling Edge Threshold Voltage
Output High Voltage
Output Low Voltage
Input Current High State
Input Current Low State
Input Rising Edge Propagation Delay Time
t19 Variation with Temperature
Min
AGND
AVCC – 0.7
t20
∆t20
Input Falling Edge Propagation Delay Time
t20 Variation with Temperature
12
2
ns
ns
tr
tf
Output Rise Time
Output Fall Time
5
6
ns
ns
–2.5
Rev. 0 | Page 14 of 24
Typ
AGND + 1
AVCC – 1
DVCC – 0.25
0.25
1.2
–1.2
16
2
Max
AGND + 0.75
AVCC
2.5
Unit
V
V
V
V
V
V
µA
µA
ns
ns
AD8385
SERIAL INTERFACE
SVRH
SVRL
SDI
12-BIT SHIFT REGISTER
SCL
VAO1, VAO2 = SVRL + SDICODE (SVRH–SVRL)/256
SEN
SD(0:7)
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11
8
DUAL SDAC
/
AO2
SELECT LOAD
AO1
CONTROL
ENABLE
THERMAL
SWITCH
12
VIDEO
DACs
6
12
/
/
/
VID(0:11)
04514-0-012
TSTM
Figure 12. Serial Interface Block Diagram
SEN
SEN
SCL
t21
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t24
04514-0-013
SDI
VAO1,
VAO2
Figure 13. Serial Interface Timing
SDI
t22
t23
t25
D11
D10
D1
D0
04514-0-014
t20
SCL
VAO1,
VAO2
t26
Figure 14. Serial Interface Timing
Table 12. Serial DAC Timing
Parameter
SEN to SCL Setup Time, t20
SCL, High Level Pulse Width, t21
SCL, Low Level Pulse Width, t22
SDI Setup Time, t24
SDI Hold Time, t25
SCL to SEN Hold Time, t23
VAO1, VAO2 Settling Time, t26
Conditions
VFS = 5 V, to 0.5%, CL = 100 pF
VFS = 5 V, to 0.5%, CL = 33 µF
Rev. 0 | Page 15 of 24
Min
10
10
10
10
10
10
Typ
Max
1
2
15
Unit
ns
ns
ns
ns
ns
ns
ms
ms
AD8385
FUNCTIONAL DESCRIPTION
The AD8385 is a system building block designed to directly
drive the columns of LCD microdisplays of the type popularized for use in projection systems. It comprises 12 channels
of precision, 10-bit digital-to-analog converters loaded from a
single, high speed, 10-bit wide input. Precision current feedback
amplifiers, providing well-damped pulse response and fast
voltage settling into large capacitive loads, buffer the 12 outputs.
Laser trimming at the wafer level ensures low absolute output
errors and tight channel-to-channel matching. Tight part-topart matching in high resolution systems is guaranteed by the
use of external voltage references.
INV Control—Analog Output Inversion
Three groups of level shifters convert digital inputs to high
voltage outputs for direct connection to the control inputs of
LCD panels.
3-Wire Serial Interface—SDAC, Output, Thermal Switch
Control
An edge detector conditions a high voltage reference timing
input from the LCD and converts it to digital levels for use in
synchronizing timing controllers, such as the AD8389.
The analog voltage equivalent of the input code is subtracted
from (V2 + VFS) while INV is held high and added to
(V1 – VFS) while INV is held low. Video inversion is delayed
by 6 to 12 CLK cycles from the INV input.
TSTM Control—Test Mode
A low on this input allows serial interface control of the output
operating mode and the thermal switch.
A high on this input turns the thermal switch on and releases
the video outputs and VAO1 from grounded mode.
The serial interface controls two 8-bit serial DACs, the thermal
switch of the overload protection circuit, and the video output
operating mode via a 12-bit-wide serial word from a microprocessor. Four of the 12 bits select the function; the remaining
8 bits are the data for the serial DACs.
REFERENCE AND CONTROL INPUT
Table 13. Bit Definitions
Start Sequence Control—Input Data Loading
Bit
Name
SD(0:7)
SD8
SD9
SD10
A valid STSQ control input initiates a new 6-clock loading cycle
during which 12 input data-words are loaded sequentially into
12 internal channels. Data is loaded on both the rising and
falling edges of CLK. A new loading sequence begins on the
current rising CLK edge only when STSQ is held high at the
preceding rising CLK edge.
Right/Left Control—Input Data Loading
Bit Functionality
8-bit SDAC data. MSB = SD7
Not used
Thermal switch control
Output operating mode, SDAC selection, and
thermal switch control
Output operating mode and SDAC selection control
SD11
To facilitate image mirroring, the direction of the loading
sequence is set by the R/L control.
Table 14. Truth Table @ TSTM = Low
A new loading sequence begins at Channel 0 and proceeds to
Channel 11 when the R/L control is held low. It begins at
Channel 11 and proceeds to Channel 0 when the R/L control
is held high.
SEN
XFR Control—Data Transfer to Outputs
Data transfer to the outputs is initiated by the XFR control. Data
is transferred to all outputs simultaneously on the rising CLK
edge only when XFR is high during the preceding rising
CLK edge.
11
0
1
SD
10 9
0 X
0 X
8
X
X
0
1
0
X
0
1
1
X
1
1
0
X
1
1
1
X
X
X
X
X
V1, V2 Inputs—Voltage Reference Inputs
Two external analog voltage references set the levels of the
outputs. V1 sets the output voltage at Code 1023 while the INV
input is low, and V2 sets the output voltage at Code 1023 while
the INV input is held high.
VRH, VRL Inputs—Full-Scale Video Reference Inputs
Twice the difference between these analog input voltages sets
the full-scale output voltage VFS = 2 (VRH–VRL).
Rev. 0 | Page 16 of 24
Action
Load VAO2. No change to VAO1.
Load VAO1. Release video outputs
from grounded mode. No change to
VAO2.
Release video outputs and VAO1 from
grounded mode. Disable thermal
switch. No change to VAO1 and
VAO2.
Release video outputs and VAO1 from
grounded mode. Enable thermal
switch. No change to VAO1 and
VAO2.
Video outputs and VAO1 to grounded
output mode. Disable thermal switch.
No change to VAO1, VAO2.
Video outputs and VAO1 to grounded
output mode. Enable thermal switch.
No change to VAO1, VAO2.
Start a serial interface loading cycle.
No change to outputs.
AD8385
Table 15. Truth Table @ TSTM = High. Thermal Switch
Enabled. Grounded Output Disabled.
SEN
0
0
X
X
Load VAO2. No change to VAO1.
For systems that operate at high internal ambient temperatures
and require large capacitive loads to be driven by the AD8385 at
high frequencies, junction temperatures above 125°C may be
required. In such systems, the thermal switch should either be
disabled or a minimum airflow of 200 lfm be maintained.
1
0
X
X
Load VAO1. No change to VAO2.
SERIAL DACS
X
1
X
X
No change to VAO1 and VAO2 data.
X
X
X
X
Start a serial interface loading cycle.
No change to outputs.
Both serial DACs are loaded via the serial interface. The output
voltage is determined by the following equation:
11
SD
10 9
Action
8
VAO1, VAO2 = SVRL + SD(0:7) × (SVRH – SVRL)/256
X = Don’t Care.
OUTPUT OPERATING MODE
In normal operating mode, the voltage of the video outputs and
VAO1 is determined by the inputs.
Output VAO1 is designed to drive very large capacitive loads,
above 0.047 µF. Lower capacitive loads may result in excessive
overshoot at VAO1.
Level Shifters
In grounded output mode, the video outputs and VAO1 are
forced to (AGND + 0.1 V) typ.
The characteristics of the level shifters are optimized based on
their intended use.
OVERLOAD PROTECTION
The overload protection employs current limiters and a thermal
switch to protect the video output pins against accidental shorts
between any video output pin and AVCC or AGND.
The junction temperature trip point of the thermal switch is
165°C. Production test guarantees a minimum junction
temperature trip point of 125°C. Consequently, the operating
junction temperature should not be allowed to rise above 125°C
with the thermal switch enabled.
Seven level shifters—DX, CLX, CLXN, and ENBX[1:4]—are
optimized for the X direction and three—DY, CLY and CLYN—
are optimized for the Y direction control signals.
One level shifter—NRG—is designed to drive a large capacitive
load and is optimized for an X direction control signal. Two
level shifters—DIRX and DIRY—are optimized for very low
frequency control signals.
One level shifting edge detector—MONITI, MONITO—is
optimized to condition a synchronizing feedback reference
signal from the LCD.
Rev. 0 | Page 17 of 24
AD8385
THEORY OF OPERATION
TRANSFER FUNCTION AND ANALOG OUTPUT
VOLTAGE
ACCURACY
The DECDRIVER has two regions of operation where the video
output voltages are either above reference voltage V2 or below
reference voltage V1. The transfer function defines the video
output voltage as the function of the digital input code:
VIDx(n) = V2 + VFS × (1 – n/1023), for INV = high
VIDx(n) = V1 – VFS × (1 – n/1023), for INV = low
where:
n = input code
VFS = 2 × (VRH – VRL)
To best correlate transfer function errors to image artifacts, the
overall accuracy of the DECDRIVER is defined by two
parameters, VDE and VCME.
VDE, the differential error voltage, measures the difference
between the rms value of the output and the rms value of the
ideal. The defining expression is
[VOUTN(n) – V 2] – [VOUTP(n) – V 1] ⎛
n ⎞
– ⎜1 –
VDE(n) =
⎟ × VFS
2
⎝ 1023 ⎠
VCME, the common-mode error voltage, measures ½ the dc
bias of the output. The defining expression is
A number of internal limits define the usable range of the video
output voltages, VIDx. See Figure 15.
AVCC
≥ 1.3V
V2 + VFS
INV = HIGH
VIDx (V)
VOUTN(n)
INTERNAL LIMITS AND
USABLE VOLTAGE RANGES
0 ≤ VFS ≤ 5.5V
9V ≤ AVCC ≤ 18V
V2
5V ≤ V2 ≤ (AVCC – 4)
V1
VOUTP(n)
0 ≤ VFS ≤ 5.5V
5V ≤ V1
≤ (AVCC – 4)
INV = LOW
≥ 1.3V
AGND
0
1023
INPUT CODE
04514-0-015
V1 – VFS
Figure 15. Transfer Function and Usable Voltage Ranges
Rev. 0 | Page 18 of 24
1 1
V1 + V 2 ⎤
VCME(n) = ⎡⎢ (VOUTN(n) +VOUTP(n)) –
2 ⎣2
2 ⎥⎦
AD8385
APPLICATIONS
AD8385
12-CHANNEL LCD
VID(0:11)
DB(0:9)
CHANNEL 0–5
STSQ, XFR,
CLK, R/L, INV
IMAGE
PROCESSOR
DIRXIN, DIRYIN,
DYIN, CLYIN,
NRGIN
DIRX, DIRY,
DY, CLY,
CLYN, NRG
LCD TIMING
CONTROLS
DXIN,
CLXIN,
ENBXIN (1–4)
DX,
CLX, CLXN,
ENBX (1–4)
LCD TIMING
CONTROLS
1/3 AD8389
DXI, CLXI,
ENBX(1–4)I
CLK
DXxO, CLXxO,
ENBX(1–4)xO
MONITxI
MONITO
MONITI
VAO1
SDI
µP
MONITOR
SCL
VCOM
VAO2
SEN
04514-0-016
VRH, VRL,
V1, V2,
SVRH, SVRL
DC REFERENCE
VOLTAGES
Figure 16. Typical Applications Circuit
OPTIMIZED RELIABILITY WITH THE THERMAL SWITCH
While internal current limiters provide short-term protection
against temporary shorts at the outputs, the thermal switch
must be enabled to protect against persistent shorts lasting for
several seconds.
OPTION A
DVCC
DVCC
AD8385
To optimize reliability with the use of the thermal switch, the
following sequence of operations is recommended:
TSTM PIN7
SERVICE
JUMPER
TO µP
AD8385
TSTM PIN7
04514-0-017
SERVICE
JUMPER
Initial Power-Up After Assembly or Repair Using a
Service Jumper
OPTION B
DGND
Figure 17. Service Jumper Location
1.
Ensure that the TSTM pin is high on initial power-up by
inserting a service jumper. See Figure 17.
2.
Execute the initial power-up.
Initial Power-Up after Assembly or Repair Using the
Serial Interface
3.
Identify any shorts at outputs.
1.
4.
Power down, repair shorts, and repeat the initial power-up
sequence until proper system functionality is verified.
Immediately after power-up, send Code 011XXXXXXXXX
through the serial interface to enable the thermal switch
and disable the grounded output mode.
5.
Remove service jumper.
2.
Identify any shorts at the outputs.
6.
Resume normal operation.
3.
Power down, repair shorts, and repeat the initial power-up
sequence until proper system functionality is verified.
4.
Resume normal operation.
Rev. 0 | Page 19 of 24
AD8385
Power-Up During Normal Operation
Internal Bias Voltage Generation
The serial interface has no power-on reset.
Code 010XXXXXXXXX, sent immediately following
a power-up places, all outputs into normal operating
mode and disables the thermal switch.
Standard systems that internally generate the bias voltage
reserve the uppermost code range for the bias voltage, and use
the remaining code range to encode the video for gamma
correction. A high degree of ac symmetry is guaranteed by the
AD8385 in these systems.
OPERATION IN HIGH AMBIENT TEMPERATURE
To extend the maximum operating junction temperature of the
AD8385 to 150°C, keep the thermal switch disabled during
normal operation. Code format X10XXXXXXXXX ensures a
disabled thermal switch.
The V1 and V2 inputs in these systems are tied together and are
normally connected to VCOM, as shown in Figure 18.
POWER SUPPLY SEQUENCING
VFS = 5V
AD8385
VCOM
V1
Failure to comply with the Absolute Maximum Ratings, may
result in functional failure or damage to the internal ESD
diodes. Damaged ESD diodes can cause temporary parametric
failures, which can result in image artifacts. Damaged ESD
diodes cannot provide full ESD protection, reducing reliability.
Table 16.
Power-On
1. Apply power to supplies.
2. Apply power to other I/Os.
Power-Off
1. Remove power from I/Os.
2. Remove power from supplies.
VBIAS = 1V
VCOM
VBIAS = 1V
VFS = 5V
During power-up, initial application of nonzero voltages to any
of the input pins must be delayed until the supply voltage ramps
up to its highest operational input voltage.
During power-down, the voltage at any input pin must reach
zero during a period not exceeding the hold-up time of the
power supply.
V2
820
1023
RESERVED
CODE
RANGE
04514-0-018
As indicated in the Absolute Maximum Ratings, the voltage at
any input pin cannot exceed its supply voltage by more than
0.5 V. To ensure compliance with the Absolute Maximum
Ratings, the following power-up and power-down sequencing
is recommended.
Figure 18. V1, V2 Connection and Transfer
Function in a Typical Standard System
External Bias Voltage Generation
In systems that require improved brightness resolution and
higher accuracy, the V1 and V2 inputs, connected to external
voltage references, provide the necessary bias voltage (VBIAS)
while allowing the full code range to be used for gamma
correction.
To ensure a symmetrical ac voltage at the AD8385’s outputs,
VBIAS must remain constant for both states of INV. Therefore,
V1 and V2 are defined as
V1 = VCOM – VBIAS
V2 = VCOM + VBIAS
VBIAS GENERATION—V1, V2 INPUT PIN
FUNCTIONALITY
To avoid image flicker, a symmetrical ac voltage is required and
a bias voltage of approximately 1 V minimum must be
maintained across the pixels of HTPS LCDs. The AD8385
provides an internal and external method of maintaining this
bias voltage.
Rev. 0 | Page 20 of 24
AD8385
APPLICATIONS CIRCUIT
The following circuit ensures VBIAS symmetry to within 1 mV
with a minimum component count. Bypass capacitors are not
shown for clarity.
AVCC = 15.5V
VZ = 5.1V
–IN
V2 = 8V
5
V+
V2
2 V
OCM AD8132
VCOM = 7V
8
R2 = 1kΩ
+IN
V–
4
V1 = 6V
V1
04514-0-019
6
R1 = 6kΩ
DVCC = 3.3V
The total maximum power dissipation of the AD8385 is partly
load-dependent. In a 12-channel 60 Hz XGA system running at
a 65 MHz pixel rate, the total maximum power dissipation is
2.3 W at an LCD channel input capacitance of 150 pF. At a
100 MHz pixel rate, the total maximum power dissipation can
exceed 3 W.
To limit the operating junction temperature at or below the
guaranteed maximum, the package, in conjunction with the
PCB, must effectively conduct heat away from the junction.
AD8385
3
1
PCB DESIGN FOR OPTIMIZED THERMAL
PERFORMANCE
The AD8385 package is designed to provide enhanced thermal
characteristics through the exposed die paddle on the bottom
surface of the package. To take full advantage of this feature, the
exposed paddle must be in direct thermal contact with the PCB,
which then serves as a heat sink.
Figure 19. External VBIAS Generator with the AD8132
A thermally effective PCB must incorporate two thermal pads
and a thermal via structure. The thermal pad on the top PCB
layer provides a solderable contact surface on the top surface of
the PCB. The thermal pad on the bottom PCB layer provides a
surface in direct contact with the ambient. The thermal via
structure provides a thermal path to the inner and bottom
layers of the PCB to remove heat.
VFS = 4V
V2
VBIAS = 1V
VCOM
1023
VBIAS = 1V
V1
THERMAL PAD DESIGN
04514-0-020
VFS = 4V
Figure 20. AD8385 Transfer Function in a Typical High Accuracy System
8.75
7.50
To minimize thermal performance degradation of production
PCBs, the contact area between the thermal pad and the PCB
should be maximized. Therefore, the size of the thermal pad on
the top PCB layer should match the exposed paddle size. The
second thermal pad of at least the same size should be placed on
the bottom side of the PCB. At least one thermal pad should be
in direct thermal contact with a plane such as AVCC or GND.
6.25
THERMAL VIA STRUCTURE DESIGN
(V2 + V1)/2 – VCOM (mV)
5.00
3.75
Effective heat transfer from the top to the inner and bottom
layers of the PCB requires thermal vias incorporated into the
thermal pad design. Thermal performance increases logarithmically with the number of vias.
TA = 25°C
TA = 85°C
2.50
1.25
0.00
–1.25
–2.50
Near optimal thermal performance of production PCBs is
attained only when tightly spaced thermal vias are placed on
the full extent of the thermal pad.
–3.75
–5.00
–6.25
–8.75
5.7
6.2
6.7
7.2
7.7
8.2
8.7
(V+) – (V–) (V)
9.2
9.7
10.2
10.7
04514-0-021
–7.50
Figure 21. Typical Asymmetry at the Outputs of the AD8132 vs. Its Power
Supply for the Application Circuit
Figure 21 shows that the AD8132 (Figure 19) typically produces
a symmetrical output at 85°C when its supply, (V+) – (V–), is
at 7.2 V.
Rev. 0 | Page 21 of 24
AD8385
16 mm
AD8385 PCB DESIGN RECOMMENDATIONS
Top PCB Layer
•
Pad size: 0.25 mm × 0.25 mm
•
Pad pitch: 0.5 mm
•
Thermal pad size: 6.5 mm × 6.5 mm
•
Thermal via structure: 0.25 mm diameter vias on a
0.5 mm grid
6.5 mm
16 mm
6.5 mm
Bottom PCB Layer
04514-0-022
It is recommended that the bottom thermal pad be thermally
connected to a plane. The connection should be direct such that
the thermal pad becomes part of the plane.
Figure 22. Land Pattern—Top Layer
The use of thermal spokes is not recommended when connecting the thermal pads or via structure to the AVCC plane.
Solder Masking
6.5 mm
6.5 mm
To minimize the formation of solder voids due to solder flowing
into the via holes (solder wicking), the via diameter should be
small. Optional solder masking of the via holes on the top layer
of the PCB plugs the via holes, inhibiting solder flow into the
holes. To optimize the thermal pad coverage, the solder mask
diameter should be no more than 0.1 mm larger than the via
hole diameter.
•
Pads: Set by the customer’s PCB design rules
•
Thermal vias: 0.25 mm diameter circular mask, centered
on the vias.
04514-0-023
Solder Mask—Top Layer
Figure 23. Land Pattern—Bottom Layer
Solder Mask—Bottom Layer
04514-0-024
Set by the customer’s PCB design rules.
Figure 24. Solder Mask—Top Layer
Rev. 0 | Page 22 of 24
AD8385
OUTLINE DIMENSIONS
Figure 25. 100-Lead, Thermally Enhanced Thin Quad Flat Package (with Exposed Heat Sink) [TQFP_EP]
(SV-100-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8385ASVZ1
1
Temperature Range
0°C to 85°C
Package Description
100-Lead TQFP_EP
Z = Pb-free part.
Rev. 0 | Page 23 of 24
Package Option
SV-100-3
AD8385
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04514–0–1/05(0)
Rev. 0 | Page 24 of 24