IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: The LVC16823A 18-bit register is built using advanced dual metal CMOS technology. This high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. The Output Enable (OE) and clock (CLK) controls are organized to operate each device as two 9-bit registers or one 18-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of the LVC16823A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ 5V supply system. The LVC16823A has been designed with a ±24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance. • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP, TSSOP, and TVSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1OE 1CLR 1CLK 2 27 2OE 1 28 2CLR 56 2CLK 55 2CLKEN 1CLKEN 29 30 R R R R C C C C 3 DD 1D1 1Q1 54 DD 2D1 15 2Q1 42 TO EIGHT OTHER CHANNELS TO EIGHT OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE APRIL 1999 1 © 1999 Integrated Device Technology, Inc. DSC-4573/2 IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V 1CLR 1 56 1CLK TSTG Storage Temperature –65 to +150 °C 1OE 2 55 1CLKEN IOUT DC Output Current –50 to +50 mA 1Q1 3 54 1D1 IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA GND 4 53 GND mA 1Q2 52 1D2 Continuous Current through each VCC or GND ±100 5 ICC ISS 1Q3 6 51 1D3 VCC 7 50 VCC 1Q4 8 49 1D4 1Q5 9 48 1D5 1Q6 10 47 1D6 GND 11 46 GND 1Q7 12 45 1D7 1Q8 13 44 1D8 1Q9 14 43 1D9 2Q1 15 42 2D1 2Q2 16 41 2D2 2Q3 17 40 2D3 GND 18 39 GND NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description xDx Data Inputs xCLK Clock Inputs 19 38 2D4 2Q5 20 37 2D5 2Q6 21 36 2D6 xOE Output Enable Input (Active LOW) xQx 3-State Outputs 22 35 VCC 2Q7 23 34 2D7 2Q8 24 33 2D8 GND 25 32 GND 2Q9 26 31 2D9 2OE 27 30 2CLKEN 28 29 2CLK 2CLR Unit CIN 2Q4 VCC Max. xCLKEN Clock Enable Inputs (Active LOW) xCLR Asynchronous Clear Inputs (Active LOW) FUNCTION TABLE(1) Inputs SSOP/ TSSOP/ TVSOP TOP VIEW Outputs xOE xCLR xCLKEN xCLK xDx xQx Function H X X X X Z High Z L L X X X L Clear L H H X X Q(2) Hold H H L ↑ L Z H H L ↑ H Z L H L ↑ L L L H L ↑ H H Load NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance ↑ = LOW-to-HIGH transition 2. Output level before indicated steady-state input conditions were established. 2 IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV µA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 µA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit VCC – 0.2 — V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Flip-Flop Outputs enabled CPD Power Dissipation Capacitance per Flip-Flop Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 39 pF 6 SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol fMAX Parameter tPLH Propagation Delay tPHL xCLK to xQx tPHL Propagation Delay VCC = 3.3V ± 0.3V Min. 150 Max. — Min. 150 Max. — Unit MHz — 8.9 1.4 8 ns — 8.8 2.5 7.9 ns — 8.3 1.6 7.2 ns — 7.1 1.1 6 ns 1.3 — 1.3 — ns xCLR to xQx tPZH Output Enable Time tPZL xOE to xQx tPHZ Output Disable Time tPLZ xOE to xQx tSU Set-up Time HIGH or LOW, xDx before xCLK↑ tREM Recovery Time xCLR to xCLK 1 — 1 — ns tH Hold Time HIGH or LOW, xDx after xCLK↑ 2 — 2 — ns tSU Set-up Time HIGH or LOW, xCLKEN LOW before xCLK↑ 1.8 — 1.8 — ns tH Hold Time HIGH or LOW, xCLKEN LOW after xCLK↑ 1.3 — 1.3 — ns tW xCLK Pulse Width HIGH or LOW 3.3 — 3.3 — ns tW xCLR Pulse Width LOW 3.3 — 3.3 — ns Output Skew(2) — — — 500 ps tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF Pulse (1, 2) Generator VIN DISABLE tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Switch VLOAD TIMING INPUT Disable High Enable High GND ASYNCHRONOUS CONTROL All Other Tests Open SYNCHRONOUS CONTROL tSK (x) tPLH2 VOH VT VOL tH tREM tSU tH LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT LVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V Set-up, Hold, and Release Times VOH VT VOL OUTPUT 2 VOH VOH-VHZ 0V VT 0V LVC Link VIH VT 0V tSK (x) tPHZ Enable and Disable Times DATA INPUT tPHL1 VLOAD/2 VOL+VLZ VOL NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Open Drain Disable Low Enable Low tPLZ VLOAD/2 VT LVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test VIH VT 0V CONTROL INPUT Test Circuit for All Outputs OUTPUT 1 VIH VT 0V ENABLE GND VOUT tPLH1 tPHL Propagation Delay LVC Link INPUT tPLH LVC Link D.U.T. RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT LVC X XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package PV PA PF Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 823A 18-Bit Register with 3-State Outputs 16 Double-Density, ±24mA Blank No Bus-hold 74 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459