LINER LT8415 Ultralow power boost converter with dual half-bridge switch Datasheet

LT8415
Ultralow Power Boost
Converter with Dual
Half-Bridge Switches
DESCRIPTION
FEATURES
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High Voltage Switches Built in (Dual half-bridge)
Ultralow Quiescent Current
10.5μA in Active Mode
0μA in Shutdown Mode
Comparator Built into SHDN pin
Low Noise Control Scheme
Adjustable FB reference voltage
Wide Input Range: 2.5V to 16V
Wide Output Range: Up to 40V
Integrated Power NPN Switch (25mA Current Limit)
Integrated Schottky Diode
Integrated Output Disconnect
High Value (12.4M/0.4M) Feedback Resistor Integrated
Built in Soft Start (Optional Capacitor from VREF to GND)
Over Voltage Protection for CAP, VOUT, OUT1 and
OUT2 Pins
12-Pin 3mm × 2mm DFN package
APPLICATIONS
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Sensor Power
RF Mems Relay Power
Low Power Actuator Bias/Control
Liquid Lens Driver
The LT®8415 is an ultralow power boost converter with
two integrated complementary MOSFET half-bridges
(N- and P-channel), integrated power switch, Schottky
diode and output disconnect circuitry. The N-channel and
P-channel MOSFETs in each half-bridge are synchronously
controlled by a single input pin, and never turn on at the
same time in typical applications.
The boost regulator controls power delivery by varying
both the peak inductor current and switch off-time. This
control scheme results in low output voltage ripple as well
as high efficiency over a wide load range. The quiescent
current is a low 10.5μA, which is further reduced to 0μA
in shutdown. The internal disconnect circuitry allows the
output voltage to be blocked from the input during shutdown. High value (12.4M/0.4M) resistors are integrated
on chip for output voltage detection, significantly reducing
input referred quiescent current. The LT8415 also features a
comparator built into the SHDN pin, overvoltage protection
for the CAP, VOUT, OUT1 and OUT2 pins, built in soft start
and comes in a tiny 12-pin 3mm × 2mm DFN package.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815,
6498466, 6611131.
TYPICAL APPLICATION
Drive External Capacitors to 34V/0V with the LT8415
VIN
2.5V to 16V
Response Driving External Capacitors
100μH
2.2μF
SW
CAP
VCC
VOUT
VOUT = 34V
LT8415
LOGIC
LEVEL
CHIP
ENABLE
OUT2 VOLTAGE
20/DIV
22nF
IN 1
IN 2
SHDN
0.1μF*
OUT 1
OUT 2
VREF
34V/0V
137K
GND
34V/0V
887K
OUT1 VOLTAGE
20/DIV
IN1 VOLTAGE
2V/DIV
COUT1 = 1nF
COUT2 = 200pF
FBP
*HIGHER VALUE CAPACITOR IS REQUIRED
WHEN THE VIN IS HIGHER THAN 8V
**THIS CAPACITOR IS OPTIONAL
IN2 VOLTAGE
2V/DIV
20μs/DIV
8415 TA02
0.1μF**
8415 TA01
8415f
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LT8415
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VCC Voltage ................................................– 0.3V to 16V
CAP, VOUT Voltage ......................................– 0.3V to 40V
SW .............................................................– 0.3V to 41V
IN1,IN2 ........................................................– 0.3V to 6V
OUT1,OUT2 ................................................– 0.3V to 40V
SHDN Voltage ............................................– 0.3V to 16V
VREF Voltage..............................................– 0.3V to 2.5V
FBP Voltage...............................................– 0.3V to 2.5V
Maximum Junction Temperature........................... 125°C
Operating Temperature Range (Note 2)..–40°C to 125°C
Storage Temperature Range...................– 65°C to 150°C
TOP VIEW
SHDN 1
12 FBP
VCC 2
GND 3
SW 4
13
11 VREF
10 CAP
IN1 5
9 VOUT
8 OUT1
IN2 6
7 OUT2
DDB PACKAGE
12-PIN (3mm s 2mm) PLASTIC DFN
TJMAX = 125°C, θJA = 76°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8415EDDB#PBF
LT8415EDDB#TRPBF
LFDC
12-Pin (3mm × 2mm) Plastic DFN
–40°C to 125°C
LT8415IDDB#PBF
LT8415IDDB#TRPBF
LFDC
12-Pin (3mm × 2mm) Plastic DFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 3.0V, VSHDN = VIN unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
Minimum Operating Voltage
TYP
MAX
2.20
2.50
V
16
V
1.255
V
Maximum Operating Voltage
l
Reference Voltage
1.220
1.235
UNITS
VREF Current Limit
(Note 3)
10
μA
VREF Discharge Time
(Note 3)
70
μS
VREF Line Regulation
0.01
%/V
Quiescent Current
Not Switching
l
10.5
15.5
μA
Quiescent Current in Shutdown
VSHDN = 0V
l
0
1
μA
Quiescent Current from VOUT and CAP
VOUT = 16V
Minimum Switch Off Time
After Start-Up (Note 4)
During Start-Up (Note 4)
l
Switch Current Limit
Switch VCESAT
4
ISW = 10mA
Switch Leakage Current
VSW = 5V
Schottky Forward Voltage
IDIODE = 10mA
Schottky Reverse Leakage
VCAP – VSW = 5
VCAP – Vsw = 40
μA
240
600
20
25
nS
30
150
mA
mV
0
1
μA
650
850
mV
0
0
0.5
1
μA
μA
8415f
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LT8415
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 3.0V, VSHDN = VIN unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
PMOS Disconnect Current Limit
PMOS Disconnect VCAP - VOUT
MIN
TYP
MAX
14
19
25
IOUT = 1mA
50
l
Internal Resistor Divider Ratio
FBP pin Bias Current
VFBP = 0.5V, Current Flows Out of Pin
l
SHDN Minimum Input Voltage High
SHDN Rising
l
31.6
mV
32.2
1.3
30
nA
1.20
1.30
1.45
V
0.08
0.1
60
(Note 3)
SHDN Input Voltage Low
SHDN Pin Bias Current
VSHDN = 3V
VSHDN = 16V
0
2
IN1,IN2 Minimum Input Voltage High
l
IN1,IN2 Input Voltage Low
l
mA
31.85
SHDN Input Voltage High hysteresis
SHDN Hysteresis Current
UNITS
mV
0.14
μA
0.3
V
1
3
μA
μA
1.1
V
0.3
V
OUT1,OUT2 Rise Time
VOUT = 34V, CLOAD = 200pF (Note 5)
2.5
μs
OUT1,OUT2 Fall Time
VOUT = 34V, CLOAD = 200pF (Note 5)
3
μs
OUT1,OUT2 Rise Delay
VOUT = 34V, CLOAD = 200pF (Note 5)
4
μs
OUT1,OUT2 Fall Delay
VOUT = 34V, CLOAD = 200pF (Note 5)
Half-bridge PMOS Voltage Drop VOUT – VOUT1,OUT2 IN1,IN2 = 2V, 0.1mA Load From OUT1,OUT2
IN1,IN2 = 0V, 0.1mA Current Into OUT1,OUT2
Half-bridge NMOS Voltage Drop VOUT1,OUT2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8415 is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls.
Load Regulation
600
400
200
0
0
1
2
LOAD CURRENT (mA)
3
Vout vs FBP Voltage
8415 G01
VCC = 3.6V
VOUT = 16V
FIGURE 4 CIRCUIT
0.4
40
0.2
0
–0.2
30
20
10
–0.4
–0.6
mV
50
OUTPUT VOLTAGE (V)
800
OUTPUT VOLTAGE CHANGE (%)
SWITCHING FREQUENCY (kHz)
VCC = 3.6V
VOUT = 16V
FIGURE 4 CIRCUIT
85
TA = 25°C, unless otherwise noted.
0.6
1000
μs
mV
Note 3: See applications section for more information.
Note 4: Start-Up mode occurs when VOUT is less than VFBP*64/3.
Note 5: See Timing Diagram. Rise times are measured from 4V to 30V and
fall times are measured from 30V to 4V. Delay times are measured from
the IN1,IN2 transition to when the OUT1,OUT2 voltage has risen to 4V or
decreased to 30V.
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency
vs Load Current
2
70
0
1
2
LOAD CURRENT (mA)
3
8415 G02
0
0
0.5
1
1.5
FBP VOLTAGE (V)
2
8415 G03
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LT8415
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Quiescent Current –
Not Switching
Output Voltage vs Temperature
15
VCC = 3.6V
VCC = 3.6V, VOUT = 16V
LOAD = 0.5mA
FIGURE 4 CIRCUIT
0.5
0.25
0
– 0.25
– 0.5
QUIESCENT CURRENT (μA)
15
QUIESCENT CURRENT (μA)
0.75
OUTPUT VOLTAGE CHANGE (%)
Quiescent Current vs Temperature
18
1
12
9
6
3
– 0.75
0
–1
– 40
0
40
80
TEMPERATURE (°C)
120
0
4
8
12
VCC VOLTAGE (V)
12
9
6
3
0
–40
16
8415 G04
SHDN Current vs SHDN Voltage
VCC = 3.6V
SHDN PIN BIAS CURRENT (μA)
AVERAGE INPUT CURRENT (μA)
QUIESCENT CURRENT (μA)
VCC = 3.6V
3
120
2.5
1000
12
6
40
80
TEMPERATURE (°C)
8415 G06
Average Input Current in
Regulation with No Load
Quiescent Current
vs SHDN Voltage
9
0
8415 G05
100
2
1.5
1
0.5
0
VCC = 3.6V
0
0
1
2
3
SHDN VOLTAGE (V)
4
10
5
–0.5
0
10
20
30
OUTPUT VOLTAGE (V)
8415 G07
UVLO VOLTAGE (V)
VREF VOLTAGE (V)
PEAK INDUCTOR CURRENT (mA)
2.4
1.233
28
1.232
24
16
2.6
1.234
32
8
12
SHDN VOLTAGE (V)
UVLO vs Temperature
1.235
VCC = 3.6V
VOUT = 16V
FIGURE 4 CIRCUIT
4
8415 G09
VREF Voltage vs Temperature
40
0
8415 G08
Peak Inductor Current
vs Temperature
36
40
1.231
VCC RISING
2.2
VCC FALLING
2
1.8
1.6
VCC = 3.6V
20
– 40
0
40
80
TEMPERATURE (°C)
120
8415 G10
1.23
–40
0
40
80
TEMPERATURE (°C)
120
8415 G11
1.4
–40
0
40
80
TEMPERATURE (°C)
120
8415 G12
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LT8415
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
SW Saturation Voltage
vs Switch Current
SHDN Minimum Input Voltage
High vs Temperature
Line Regulation
300
0.3
1.5
VOUT = 16V
200
150
100
50
0
0
5
10
15
20
SWITCH CURRENT (mA)
0.25
1.4
SHDN MINIMUM INPUT
VOLTAGE HIGH (V)
OUTPUT VOLTAGE CHANGE (%)
SWITCH VCESAT (mV)
250
0.2
0.15
0.1
0
0
4
8
12
VCC VOLTAGE (V)
PMOS CURRENT (mA)
20
15
SHDN
VOLTAGE
5V/DIV
INDUCTOR
CURRENT
20mA/DIV
INDUCTOR
CURRENT
20mA/DIV
CAP
VOLTAGE
5V/DIV
VOUT
VOLTAGE
5V/DIV
CAP
VOLTAGE
5V/DIV
VOUT
VOLTAGE
5V/DIV
10
5
VCC = 3.6V
VOUT = 16V
12
120
Start-Up Waveforms With 0.1μF
Capacitor at VREF pin
SHDN
VOLTAGE
5V/DIV
VCAP = 16V
8
40
80
TEMPERATURE (°C)
8415 G15
Start-Up Waveforms Without
Capacitor at VREF Pin
25
4
0
8415 G14
Output Disconnect PMOS current
vs CAP to VOUT Voltage Difference
0
1
–40
16
8415 G13
0
SHDN FALLING
1.2
1.1
0.05
25
SHDN RISING
1.3
8415 G17
200μs/DIV
VCC = 3.6V
VOUT = 16V
8415 G18
2ms/DIV
16
CAP TO VOUT VOLTAGE DIFFERENCE (V)
8415 G16
IN1,IN2 Minimum Input Voltage
High vs Temperature
0.6
0.4
VCC = 3.6V
VOUT = 34V
FRONT PAGE APPLICATION
0
40
80
TEMPERATURE (°C)
120
8415 G19
RISE TIME AND RISE DELAY (μs)
IN1,IN2 MINIMUM INPUT
VOLTAGE HIGH (V)
0.8
0
– 40
5
5
FALL TIME AND FALL DELAY (μs)
1
0.2
Half-Bridge Rise Time and Rise
Delay vs Temperature
Half-Bridge Fall Time and Fall
Delay vs Temperature
4
FALL TIME
3
2
1
0
–40
FALL DELAY
LOAD = 220pF
VCC = 3.6V, VOUT = 34V
FRONT PAGE APPLICATION
0
40
80
TEMPERATURE (°C)
120
8415 G20
RISE DELAY
4
3
RISE TIME
2
1
0
–40
LOAD = 220pF
VCC = 3.6V, VOUT = 34V
FRONT PAGE APPLICATION
0
40
80
TEMPERATURE (°C)
120
8415 G21
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LT8415
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Pin. This pin is used to enable/disable the chip. Drive below 0.3V to disable the chip. Drive
above 1.4V to activate the chip. Do not float this pin.
VOUT (Pin 9): Drain of Output Disconnect PMOS. Place a
bypass capacitor from this pin to GND.
CAP (Pin 10): This is the Cathode of the Internal Schottky
Diode. Place a bypass capacitor from this pin to GND.
VCC (Pin 2): Input Supply Pin. Must be locally bypassed
to GND. See typical applications section.
VREF (Pin 11): Reference Pin. Soft start can be achieved
by placing a capacitor from this pin to GND. This cap
will be discharged for 70μs (typical) at the beginning
of start-up and then be charged to 1.235V with a 10μA
current source.
GND (Pin 3 and Pin 13): Ground. Tie directly to local
ground plane. Pin 13 is floating but must be grounded
for proper shielding.
SW (Pin 4): Switch Pin. This is the collector of the internal
NPN power switch. Minimize the metal trace area connected
to this pin to minimize EMI.
FBP(Pin 12): Positive Feedback Pin. This pin is the error
amplifier’s positive input terminal. To achieve the desired
output voltage, choose the FBP pin voltage (VFBP) according to the following formula:
IN1 (Pin 5): First Half-Bridge Control Input. Do not float
this pin.
VFBP = VOUT /31.85
IN2 (Pin 6): Second Half-Bridge Control Input. Do not
float this pin.
When resistor divider from the VREF is used to set the FBP
voltage, choose the resistor divider ratio according to the
following formula:
OUT2 (Pin 7): Second Half-Bridge Output. This pin is
controlled in phase by the voltage on IN2. The output level
is either the voltage on VOUT or GND.
R1/R2 = (39.33 – VOUT )/VOUT
For protection purposes, the output voltage can not exceed
40V even if VFBP is driven higher than VREF.
OUT1 (Pin 8): First Half-Bridge Output. This pin is controlled
in phase by the voltage on IN1. The output level is either
the voltage on VOUT or GND.
BLOCK DIAGRAM
VCC
SHDN
VOUT
CAP
SW
OUT1
OUT2
2
1
9
10
4
8
7
ENABLE
CHIP
MAX
10μA
+
VOUT
12.4M
TOP GATE
CONTROL
1.235V
+
–
VREF
400K
–
11
1.235V
DISCHARGE
CONTROL
TIMING AND PEAK
CURRENT CONTROL
R1
FB
FBP
OUTPUT DISCONNECT
CONTROL
1.235V
SWITCH
CONTROL
VOUT
TOP GATE
CONTROL
–
+
12
BOTTOM GATE
CONTROL
VC
+
+
BOTTOM GATE
CONTROL
–
R2
13
GND
3
5
GND IN1
6
IN2
8415 BD
8415f
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LT8415
TIMING DIAGRAM
2V
IN1,IN2
VOLTAGE
0V
RISE
TIME
34V
FALL
DELAY
30V
OUT1,OUT2
VOLTAGE
4V
0V
FALL
TIME
RISE
DELAY
8415 TD
OPERATION
Switching Regulator
The LT8415 utilizes a variable peak current, variable offtime control scheme to provide high efficiency over a wide
output current range.
The operation of the part can be better understood by
referring to the Block Diagram. The part senses the
output voltage by monitoring the internal FB node, and
servoing the FB node voltage to be equal to the FBP
pin voltage. The chip integrates an accurate high value
resistor divider (12.4MEG/0.4MEG) from the VOUT pin.
The output voltage is set by the FBP pin voltage, which
in turn is set by an external resistor divider from the VREF
pin. The FBP pin voltage can also be directly biased with
an external reference, allowing full control of the output
voltage during operation.
The Switch Control block senses the output of the amplifier and adjusts the switching frequency as well as other
parameters to achieve regulation. During the start-up of
the circuit, special precautions are taken to ensure that
the inductor current remains under control.
The LT8415 also has a PMOS output disconnect switch.
The PMOS switch is turned on when the part is enabled
via the SHDN pin. When the part is in shutdown, the
PMOS switch turns off, allowing the VOUT node to go to
ground. This type of disconnect function is often required
in power supplies.
Half-Bridge
The N-channel and P-channel MOSFETs in each half-bridge
are synchronously controlled by a single input pin, and
will never turn on at the same time in typical applications,
protecting against shoot-through current. The OUT1 and
OUT2 pins are the same polarity as the IN1 and IN2 pins
respectively. When the part is disabled, both N-channel
and P-channel MOSFETs turn off, and the OUT1 and OUT2
pins will become high impedance with a 20MΩ pull down
resistor connected to ground.
8415f
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LT8415
APPLICATIONS INFORMATION
Inductor Selection
Several inductors that work well with the LT8415 are listed
in Table 1. The tables are not complete, and there are many
other manufacturers and devices that can be used. Consult
each manufacturer for more detailed information and for
their entire selection of related parts, as many different
sizes and shapes are available.
Inductors with a value of 47μH or higher are recommended
for most LT8415 designs. Inductors with low core losses
and small DCR (copper wire resistance) are good choices
for LT8415 applications. For full output power, the inductor should have a saturation current rating higher than
the peak inductor current. The peak inductor current can
be calculated as:
IPK = ILIMIT
VIN • 150 •10 − 6
+
mA
L
where the worst case ILIMIT is 30mA. L is the inductance
value in Henrys and VIN is the input voltage to the boost
circuit.
Table 1. Recommended Inductors for LT8415
PART
L
(μH)
DCR
(μH)
SIZE
(mm)
LQH2MCN680K02
LQH32CN101K53
68
100
6.6
3.5
2.0 × 1.6 × 0.9
3.2 × 2.5 × 2.0
Murata
www.murata.com
DO2010-683ML
DO2010-104ML
LPS3015-104ML
LPS3015-154ML
68
100
100
150
8.8
15.7
3.4
6.1
2.0 × 2.0 × 1.0
2.0 × 2.0 × 1.0
3.0 × 3.0 × 1.4
3.0 × 3.0 × 1.4
Coilcraft
www.coilcraft.com
VENDOR
Capacitor Selection
capacitor placed on the CAP node is recommended to filter
the inductor current while a 0.1μF to 1μF capacitor placed
on the VOUT node will give excellent transient response
and stability. To make the VREF pin less sensitive to noise,
putting a capacitor on the VREF pin is recommended, but
not required. A 47nF to 220nF 0402 capacitor will be sufficient. See also Soft-Start section for more information
about a capacitor across VREF. Table 2 shows a list of several
capacitor manufacturers. Consult the manufacturers for
more detailed information and for their entire selection
of related parts.
Table 2. Recommended Ceramic Capacitor Manufacturers
MANUFACTURER
PHONE
WEBSITE
Taiyo Yuden
(408) 573-4150
www.t-yuden.com
Murata
(814) 237-1431
www.murata.com
AVX
(843) 448-9411
www.avxcorp.com
Kemet
(408)986-0424
www.kemet.com
TDK
(847) 803-6100
www.tdk.com
Setting Output Voltage
The output voltage is set by the FBP pin voltage, and VOUT
is equal to 31.85 • VFBP when the output is regulated,
shown in Figure 1. Since the VREF pin provides a good
reference (~1.235V), the FBP voltage can be easily set by
a resistor divider from the VREF pin to ground. The series
resistance of this resistor divider should be kept larger than
200KΩ to prevent loading down the VREF pin. The FBP pin
can also be biased directly by an external reference. For
over voltage protection, the output voltage is limited to
40V. Therefore, if VFBP is higher than 1.235V, the output
voltage will stay at 40V.
50
40
OUTPUT VOLTAGE (V)
The small size and low ESR of ceramic capacitors make
them suitable for most LT8415 applications. X5R and
X7R types are recommended because they retain their
capacitance over wider voltage and temperature ranges
than other types such as Y5V or Z5U. A 2.2μF or higher
input capacitor and a 0.1μF to 1μF output capacitor are
sufficient for most applications. Always use a capacitor
with a sufficient voltage rating. Many ceramic capacitors
rated at 0.1μF to 1μF have greatly reduced capacitance
when bias voltages are applied. Be sure to check actual
capacitance at the desired output voltage. Generally a 0603
or 0805 size capacitor will be adequate. A 0.1μF to 1μF
30
20
10
0
0
0.5
1
1.5
FBP VOLTAGE (V)
2
8415 F01
Figure 1. FBP to VOUT Transfer Curve
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LT8415
APPLICATIONS INFORMATION
Maximum Output Load Current
Inrush Current
The maximum output current of a particular LT8415 circuit
is a function of several circuit variables. The following
method can be helpful in predicting the maximum load
current for a given circuit:
When VCC is stepped from ground to the operating voltage
while the output capacitor is discharged, a high level of
inrush current may flow through the inductor and Schottky
diode into the output capacitor. Conditions that increase
inrush current include a larger more abrupt voltage step
at VCC , a larger output capacitor tied to the CAP pin and
an inductor with a low saturation current. While the chip is
designed to handle such events, the inrush current should
not be allowed to exceed 0.3A. For circuits that use output
capacitor values within the recommended range and have
input voltages of less than 6V, inrush current remains low,
posing no hazard to the device. In cases where there are
large steps at VCC (more than 6V) and/or a large capacitor
is used at the CAP pin, inrush current should be measured
to ensure safe operation.
Step 1: Calculate the peak inductor current:
IPK = ILIMIT
VIN • 150 • 10 − 6
+
mA
L
where ILIMIT is 25mA. L is the inductance value in Henrys
and VIN is the input voltage to the boost circuit.
Step 2: Calculate the inductor ripple current:
IRIPPLE =
(VOUT + 1− VIN ) • 200 • 10 − 6
mA
L
where VOUT is the desired output voltage. If the inductor
ripple current is less than the peak current, then the circuit
will only operate in discontinuous conduction mode. The
inductor value should be increased so that IRIPPLE < IPK .
An application circuit can be designed to operate only in
discontinuous mode, but the output current capability
will be reduced.
Step 3: Calculate the average input current:
IIN(AVG) = IPK −
IRIPPLE
mA
2
Step 4: Calculate the nominal output current:
IOUT(NOM) =
IIN(AVG) • VIN • 0.7
VOUT
mA
Step 5: Derate output current:
IOUT = IOUT(NOM) • 0.8
For low output voltages the output current capability will
be increased. When using output disconnect (load current
taken from VOUT), these higher currents will cause the
drop in the PMOS switch to be higher resulting in lower
output current capability than predicted by the preceding
equations.
Soft-Start
The LT8415 contains a soft-start circuit to limit peak switch
currents during start-up. High start-up current is inherent
in switching regulators in general since the feedback loop
is saturated due to VOUT being far from its final value. The
regulator tries to charge the output capacitor as quickly
as possible, which results in large peak current.
When the FBP pin voltage is generated by a resistor divider
from the VREF pin, the start-up current can be limited by
connecting an external capacitor (typically 47nF to 220nF)
to the VREF pin. When the part is brought out of shutdown,
this capacitor is first discharged for about 70μs (providing
protection against pin glitches and slow ramping), then
an internal 10μA current source pulls the VREF pin slowly
to 1.235V. Since the VOUT voltage is set by the FBP pin
voltage, the VOUT voltage will also slowly increase to the
regulated voltage, which results in lower peak inductor
current. The voltage ramp rate on the pin can be set by
the value of the VREF pin capacitor.
Output Disconnect
The LT8415 has an output disconnect PMOS that blocks
the load from the input during shutdown. The maximum
current through the PMOS is limited to 19mA by circuitry
inside the chip, helping the chip survive output shorts.
8415f
9
LT8415
APPLICATIONS INFORMATION
If the application doesn’t require the output disconnect
function, the CAP and VOUT pin can be shorted, and higher
power converter efficiency can be achieved.
SHDN Pin Comparator and Hysteresis Current
An internal comparator compares the SHDN pin voltage
with an internal voltage reference (~1.3V) which gives a
precise turn-on voltage level. The internal hysteresis of this
turn-on voltage is about 60mV. When the chip is turned on,
and the SHDN pin voltage is close to this turn-on voltage,
0.1μA current flows out of the SHDN pin. This current is
called SHDN pin hysteresis current, and will go away when
the chip is off. By connecting the external resistors as in
Figure 2, a user-programmable enable voltage function
can be realized.
Board Layout Considerations
As with all switching regulators, careful attention must
be paid to the PCB layout and component placement. To
maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interference (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the SW pin
has sharp rising and falling edges. Minimize the length and
area of all traces connected to the SW pin and always use
a ground plane under the switching regulator to minimize
interplane coupling. In addition, the FBP pin and VREF pin
are sensitive to noise. Minimizing the length and area of all
traces to these two pins is recommended. Recommended
component placement is shown in Figure 3.
SHDN
VIN
The turn-on voltage for the configuration is:
1.30 • (1 + R1/R2)
SHDN
and the turn-off voltage is:
VCC
(1.24 – R3 • 10 –7) • (1 + R1/R2) – R1 • 10 –7
where R1, R2 and R3 are resistance value in Ω.
FBP
GND
VREF
GND
CAP
SW
VOUT
IN1
OUT1
IN2
OUT2
ENABLE VOLTAGE
R1
R3
CONNECT TO
SHDN PIN
8410 F03
R2
IN2
IN1
OUT1
OUT2
VIAS TO GROUND PLANE REQUIRED
TO IMPROVE THERMAL PERFORMANCE
Figure 2. Programming Enable Voltage by Using External
Resistors
Half-Bridge Control Signals
VIAS FOR CAP AND VOUT GROUND RETURN THROUGH
SECOND METAL LAYER, CAPACITOR GROUNDS MUST
BE RETURNED DIRECTLY TO IC GROUND
Figure 3. Recommended Board Layout
The half-bridge is controlled by the IN1 and IN2 pins. The
IN1 and IN2 pins should be driven with a logic signal.
When the chip is enabled, the OUT1 and OUT2 voltages
are equal to VOUT IN1 and IN2 are driven higher than 1V,
and they are near GND when IN1 and IN2 are driven below
0.3V. Do not drive the IN1 or IN2 pins between 0.3V to
1V for more than 20μs since this will leave OUT1 or OUT2
in an uncertain state and may also cause shoot-through
current.
8415f
10
LT8415
TYPICAL APPLICATIONS
Drive External Capacitors to 34V/0V with the LT8415
Response Driving External Capacitors
L1
100μH
VIN
2.5V to 16V
C1
2.2μF
SW
CAP
VCC
VOUT
IN 1
IN 2
LOGIC
LEVEL
SHDN
GND
VOUT = 34V
C3
0.1μF*
LT8415
CHIP
ENABLE
OUT2 VOLTAGE
20/DIV
C2
22nF
OUT 1
OUT 2
VREF
IN2 VOLTAGE
2V/DIV
34V/0V
COUT1
OUT1 VOLTAGE
20/DIV
34V/0V
COUT2
R1
137K
IN1 VOLTAGE
2V/DIV
FBP
R2
887K
C1: 2.2μF, 16V, X5R, 0603
C2: 22nF, 100V, X5R, 0603
C3: 0.1μF, 100V, X5R, 0603*
C4: 0.1μF, 16V, X7R, 0402
L1: COILCRAFT DO2010-104ML
* HIGHER CAPACITANCE VALUE IS
REQUIRED FOR C3 WHEN THE VIN IS
HIGHER THAT 8V
C4
0.1μF
8415 TA02
20μs/DIV
COUT1 = 1nF
COUT2 = 200pF
8415 TA03
VOUT (V)
RESISTOR DIVIDER
FROM VREF
R1 (kΩ)/R2 (kΩ)
VIN = 2.8V
VIN = 3.6V
VIN = 5.0V
VIN = 12V
40
NA
0.5
0.7
1.1
3.6
35
110/887
0.7
0.9
1.4
4.4
30
237/768
0.8
1.0
1.5
5.5
25
365/634
1.0
1.4
2.1
7.2
20
487/511
1.4
1.9
2.9
9.7
15
619/383
1.6
2.4
4.0
14
10
750/255
3.3
4.6
7.0
NA
5
866/127
8.0
11
17
NA
MAXIMUM OUTPUT CURRENT (mA)
PACKAGE DESCRIPTION
DDB Package
12-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1723 Rev Ø)
0.64 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
R = 0.05
TYP
R = 0.115
TYP
7
0.40 ± 0.10
12
0.70 ±0.05
2.55 ±0.05
1.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
2.00 ±0.10
(2 SIDES)
0.75 ±0.05
0.64 ± 0.10
(2 SIDES)
6
0.23 ± 0.05
1
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
0 – 0.05
(DDB12) DFN 0106 REV Ø
0.45 BSC
0.45 BSC
2.39 ±0.05
(2 SIDES)
PIN 1
R = 0.20 OR
0.25 s 45°
CHAMFER
2.39 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
8415f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT8415
TYPICAL APPLICATION
L1
100μH
VIN
2.5V to 16V
C1
2.2μF
SW
CAP
VCC
VOUT
C2
0.1μF
C3
0.1μF*
LT8415
LOGIC
LEVEL
CHIP
ENABLE
IN 1
IN 2
SHDN
OUT 1
OUT 2
VREF
16V/0V
COUT1
604K
GND
VOUT = 16V
16V/0V
COUT2
FBP
412K
C4
C1: 2.2μF, 16V, X5R, 0603
0.1μF
C2: 0.1μF, 25V, X5R, 0603
C3: 0.1μF, 25V, X5R, 0603*
8415 TA04
C4: 0.1μF, 16V, X7R, 0402
L1: MURATA LQH32CN101K53
* HIGHER CAPACITANCE VALUE IS REQUIRED FOR C3 WHEN THE VIN IS HIGHER THAT 8V
Figure 4. Drive External Capacitors to 16V/0V with the LT8415
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DESCRIPTION
COMMENTS
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Package
8415f
12 Linear Technology Corporation
LT 0409 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2009