LINER LTC4310IMS-1-TRPBF Hot-swappable i2c isolator Datasheet

LTC4310-1/LTC4310-2
Hot-Swappable
I2C Isolators
Features
Description
Bidirectional I2C Communication Between Two
Isolated Buses
n Full Isolation with Inexpensive Ethernet
Transformers or Capacitors
n Low Voltage Level Shifting
n I2C Maximum Operating Frequency:
100kHz for LTC4310-1
400kHz for LTC4310-2
n I2C Specification Compliant V , V
OL IL
n ±5kV Human Body Model ESD Protection
n Rise Time Accelerators
n SDA, SCL Hot-Swapping
n Very Low Shutdown Current
n Stuck Bus Disconnect and Recovery
n Thermal Shutdown
n 10-Lead MSOP and 3mm × 3mm DFN Packages
The LTC®4310 provides bidirectional I2C communications
between two I2C buses whose grounds are isolated from
one another. Each LTC4310 encodes I2C bus logic states
into signals that are transmitted across an isolation barrier
to another LTC4310. The receiving LTC4310 decodes the
transmission and drives its l2C bus to the appropriate logic
state. The isolation barrier can be bridged by an inexpensive
Ethernet, or other transformer, to achieve communications
across voltage differences reaching thousands of volts, or
it can be bridged by capacitors for lower voltage isolation.
The LTC4310-1 is intended for use in 100kHz I2C systems.
The LTC4310-2 is intended for 400kHz I2C systems.
n
Rise time accelerators provide strong pull-up currents on
SCL and SDA rising edges to meet rise time specifications
for heavily loaded systems. Data and clock Hot Swap™
circuitry prevent data corruption when a card is inserted
into or removed from a live bus. When a bus is stuck low
for 37ms, the LTC4310 turns off its pull-down devices and
generates up to sixteen clocks and a STOP bit in an attempt
to free the bus. Driving EN low sets the LTC4310 in a very
low current shutdown mode to conserve power.
Applications
n
n
n
n
Isolated I2C, SMBus and PMBus Interfaces
Isolated Power Supplies
Positive-to-Negative Rail Communications
Power-over-Ethernet
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Typical Application
LTC4310 Operating Through
20kV/µs Common Mode Transient
1500V Isolated I2C System
3.3V
0.01µF
10/100Base-TX
ETHERNET TRANSFORMER
VCC TXP
RXP
VCC
0.01µF
ISOLATED
5V
0V
3.3k
3.3k
0.01µF
LTC4310-1
LTC4310-1
3.3k
3.3k
SDA1
SDA
TXN
RXN
SDA
SDA2
SCL1
SCL
RXP
TXP
SCL
SCL2
SCL
2V/DIV
SDA
500V/
DIV
20kV/µs
0V
EN
READY
EN
0.01µF
2µs/DIV
READY
GND RXN
431012 TA01b
TXN GND
EPF8119S
431012 TA01a
431012f
LTC4310-1/LTC4310-2
Absolute Maximum Ratings
(Notes 1, 4)
Input Supply Voltage (VCC)........................... –0.3V to 6V
Input and Bidirectional Pin Voltages
SCL, SDA, EN, RXP, RXN........................... –0.3V to 6V
Output Voltages
READY...................................................... –0.3V to 6V
TXP, TXN....................... –0.3V to VCC + 0.3V (6V Max)
Maximum Sink Current (SDA, SCL, READY)...........30mA
Operating Ambient Temperature Range
LTC4310C................................................. 0°C to 70°C
LTC4310I.............................................. –40°C to 85°C
Storage Temperature Range
DD...................................................... –65°C to 125°C
MS...................................................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package....................................................... 300°C
Pin Configuration
TOP VIEW
EN
1
10 RXN
SDA
2
9 RXP
SCL
3
READY
4
GND
5
11
GND
TOP VIEW
EN
SDA
SCL
READY
GND
8 VCC
7 TXP
6 TXN
1
2
3
4
5
10
9
8
7
6
RXN
RXP
VCC
TXP
TXN
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 120°C/W
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) PCB CONNECTION TO GROUND IS OPTIONAL
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4310CDD-1#PBF
LTC4310CDD-1#TRPBF
LFCH
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC4310IDD-1#PBF
LTC4310IDD-1#TRPBF
LFCH
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4310CMS-1#PBF
LTC4310CMS-1#TRPBF
LTFCG
10-Lead Plastic MSOP
0°C to 70°C
LTC4310IMS-1#PBF
LTC4310IMS-1#TRPBF
LTFCG
10-Lead Plastic MSOP
–40°C to 85°C
LTC4310CDD-2#PBF
LTC4310CDD-2#TRPBF
LFCK
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC4310IDD-2#PBF
LTC4310IDD-2#TRPBF
LFCK
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4310CMS-2#PBF
LTC4310CMS-2#TRPBF
LTFCJ
10-Lead Plastic MSOP
0°C to 70°C
LTC4310IMS-2#PBF
LTC4310IMS-2#TRPBF
LTFCJ
10-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
431012f
LTC4310-1/LTC4310-2
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supplies
VCC
Input Supply Range
5.5
V
ICC
Input Supply Current, LTC4310-1
Input Supply Current, LTC4310-2
EN = VCC = 5.5V, SDA = SCL = VSDA,SCL(OL)
EN = VCC = 5.5V, SDA = SCL = VSDA,SCL(OL)
l
l
6.5
7
8
8.5
mA
mA
ICC(SD)
Shutdown Input Supply Current
EN = 0V, VCC = 5.5V
l
0.1
±10
µA
VCCH(UVL)
Input Supply Undervoltage Lockout
Rising Threshold Voltage
l
2.1
2.4
2.7
V
VCC(UVL, HYST)
Input Supply Undervoltage Lockout
Hysteresis
l
90
190
270
mV
l
310
350
380
mV
l
3
I2C Interface
VSDA,SCL(OL)
SDA, SCL Logic Low Output Voltage
I(SDA,SCL) = 4mA, 500µA; VCC = 3V, 5.5V
VSDA,SCL(IL,R)
SDA, SCL Controlled Rising Edge Rate VCC = 3V, 5.5V (Note 5)
Turn-Off Threshold Voltage
l
0.3 • VCC
0.35 • VCC
0.4 • VCC
V
VSDA,SCL(IL,F)
SDA, SCL Logic Low Falling Input
Threshold Voltage
VCC = 3V
l
0.4 • VCC
0.45 • VCC
0.5 • VCC
V
ISDA,SCL(OH)
SDA, SCL Input Current
SCL, SDA = VCC = 0V, 5.5V
l
0
±5
µA
Bus Line Controlled Rising Edge Rate,
LTC4310-1
0.35V < VBUS < 0.35 • VCC, VCC = 3V
0.35V < VBUS < 0.35 • VCC, VCC = 5.5V
l
l
0.8
1.5
1.16
2.14
1.4
2.6
V/µs
V/µs
Bus Line Controlled Rising Edge Rate,
LTC4310-2
0.35V < VBUS < 0.35 • VCC, VCC = 3V
0.35V < VBUS < 0.35 • VCC, VCC = 5.5V
l
l
2
3.9
3
5.4
3.9
6.9
V/µs
V/µs
tPHL(SDA,SCL)
SDA, SCL High-to-Low Propagation
Delay
VCC = 5.5V (Note 3)
l
170
270
ns
fSCL(MAX)
Maximum SCL Clock Frequency
LTC4310-1
LTC4310-2
l
l
CIN
SCL, SDA Input Capacitance
SCL, SDA = VCC (Note 2)
I2C Interface Timing
dV/dtRISE
100
400
kHz
kHz
10
pF
0.5 • VCC
V
Rise Time Accelerators
VBOOST
SDA, SCL Rise Time Accelerator
Activation Threshold Voltage
VCC = 3V (Note 5)
l
IBOOST
SDA, SCL Rise Time Accelerator
Current
VCC = 3V
l
0.32 • VCC 0.45 • VCC
2
6
mA
READY Open-Drain Output
VREADY(OL)
READY Output Low Voltage
IREADY = 4mA
l
50
400
mV
IREADY(OH)
READY Off-Current
READY= VCC = 5.5V, EN = 0V
l
0.1
±10
µA
0.6 • VCC
0.9 • VCC
V
Connection Control
VEN,RISE
EN Rising Threshold Voltage
l
VEN,FALL
EN Falling Threshold Voltage
l
IEN(OH)
EN Input Current
tIDLE
tUVLO,EN_FILT
tSTUCK
EN = VCC = 5.5V
0.1 • VCC
0.3 • VCC
0.1
l
Bus Idle Time
l
75
Start-Up Filter Time
l
700
SDA, SCL Bus Stuck Low Disconnect
l
27
V
±10
µA
115
155
µs
900
1200
µs
37
47
ms
431012f
LTC4310-1/LTC4310-2
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL
PARAMETER
tMAX(TX)
tMAX(RX)
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Time Between TXP, TXN
Transmit Events
l
0.85
1.15
1.45
ms
Maximum Time Between RXP, RXN
Receive Events
l
3.4
4.6
5.8
ms
1.5
5
mV
0.95
1.25
1.52
V
Transmit Outputs
VTX(OL)
TXP, TXN Single-Ended Output Low
ISINK = 100µA, VCC = 3V
l
VTX(OH)
TXP, TXN Single-Ended Output High
15kΩ to GND on TXP, TXN; VCC = 3V, 5.5V
l
tR(TX)
TXP, TXN Output Rise Time
CTXP, CTXN = 20pF
l
1
3
ns
tF(TX)
TXP, TXN Output Fall Time
CTXP, CTXN = 20pF
l
1
3
ns
tPWMIN(TX)
TXP, TXN Minimum Transmission
Pulse Width
VCC = 3V, 5.5V
l
31.5
35
39
ns
VRX(TH)
RXP, RXN Differential High Level
Threshold
RXP, RXN Pins; VCC = 3V, 5.5V
l
0.3
0.5
0.875
V
tPWMIN(RX)
RXP, RXN Minimum Received Pulse
Width
VCC = 3V, 5.5V
l
30
RRX(IN)
RXP, RXN Differential Input Resistance
l
13
Receive Inputs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. Guaranteed by design, not tested in production.
Note 3. SDA, SCL high-to-low propagation delay is measured from the
beginning of a new received message telling the LTC4310 to drive its SDA,
SCL pins from high to low, to when the SDA, SCL lines have fallen below
0.5 • VCC. It includes approximately 87ns required for an LTC4310 to
ns
16.5
20
kΩ
receive a message on the RXP and RXN pins, plus the time the LTC4310
requires to process the message and pass the low to the data and clock
buffers, plus the time required by the buffers to drive their bus pins below
0.5 • VCC.
Note 4. All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 5. Internal control circuitry prevents the rise time accelerators from
activating until the rising edge rate control circuitry is off.
431012f
LTC4310-1/LTC4310-2
Typical Performance Characteristics
SDA = 0V
SCL = VCC
2.0
ICC (mA)
4.8
4.6
VCC = 3.3V
4.4
4.2
4.0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
1.8
1.6
1.4
VCC = 3.3V
1.2
–50
125
25
50
75
100
125
431012 G02
SDA, SCL Rise Time Accelerator
Pull-Up Current vs Temperature
11
5.0
VCC = 5V
10
PULL-UP CURRENT (mA)
CONTROLLED RISE RATE (V/µs)
0
TEMPERATURE (°C)
5.5
4.5
4.0
3.5
VCC = 3.3V
3.0
VCC = 5V
9
8
7
VCC = 3.3V
6
2.5
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
5
–50
125
12
–25
0
25
50
75
100
TEMPERATURE (°C)
431012 G03
SDA, SCL Rise Time Accelerator
Pull-Up Current vs Bus Capacitance
125
431012 G04
SDA,SCL Falling Propagation
Delay vs Temperature
220
TA = 25°C
200
PROPAGATION DELAY (ns)
10
PULL-UP CURRENT (mA)
–25
431012 G01
SDA, SCL Controlled Rising Edge
Rate vs Temperature, LTC4310-2
VCC = 5V
8
6
VCC = 3.3V
4
2
0
VCC = 5V
VCC = 5V
CONTROLLED RISE RATE (V/µs)
5.0
SDA, SCL Controlled Rising Edge
Rate vs Temperature, LTC4310-1
ICC vs Temperature, LTC4310-1
VCC = 3.3V
180
160
VCC = 5V
140
120
0
100 200 300 400 500 600 700 800
BUS CAPACITANCE (pF)
431012 G05
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
431012 G06
431012f
LTC4310-1/LTC4310-2
Pin Functions
EN (Pin 1): Device Enable Input. Pulling EN up to VCC
sets the device in normal operation mode, allowing bus
information to be sent and received across the barrier.
Grounding EN disables communication across the barrier and debiases all internal circuitry, setting the device
in a very low current shutdown mode. Connect to VCC if
unused.
SDA (Pin 2): Serial Bus Data Input/Output. This is the
bidirectional data line for the two-wire bus. An external
pull-up resistor or current source from SDA to a supply
voltage greater than or equal to the VCC voltage is required.
See the Applications Information section for guidance
on selecting the resistor or current source value. Do not
leave open.
SCL (Pin 3): Serial Bus Clock Input/Output. This is the
bidirectional clock line for the two-wire bus. An external
pull-up resistor or current source from SCL to a supply
voltage greater than or equal to the VCC voltage is required.
See the Applications Information section for guidance
on selecting the resistor or current source value. Do not
leave open.
READY (Pin 4): Device Receiving Indicator Output. READY
is an open-drain digital output that pulls low when the
LTC4310 is driving its SDA and SCL pins with the logic
state information it is receiving on its RXP and RXN pins.
Connect this pin to VCC with a 10k resistor. This pin can
be left open or tied to GND if unused.
TXN (Pin 6): Negative Transmit Output. Tie TXN to the
negative side of the transformer primary winding or to the
RXN pin of another LTC4310 through a ceramic capacitor.
See the Applications Information section for guidance in
selecting the capacitor value. Do not leave open.
TXP (Pin 7): Positive Transmit Output. Tie TXP to the
positive side of the transformer primary winding or to the
RXP pin of another LTC4310 through a ceramic capacitor.
See the Applications Information section for guidance in
selecting the capacitor value. Do not leave open.
VCC (Pin 8): Device Power Supply Input. Connect a bypass capacitor of at least 0.01µF directly between VCC
and GND.
RXP (Pin 9): Positive Receive Input. Tie RXP to the positive side of the transformer secondary winding or to the
TXP pin of another LTC4310 through a ceramic capacitor.
See the Applications Information section for guidance in
selecting the capacitor value. Do not leave open.
RXN (Pin 10): Negative Receive Input. Tie RXN to the negative side of the transformer secondary winding or to the
TXN pin of another LTC4310 through a ceramic capacitor.
See the Applications Information section for guidance in
selecting the capacitor value. Do not leave open.
Exposed Pad (Pin 11) DFN Package Only: The exposed
pad may be left open or connected to device ground.
GND (Pin 5): Device Ground.
431012f
LTC4310-1/LTC4310-2
FUNCTIONAL Diagram
+
–
LOGIC
0.45 • VCC
1.25V
8
0.45 • VCC
VCC
IBOOST
2
0.35 • VCC
SDA
0.35V
+
–
+
–
FALLING VIL
RISING VIL
–
+
3
SCL
+
–
+
–
–
+
0.45 • VCC
–+
RXP
–+
RXN
9
10
0.5V
0.45 • VCC
+
–
0.35 • VCC
+
–
0.35V
FALLING VIL
STOP BIT
AND BUS IDLE
DETECTORS
RXP
RXN
RISING VIL
RX
–
+
RISE RATE
LIMITER
dV/dtRISE
150µA
1
6
LOGIC
0.5V
+
–
IBOOST
TXN
RX
150µA
LOGIC
7
1.25V
RISE RATE
LIMITER
dV/dtRISE
VCC
TXP
+
–
STUCK BUS
TIMERS
SCL
SDA
READY
4
EN
GND
tSD
VCC
2.4V/2.21V
+
–
5
UVLO
POR CIRCUITRY
431012 FD
431012f
LTC4310-1/LTC4310-2
Operation
(LTC4310 refers to both LTC4310-1 and LTC4310-2)
The LTC4310 provides fully bidirectional communications
between two I2C or SMBus buses whose grounds are
isolated from one another. Clock stretching, clock synchronization, arbitration and data acknowledging all work
seamlessly across the barrier, regardless of the locations
of the master(s) and slave(s).
bus rise rate to dV/dtRISE via the rise rate limiter circuitry.
It also transmits a high to the other LTC4310. If the SDA
rise rate falls below the threshold, it is assumed that another pull-down on the bus has turned on and is pulling
SDA low, and a command to pull the far side low is sent
across the isolation barrier.
Referring to the application circuit shown in Figure 1, an
LTC4310 is located on each side of the isolation barrier.
Each LTC4310 contains logic detection circuitry that can
differentiate externally driven SDA and SCL logic signals
from its own output signals. Each LTC4310 converts the
logic state of the externally driven signals into a sequence
of pulses that are then transmitted across the isolation barrier via an Ethernet transformer (or coupling capacitors for
low isolation voltage applications) to the other LTC4310.
Each LTC4310 also receives and decodes corresponding
pulses from the other LTC4310 and drives its SDA and
SCL pins accordingly.
When SDA rises above 0.35 • VCC, the rise rate limiter
circuitry is deactivated. When SDA rises above 0.45 • VCC,
the rise time accelerator current IBOOST is activated, which
provides a strong, slew-limited pull-up current to reduce
system rise time.
Transmissions occur on the TXP and TXN pins in a sequence
of 1.25V pulses. The LTC4310 receives messages on its
RXP and RXN pins. Signals having less than 500mV differential voltages are rejected to provide noise immunity
against common-mode transients.
When the LTC4310 receives a message to drive SDA low,
it regulates SDA to 0.35V. If an external device pulls SDA
below 0.35V during this time, the LTC4310 detects this
condition and immediately transmits a LOW to the other
LTC4310.
When an external pull-down device drives SDA below
0.45 • VCC from a logic high, TXP and TXN transmit a
message across the isolation barrier instructing the other
LTC4310 to drive its SDA line low.
When the external pull-down device turns off and SDA is
rising between 0V and 0.35 • VCC, the LTC4310 limits the
The LTC4310 contains power-on reset (POR) circuitry that
sets the data and clock pins in a high impedance state and
deactivates the transmit and receive circuitry until the EN
voltage is high, the device is not in thermal shutdown
and the VCC voltage is above the 2.4V UVLO threshold
voltage. The LTC4310 enters thermal shutdown when the
die temperature exceeds 150°C. Grounding EN sets the
LTC4310 in a near-zero current mode.
After the LTC4310 exits POR, STOP bit and bus idle detector
circuitry monitors the logic state of its own SDA and SCL
bus and of the other I2C bus in the system via RXP and
RXN. When a STOP bit or bus idle occurs simultaneously
on both I2C buses, the LTC4310 activates its SDA and SCL
drivers, logic detection circuitry and rise time accelerators
and drives READY low.
The stuck bus timer and recovery circuitry disable the
SDA and SCL driver, logic detection circuitry and rise
time accelerators if the bus is low for 37ms. A stuck bus
also causes READY to be released high. If the stuck bus
releases high, the I2C driver and accelerator circuitry are
reactivated when a STOP bit or bus idle occurs simultaneously on both I2C buses, as previously described.
431012f
LTC4310-1/LTC4310-2
Operation
3.3V
C1
0.01µF
R1
7.5k
R3
10k
READY
TXP
R2
7.5k
1
10/100Base-TX
ETHERNET
TRANSFORMER
LTC4310-1
VCC
EN
CBUS = 40pF
SCL1
µP
SDA
TXN
SCL
RXP
15
3
14
6
READY
RXP
16
11
IS0LATED
5V
C4
0.01µF
R4
10k
R5
7.5k
R6
7.5k
LTC4310-1
C3
0.01µF
VCC
EN
RXN
SDA
TXP
SCL
CBUS = 80pF
SCL2
SLAVE#1 . . . SLAVE#4
SLAVE
7
GND RXN
C2
0.01µF
8
9
TXN GND
431012 F01
EPF8119S
Figure 1. The LTC4310-1 in a Transformer Isolated Application
431012f
LTC4310-1/LTC4310-2
Applications Information
SDA, SCL Bus Pull-Up Resistor Value Selection
When the SDA (or SCL) bus is rising between 0V and
0.35 • VCC, the LTC4310 controls the bus rise rate to
(0.35 • VCC)/900ns for the LTC4310-1 and to (0.35 • VCC)/
300ns for the LTC4310-2. Users must quantify their
parasitic bus capacitance, CBUS, and choose a bus pullup resistor, RBUS, based on their bus pull-up supply
voltage and maximum bus switching frequency to ensure that each bus rises faster than the controlled rise
rate. For bus frequencies up to 100kHz, choose the
LTC4310-1 and refer to Figure 2 for the maximum pull-up
resistance to use. For bus frequencies between 100kHz
and 400kHz, choose the LTC4310-2 and refer to Figure 3
for the maximum pull-up resistance to use. Be sure to
include worst-case resistor tolerance when selecting
resistor value.
Rise Time Accelerators
The LTC4310’s rise time accelerator circuitry on the
SDA and SCL lines turns on during rising edges to
18
18
16
16
14
14
VCC = 5V
12
RBUS(MAX) (kΩ)
RBUS(MAX) (kΩ)
reduce the bus rise time. When the bus has risen
above 0.45 • VCC, the LTC4310 turns on a strong,
slew-limited pull-up current, I BOOST, to help even
heavily loaded buses meet the rise time specifications. See the Typical Performance Characteristics section for the rise time accelerator pull-up
current as a function of temperature and bus
capacitance. When either the bus has risen above
(VCC – 1V) or 300ns after the pull-up current has
turned on (whichever comes first), the LTC4310
deactivates its pull-up current to deter fighting
with the subsequent falling edge. Users must
ensure that the bus pull-up supply voltage VBUS ≥
VCC, so that the accelerators do not overdrive the
SDA, SCL bus and source current into VBUS. The rise
time accelerators are deactivated during start-up,
thermal shutdown, shutdown and after disconnection due to a stuck bus or failure to receive a transmission within 4.6ms.
VCC = 3.3V
10
8
6
12
6
4
2
2
1
10
100
CBUS(MAX) (pF)
1000
431012 F02
Figure 2. Maximum SDA,SCL Bus Pull-Up Resistor Value as a
Function of Parasitic Bus Capacitance for the LTC4310-1
VCC = 3.3V
8
4
0
VCC = 5V
10
0
1
10
100
CBUS(MAX) (pF)
1000
431012 F03
Figure 3. Maximum SDA,SCL Bus Pull-Up Resistor Value as
a Function of Parasitic Bus Capacitance for the LTC4310-2
431012f
10
LTC4310-1/LTC4310-2
Applications Information
Bus Rising Edge Waveform
Start-Up, Data and Clock Hot Swap Circuitry
When all external pull-downs on SCL1 (Figure 1) turn off,
the SCL1 rising waveform will resemble that shown in
Figure 4. The LTC4310-1 senses that SCL1 is rising and
transmits a message to the other LTC4310-1 to release
SCL2 high. During the transmission, the first LTC4310-1
also drives SCL1 to 0.35V, so that when the transmission
is complete, both buses will rise simultaneously from
0.35V at a rate of (0.35 • VCC)/900ns. This functionality
minimizes the effective skew between the two buses. When
SCL1 reaches 0.35 • VCC, the LTC4310-1 deactivates its
rise rate regulation circuitry. The bus then rises with a
time constant of (RBUS • CBUS) until it reaches 0.45 • VCC,
at which point the IBOOST rise time accelerator pull-up
current is activated.
The LTC4310 contains power-on reset (POR) circuitry that
sets the data and clock pins in a high impedance state and
deactivates the transmit circuitry until the EN voltage is
high, the device is not in thermal shutdown and the VCC
voltage is above 2.4V. After the LTC4310 exits the POR
state, it activates its transmit circuitry and communicates
its SDA, SCL logic states across the barrier to the other
LTC4310 via its TXP and TXN pins.
Figure 5 shows SCL1 and SCL2 for an entire 100kHz
switching cycle. Because the LTC4310-1 regulates the bus
rise rate to (0.35 • VCC)/900ns, the 5V bus signal rises
more quickly than the 3.3V bus signal. Both buses reach
(0.35 • VCC) in approximately 900ns, so the effective skew
between the buses is nearly zero. The LTC4310-2 functions
the same as the LTC4310-1, except the controlled rise rate
is limited to (0.35 • VCC)/300ns.
The receive circuitry remains deactivated for an additional
900µs after the LTC4310 exits POR. The 900µs filter time is
required for the LTC4310 to charge its RXP and RXN pins
to their DC bias voltage, assuming a 0.01µF common-mode
noise filtering capacitor at the center-tap of the secondary
side of the external transformer. When the filter time has
elapsed, the LTC4310 activates its receive circuitry and
decodes the messages it receives on its RXP and RXN
pins, registering the logic state of the remote I2C bus.
When both the local and remote two-wire buses are “quiet”
(i.e., no data transactions are occurring on either bus), the
LTC4310 then drives its READY pin low to indicate that it
has linked the logic state of the local I2C bus with the logic
state of the remote I2C bus. This means that the LTC4310
will now drive its SDA and SCL pins to the logic state of the
remote I2C bus, as specified by the messages it receives
on RXP and RXN. The LTC4310 considers a two-wire bus
SCL2
RISE TIME
ACCELERATOR
ACTIVE
1V/DIV
SCL1
1V/DIV
BUS RC
SCL1 SET TO 0.35V
DURING TX
dV/dt =
0.35 • VCC
900 ns
200ns/DIV
431012 F04
Figure 4. SCL1 Rising Waveform of SCL1
for Application Circuit Shown in Figure 1
2µs/DIV
431012 F05
Figure 5. 100kHz SCL Waveforms for
Application Circuit Shown in Figure 1
431012f
11
LTC4310-1/LTC4310-2
Applications Information
quiet if it has been idle high for at least 115µs, or if a STOP
bit has occurred and both data and clock have remained
high since the STOP bit. This functionality makes the
LTC4310 ideal for hot-swapping cards into and out of a
live I2C system. The threshold voltages for the STOP bit
and bus idle comparators are 0.5 • VCC.
Stuck Bus Disconnect and Recovery
An internal timer runs whenever SDA, SCL or both are low.
The timer is only reset when both SDA and SCL are high. If
the timer does not reset within 37ms, the LTC4310 assumes
the bus is stuck low. Accordingly, it ceases driving its SDA
and SCL pins and transmits a special message across the
barrier to inform the other LTC4310. Upon receiving this
message, the other LTC4310 also ceases driving its SDA
and SCL pins. At least 40µs after determining the bus
is stuck low, the LTC4310 generates up to sixteen clock
cycles on SCL in an attempt to make the slave release
the SDA line. The LTC4310 stops issuing clocks when the
SDA line releases high, or after sixteen cycles, whichever
comes first. Once the clock pulses have completed, the
LTC4310 issues a STOP bit on SDA and SCL to reset all
devices on the bus.
The LTC4310 reactivates its amplifiers and rise time accelerators when the bus releases high and a STOP bit or
bus idle occurs on both the local and isolated buses, as
previously described in the Start-Up, Data and Clock Hot
Swap Circuitry section. The stuck bus disconnect and recovery circuitry is disabled when the LTC4310 is in UVLO,
thermal shutdown and low current shutdown.
Transmit and Receive Circuitry
Transmissions occur on the TXP and TXN pins whenever
the externally driven SDA or SCL logic state changes – in
other words, transmissions are event driven. In addition,
if SDA and SCL do not change state for 1.15ms, the
LTC4310 retransmits the logic state. The TXP and TXN pins
are driven in a pseudo differential fashion. Both pins are
driven to ground when inactive and are driven to 1.25V
(typical) in matched sets of alternating 35ns pulses to send
information across the barrier to the other LTC4310.
The LTC4310 receives and decodes the pulses sent by the
other LTC4310 on its RXP and RXN pins. Assuming the
start-up sequence previously described has been com-
12
pleted, the LTC4310 drives its SDA and SCL lines to the
logic state dictated by the decoded RXP and RXN signals.
The LTC4310 rejects RXP and RXN signals having less
than 500mV magnitude to provide noise immunity against
common-mode transients.The parasitic capacitances of the
LTC4310’s RXP and RXN pins and their associated board
traces form a capacitive divider with the transmit/receive
coupling capacitors, as shown in Figure 6. To guarantee
robust communications, minimize the parasitic capacitance
CPAR by minimizing the trace length from the coupling
capacitors to the RXP and RXN pins and choose coupling
capacitor values, CRXP and CRXN, that are at least ten
times larger than CPAR.
CRXP
≥47pF
CRXN
≥47pF
CPAR1
4.7pF
LTC4310
RXP
RXN
CPAR2
4.7pF
GND
431012 F06
Figure 6. Parasitic Trace and Pin Capacitances
Form a Capacitive Divider with CRXP and CRXN.
Ensure CRXP, CRXN ≥ 10 • CPAR
If the LTC4310 has not received a message in 4.6ms, it
assumes there is a communication problem and ceases
driving its SDA and SCL pins. It also transmits a special
message to the other LTC4310 to inform it that it is no
longer driving its SDA and SCL bus. Upon receiving this
message, the other LTC4310 also ceases driving its SDA and
SCL pins. Once the communication problem is resolved,
both LTC4310’s reactivate their amplifiers and rise time
accelerators after a STOP bit or bus idle has occurred on
both buses, as previously described in the Start-Up, Data
and Clock Hot Swap Circuitry section.
Thermal Shutdown
If the die temperature of the LTC4310 exceeds 150°C, the
LTC4310 enters a thermal shutdown mode. It sets TXP
and TXN to a high impedance state, ceases driving SDA
and SCL, and ignores the signals on RXP and RXN. When
the temperature drops back below 130°C, the LTC4310
goes through the POR sequence previously described.
431012f
LTC4310-1/LTC4310-2
Applications Information
Once a STOP bit or bus idle occurs on both the local and
isolated buses, the LTC4310 reactivates its buffers and
rise time accelerators.
READY Digital Output
The READY pin provides a digital output flag that pulls
low to indicate that the LTC4310 is driving its SDA and
SCL pins with the logic state information it is receiving on
its RXP and RXN pins from the other LTC4310. READY is
driven by an N-channel MOSFET open-drain pull-down that
is capable of sinking 4mA while holding 0.4V maximum.
The pull-down turns off whenever the LTC4310 is not
driving its SDA and SCL pins—during start-up, thermal
shutdown, low current shutdown and after disconnection
due to a stuck bus or failure to receive a transmission
within 4.6ms. Connect a resistor to the bus pull-up supply
to provide the pull-up.
Design Example: High Voltage Isolation Using an
Inexpensive Ethernet Transformer
Figure 1 shows the LTC4310-1 providing I2C communications between two buses whose ground voltages can
3.3V
C1
0.01µF
R1
4.3k
R3
10k
READY
TXP
R2
4.3k
1
10/100Base-TX
ETHERNET
TRANSFORMER
LTC4310-2
VCC
EN
CBUS = 40pF
SCL1
µP
SDA
TXN
SCL
RXP
differ up to 1500V. An EPF8119S Ethernet transformer is
used to bridge the isolation barrier. The left I2C bus connects to the LTC4310-1 and two other devices, resulting
in a bus parasitic capacitance of 40pF in this example
set-up. Referring to the VCC = 3.3V curve in Figure 2,
7.5k pull-up resistors are chosen for R1 and R2. The right
I2C bus connects to another LTC4310-1 and four slave
devices, resulting in a bus parasitic capacitance of 80pF.
Referring to the VCC = 5V curve in Figure 2, 7.5k pull-up
resistors are also chosen for R5 and R6. Standard 5%
resistors are used.
Sudden changes in the ground differential across the
isolation barrier can be effectively resisted by tying the
center tap of the receive side of the transformer to the
local ground through a 0.01µF capacitor, as shown by
capacitors C2 and C3.
Figure 7 shows the same application as Figure 1, but with
each LTC4310-1 replaced by an LTC4310-2, so that the
bus can switch at frequencies up to 400kHz. To meet the
requirements shown in the curves of Figure 3, R1 and R2
are changed from 7.5k to 4.3k, and R5 and R6 are changed
from 7.5k to 3.3k.
15
3
14
6
READY
RXP
16
11
IS0LATED
5V
C4
0.01µF
R4
10k
R5
3.3k
R6
3.3k
LTC4310-2
C3
0.01µF
VCC
EN
RXN
SDA
TXP
SCL
CBUS = 80pF
SCL2
SLAVE#1 . . . SLAVE#4
SLAVE
7
GND RXN
C2
0.01µF
8
9
TXN GND
431012 F07
EPF8119S
Figure 7. The LTC4310-2 in a 400kHz Application
431012f
13
LTC4310-1/LTC4310-2
Applications Information
Typical Applications
Figure 8 shows the LTC4310-1 providing I2C communications between an I2C bus referenced to system ground and
an I2C bus using –5V for its ground reference. Ceramic
coupling capacitors, C1-C5, are used to bridge the isolation
barrier. This circuit is recommended for ground isolation
voltages less than 100V and is limited by the voltage rating
of C1-C5. Higher voltage ceramic capacitors may be used
to achieve higher isolation voltages. Because the LTC4310
uses a pseudo-differential transmit scheme, capacitor C5
must be connected between ground and –5V to provide a
return path for the transmitted current.
Figure 9 shows the LTC4310-1 in an application circuit
using its zero current shutdown mode. A microprocessor
only activates the left LTC4310-1 when it needs to com-
3.3V
C6
0.01µF
R1
5.1k
R2
5.1k
Figure 10 shows the LTC4310-1 in a two-wire bus Hot Swap
application. Using a staggered connector, make EN the
shortest length pin to ensure that the transients associated
with hot swapping have settled before the LTC4310-1 can
be enabled. After connection is complete, a master on the
backplane may drive EN high to bring the LTC4310-1 out
of shutdown mode and into normal operation. Due to its
STOP bit and bus idle detection circuitry, the LTC4310-1’s
driver circuitry is not activated until transactions on both
buses are complete.
C7
0.01µF
–5V
R3
10k
C1
VCC
TXP
LTC4310-1
CBUS = 100pF
municate with the isolated I2C bus. Because the LTC4310-1
contains a STOP bit and bus idle detection circuitry, there
is no danger of connecting in the middle of a message
when the microprocessor asynchronously reenables the
LTC4310-1.
SDA
SCL
TXN
READY
EN
RXP
C2
C3
C4
RXN
GND
R4
10k
VCC
R5
10k
R6
10k
RXP
LTC4310-1
RXN
SDA
SCL
TXP
READY
EN
CBUS = 30pF
TXN
C5
GND
431012 F08
–5V
C1 TO C5 = 47pF, 100V
Figure 8. Low Voltage I2C Isolation Between a Ground Referenced Bus and a –5V Referenced Bus
431012f
14
LTC4310-1/LTC4310-2
Applications Information
5V
C6
0.01µF
R1
3.3k
R2
3.3k
C7
0.01µF
–5V
R3
10k
C1
VCC
TXP
LTC4310-1
CBUS = 200pF
µP
SDA
SCL
TXN
READY
EN
RXP
OFF ON
R4
10k
VCC
R5
5.1k
EN
RXP
LTC4310-1
C2
RXN
C3
TXP
C4
RXN
READY
SDA
SCL
CBUS = 150pF
SLAVE#1 . . . SLAVE#N
TXN
GND
R6
5.1k
GND
C5
431012 F09
–5V
C1 TO C5 = 47pF, 100V
Figure 9. The LTC4310-1 in a Zero Current Shutdown Application
BACKPLANE
CONNECTOR
CARD
CONNECTOR
I/O PERIPHERAL CARD
BACKPLANE
5V
C6
0.01µF
R1
2k
R2
2k
R3
10k
C1
VCC
TXP
LTC4310-1
SDA
C
= 400pF
SCL BUS
READY
EN
R7
100k
SDA
SCL
TXN
READY
EN
RXP
R4
6.8k
VCC
C2
C3
C4
RXN
GND
3.3V
C7
0.01µF
R5
6.8k
R6
10k
RXP
LTC4310-1
RXN
SDA
SCL
TXP
READY
EN
CBUS = 50pF
SDA2
SCL2
READY2
EN2
TXN
C5
GND
C1 TO C5 = 47pF, 100V
431012 F10
Figure 10. The LTC4310-1 in an I2C Hot-Swapping Application
431012f
15
LTC4310-1/LTC4310-2
Applications Information
LTC4310 Compatibility with Other LTC Bus Buffers
The LTC4310 cannot be used on the same I2C bus with the
LTC4300A-1, LTC4303 or LTC4307. During rising edges,
the rise time accelerators of these buffers turn on before
the LTC4310 disables its rise rate regulation circuitry,
resulting in nonmonotonic bus edges.
The LTC4310-1 is compatible with the LTC4301 and
LTC4301L. It is also compatible with the LTC4302, LTC4304,
LTC4305 and LTC4306, provided that the rise time accelerators of these buffers are permanently disabled. All of the
previously mentioned buffers are incompatible with the
LTC4310-2 because the compensation networks of these
buffers cause the bus to rise more slowly than (0.35 •
VCC)/300ns, therefore the LTC4310-2 would not be able
to control the bus rise rate.
LTC4310-1 Compatibility with LTC4310-2
In a typical application such as shown in Figure 1, an
LTC4310-1 can be used on one bus and an LTC4310-2 can
be used on the other, provided that the bus pull-up resistors connected to the LTC4310-1 meet the requirements
of Figure 2, and the bus pull-up resistors connected to the
LTC4310-2 meet the requirements of Figure 3. However,
the bus switching frequency is limited by the rise rate
regulation circuitry of the LTC4310-1. In addition, significant
skew is introduced on the rising edges due to the large
difference in the controlled rise rates of the two buses. For
this reason, it is recommended to use two LTC4310-1’s
in SMBus and standard mode I2C applications and to use
two LTC4310-2’s in fast mode I2C applications.
The LTC4310-1 cannot be used on the same physical I2C
bus with the LTC4310-2, because the LTC4310-1’s rise
rate regulation circuitry controls the bus rise rate to (0.35
• VCC)/900ns, therefore the LTC4310-2 would not be able
to control the bus rise rate.
Using the LTC4310-1 at Frequencies Above 100kHz
Users who implement custom two-wire buses may use the
LTC4310-1 at bus frequencies above 100kHz provided that
all other devices on the bus can tolerate the approximately
1µs bus rise times resulting from the LTC4310-1’s bus rise
rate regulation circuitry.
431012f
16
LTC4310-1/LTC4310-2
Typical Applications
Transformer Selection Guide
are inexpensive and work very well in this application for
isolation voltages up to 1500V. For applications requiring
4000V isolation, the Würth Electronics Midcom 749014012
transformer is recommended.
As shown in Figure 1, a transformer passes transmit and
receive signals between the two LTC4310’s. The transmit
signals have 1.25V magnitude and 35ns pulse width. The
receive circuitry has an equivalent input impedance of
16.5kΩ and can receive differential signals ranging from
0.875V to 1.55V. To meet these requirements, choose a
transformer having a magnetizing inductance ranging
from 50µH to 350µH, a 1:1 turns ratio and a maximum
insertion loss of –1.5dB. For optimal common mode noise
rejection, choose a center-tapped transformer and connect
the center tap on the receiving side to local ground using a
0.01µF capacitor. Ringing at the LTC4310’s RXP and RXN
pins can effectively be damped by inserting 50Ω series
resistors between each LTC4310’s TXP and TXN pins and
the corresponding transformer primary windings.
RF Radiated Emissions
The LTC4310 evaluation board passes CISPR22 Class B
requirements for radiated emissions. The results of
CISPR22 testing are shown in the evaluation board manual.
To reduce radiated emission levels further, enclose the
LTC4310 application circuit in a shielded enclosure.
Common Mode Transient Immunity
The LTC4310 has high immunity to common mode transients. This is tested by applying a square voltage pulse
having very fast edges between the isolated grounds. The
LTC4310 passes 20kV/us edges without corruption of the
I2C bus logic states.
Table 1 shows a recommended list of transformers for use
with the LTC4310. 10/100BaseTX Ethernet transformers
Table 1. LTC4310 Recommended Transformers
FORM FACTOR (mm)
MANUFACTURER
PART NUMBER
ISOLATION
VOLTAGE
x
y
z
TURNS
RATIO
CENTER
TAP
OPERATING
TEMPERATURE
PCA Electronics
EPF8119S
1500VRMS
10.41
12.45
5.84
1:1
Yes
0°C TO 70°C
EPF8119SE
1500VRMS
10.2
12.7
5.96
1:1
Yes
–40°C TO 85°C
Pulse
E5017
1500VRMS
9.4
12.7
5.08
1:1
Yes
0°C TO 70°C
Würth Electronics
Midcom
000-7090-37R-LF1
1500VRMS
9.4
12.95
5.33
1:1
Yes
–40°C TO 85°C
749014012
4000VRMS
17
24.55
10.85
1:1
Yes
0°C TO 70°C
431012f
17
LTC4310-1/LTC4310-2
Package Description
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 ± 0.10
10
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
5
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
0.200 REF
1
0.75 ±0.05
0.00 – 0.05
(DD) DFN 1103
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
431012f
18
LTC4310-1/LTC4310-2
Package Description
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.497 ± 0.076
(.0196 ± .003)
REF
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.18
(.007)
SEATING
PLANE
1.10
(.043)
MAX
0.86
(.034)
REF
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS) 0307 REV E
431012f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4310-1/LTC4310-2
Typical Application
Breaking Ground Loops Using Capacitors
3.3V
C6
0.01µF
R1
5.1k
R2
5.1k
R3
10k
C1
VCC
TXP
LTC4310-1
CBUS = 100pF
5V
C7
0.01µF
SDA
SCL
TXN
READY
EN
RXP
R4
10k
VCC
C2
RXN
R6
10k
RXP
LTC4310-1
RXN
SDA
SCL
TXP
READY
EN
C3
C4
R5
10k
CBUS = 20pF
TXN
GND
GND
C5
431012 TA02
C1 TO C5 = 47pF, 100V
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC4300A-1/LTC4300A-2/ Hot-Swappable 2-Wire Bus Buffers
LTC4300A-3
LTC4300A–1: Bus Buffer with READY and ENABLE,
LTC4300A–2: Dual Supply Bus Buffer with VCC2 and ACC,
LTC4300A–3: Dual Supply Bus Buffer with VCC2 and ENABLE
LTC4301
Supply Independent Hot-Swappable 2-Wire
Bus Buffer
Supply Independent
LTC4302-1/LTC4302-2
Addressable 2-Wire Bus Buffer
Address Expansion, GPIO, Software Controlled
LTC4303/LTC4304
Hot-Swappable 2-Wire Bus Buffer with Stuck
Bus Recovery
Provides Automatic Clocking to Free Stuck I2C Busses
LTC4305/LTC4306
2- or 4-Channel, 2-Wire Bus Multiplexers
with Capacitance Buffering
Two or Four Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time
Accelerators, Fault Reporting, ±10kV HBM ESD Tolerance
LTC4307
Low Offset Hot-Swappable 2-Wire Bus Buffer
with Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time
Accelerators, ±5kV HBM ESD Tolerance
LTC4307-1
High Definition Multimedia Interface (HDMI)
Level Shifting
2-Wire Bus Buffer, 60mV Buffer Offset, 3.3V to 5V Level Shifting, ±5kV HBM
ESD Tolerance
LTC4308
Low Voltage Level Shifting Hot-Swappable
2-Wire Bus Buffer with Stuck Bus Recovery
–200mV Offset In-Out/+300mV Offset Out-In, 0.9V to 5.5V Level Shifting,
30ms Stuck Bus Disconnect and Recovery, Output Side Rise Time
Accelerators, ±6kV HBM ESD Tolerance
LTC4309
Level Shifting Low Offset Hot-Swappable
2-Wire Bus Buffer with Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time
Accelerators, 1.8V to 5V Level Shifting, ±5kV HBM ESD Tolerance
LTC4311
I2C/SMBus Rise Time Accelerator
Strong Slew Limited Current Source, Wide 1.6V to 5.5V Supply Range, Auto
Detect Low Power Standby, Low <5µA Supply Shutdown Current, ±8kV HBM
ESD Tolerance
431012f
20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT 0410 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2010