ON NCP6121 Dual output 3 phase 1/0 phase controller Datasheet

NCP6121
Dual Output 3 Phase +1/0
Phase Controller with
Single SVID Interface for
Desktop and Notebook CPU
Applications
The NCP6121 dual output three plus one phase buck solution is
optimized for Intel VR12 compatible CPUs. The controller combines
true differential voltage sensing, differential inductor DCR current
sensing, input voltage feed−forward, and adaptive voltage positioning
to provide accurately regulated power for Desktop applications. The
control system is based on Dual−Edge pulse−width modulation
(PWM) combined with DCR current sensing providing the fastest
initial response to dynamic load events and reduced system cost. It
also sheds to single phase during light load operation and can auto
frequency scale in light load while maintaining excellent transient
performance.
Dual high performance operational error amplifiers are provided to
simplify compensation of the system. Patented Dynamic Reference
Injection further simplifies loop compensation by eliminating the need
to compromise between closed−loop transient response and Dynamic
VID performance. Patented Total Current Summing provides highly
accurate current monitoring for droop and digital current monitoring.
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MARKING
DIAGRAM
NCP6121
AWLYYWWG
1 52
QFN−52
CASE 485BE
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
Features
• Meets Intel VR12 and IMVP7 Specifications
• Current Mode Dual Edge Modulation for Fastest Initial Response to
•
•
•
•
•
•
•
•
•
•
•
Transient Loading
Dual High Performance Operational Error Amplifier
One Digital Soft Start Ramp for Both Rails
Dynamic Reference Injection
Accurate Total Summing Current Amplifier
DAC with Droop Feed−forward Injection
Dual High Impedance Differential Voltage and Total
Current Sense Amplifiers
Phase−to−Phase Dynamic Current Balancing
“Lossless” DCR Current Sensing for Current Balancing
Summed Thermally Compensated Inductor Current
Sensing for Droop
True Differential Current Balancing Sense Amplifiers
for Each Phase
Adaptive Voltage Positioning (AVP)
© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. 2
• Switching Frequency Range of 200 kHz – 1.0 MHz
• Startup into Pre−Charged Loads While Avoiding False
•
•
•
•
•
•
•
OVP
Power Saving Phase Shedding
Vin Feed Forward Ramp Slope
Pin Programming for Internal SVID parameters
Over Voltage Protection (OVP) and Under Voltage
Protection (UVP)
Over Current Protection (OCP)
Dual Power Good Output with Internal Delays
These Devices are Pb−Free and are RoHS Compliant
Applications
• Desktop and Notebook Processors
1
Publication Order Number:
NCP6121/D
NCP6121
BLOCK DIAGRAM FOR NCP6121
Figure 1. Block Diagram
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2
NCP6121
DIFFOUT
VSN
TRBST
FB
COMP
ILIM
DROOP
CSCOMP
CSSUM
IOUT
CSREF
NC
NC
51
50
49
48
47
46
45
44
43
42
41
40
Pin 1 Indicator
52
NCP6121, QFN52 SINGLE ROW PIN CONFIGURATIONS
VSP
1
39
CSN2
TSENSE
2
38
CSP2
VRHOT#
3
37
CSN3
SDIO
4
36
CSP3
SCLK
5
35
CSN1
ALERT#
6
34
CSP1
33
DRON
NCP6121
(Not to Scale)
FLAG/GND (Pin 53)
26
VBOOTA
CSNA
27
25
13
CSPA
TSENSEA
24
PWMA/IMAXA
CSSUMA
28
23
12
IOUTA
VRMP
22
IMAX
CSCOMPA
29
21
11
DROOPA
ROSC
20
PWM2
ILIMA
30
19
10
COMPA
VCC
18
PWM3/VBOOT
TRBSTA
31
17
9
DIFFOUTA
ENABLE
16
PWM1/ADDR
FBA
32
15
8
VSPA
VR_RDYA
14
7
VSNA
VR_RDY
Figure 2. Pinout (Top View)
NCP6121 QFN52 SINGLE ROW PIN DESCRIPTIONS
Pin
No.
Symbol
1
VSP
2
TSENSE
3
VR_HOT#
Description
Non−inverting input to the core differential remote sense amplifier.
Temp Sense input for the multiphase converter
Thermal logic output for over temperature.
4
SDIO
Serial VID data interface.
5
SCLK
Serial VID clock.
6
ALERT#
Serial VID ALERT#.
7
VR_RDY
Open drain output. High indicates that the core output is regulating.
8
VR_RDYA
Open drain output. High indicates that the aux output is regulating.
9
ENABLE
Logic input. Logic high enables both outputs and logic low disables both outputs.
10
VCC
11
ROSC
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground.
A resistance from this pin to ground programs the oscillator frequency. This pin supplies a trimmed output
voltage of 2 V.
12
VRMP
Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used to control
the ramp of PWM slope
13
TSENSEA
14
VSNA
Inverting input to the aux differential remote sense amplifier
15
VSPA
Non−inverting input to the aux differential remote sense amplifier
Temp Sense input for the single phase converter
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3
NCP6121
NCP6121 QFN52 SINGLE ROW PIN DESCRIPTIONS
Pin
No.
Symbol
16
FBA
17
DIFFOUTA
18
TRBSTA
Compensation pin for aux rail load transient boost.
19
COMPA
Output of the aux error amplifier and the inverting input of the PWM comparator for aux output
20
ILIMA
Over current shutdown threshold setting for aux output. A resistor to CSCOMPA sets the threshold.
21
DROOPA
Used to program droop function for aux output. It’s connected to the resistor divider placed between
CSCOMPA and CSREFA.
22
CSCOMPA
23
IOUTA
24
CSSUMA
25
CSPA
Non−Inverting input to aux current sense amplifier
26
CSNA
Inverting input to aux current sense amplifier
27
VBOOTA
VBOOTA Voltage input pin. Set to adjust the aux boot−up voltage
28
PWMA /
IMAXA
Aux PWM output to gate driver. Also as ICC_MAXA input pin for aux rail. During start up it is used to program ICC_MAXA with a resistor to ground
29
IMAX
ICC_MAX Input Pin for core rail. During start up it is used to program ICC_MAX with a resistor to ground
30*
PWM2
Phase 2 PWM output only. Pull to VCC will configure as 2−phase operation.
31
PWM3 /
VBOOT
Phase 3 PWM output. Also as VBOOT input pin to adjust the core rail boot−up voltage. During start up it is
used to program VBOOT with a resistor to ground.
32
PWM1 /
ADDR
Phase 1 PWM output. Also as Address program pin. A resistor to ground on this pin programs the SVID
address of the device.
33
DRON
Bidirectional gate drive enable for core output.
34
CSP1
Non−inverting input to current balance sense amplifier for phase 1
35
CSN1
Inverting input to current balance sense amplifier for phase 1
36
CSP3
Non−inverting input to current balance sense amplifier for phase 3
37
CSN3
Inverting input to current balance sense amplifier for phase 3
38
CSP2
Non−inverting input to current balance sense amplifier for phase 2
39*
CSN2
Inverting input to current balance sense amplifier for phase 2
40
NC
No connection
41
NC
No connection
42
CSREF
43
IOUT
44
CSSUM
45
CSCOMP
46
DROOP
47
ILIM
48
COMP
49
FB
50
TRBST
51
VSN
52
DIFFOUT
53
FLAG / GND
Description
Error amplifier voltage feedback for aux output
Output of the aux differential remote sense amplifier
Output of total current sense amplifier for aux output
Total output current monitor for aux output
Inverting input of total current sense amplifier for aux output
Total output current sense amplifier reference voltage input.
Total output current monitor for core output.
Inverting input of total current sense amplifier for core output.
Output of total current sense amplifier for core output.
Used to program droop function for core output. It’s connected to the resistor divider placed between
CSCOMP and CSREF summing node.
Over current shutdown threshold setting for core output. Resistor to CSCOMP to set threshold.
Output of the error amplifier and the inverting inputs of the PWM comparators for the core output.
Error amplifier voltage feedback for core output
Compensation pin for core rail load transient boost.
Inverting input to the core differential remote sense amplifier.
Output of the core differential remote sense amplifier.
Power supply return (QFN Flag)
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NCP6121
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
VMAX
VMIN
Unit
COMP,COMPA
VCC + 0.3 V
−0.3 V
V
CSCOMP, CSCOMPA
VCC + 0.3 V
−0.3 V
V
VSN
GND + 300 mV
GND – 300 mV
mV
DIFFOUT, DIFFOUTA
VCC + 0.3 V
−0.3 V
V
VR_RDY,VR_RDYA
VCC + 0.3 V
−0.3 V
V
VCC
6.5 V
−0.3 V
V
ROSC
VCC + 0.3 V
−0.3 V
V
IOUT, IOUTA Output
2.0 V
−0.3 V
V
VRMP
+25 V
−0.3 V
V
All Other Pins
VCC + 0.3V
−0.3 V
V
**All signals referenced to GND unless noted otherwise.
THERMAL INFORMATION
Pin Symbol
Symbol
Typ
Unit
RqJA
68
°C/W
TJ
−10 to 125
°C
−10 to 100
°C
°C
Thermal Characteristic
QFN Package, (Note 1)
Operating Junction Temperature Range, (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
TSTG
− 40 to +150
Moisture Sensitivity Level
QFN Package
MSL
1
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
NCP6121 ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
@ 1.3 V
−400
Typ
Max
Unit
400
nA
ERROR AMPLIFIER
Input Bias Current
Open Loop DC Gain
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
Open Loop Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
55
MHz
DVin = 100 mV, G = −10 V/V,
DVout = 1.5 V – 2.5 V,
CL = 20 pF to GND, DC Load =
10k to GND
20
V/ms
Slew Rate
Maximum Output Voltage
ISOURCE = 2.0 mA
3.5
−
−
V
Minimum Output Voltage
ISINK = 2.0 mA
−
−
1
V
VSP, VSPA ,VSN, VSNA = 1.3 V
−400
−
400
nA
VSP Input Voltage Range
−0.3
−
3.0
V
VSN Input Voltage Range
−0.3
−
0.3
V
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current
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NCP6121
NCP6121 ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
DIFFERENTIAL SUMMING AMPLIFIER
−3 dB Bandwidth
Closed Loop DC gain
Droop Accuracy
CL = 20 pF to GND,
RL = 10 kW to GND
12
MHz
VS+ to VS− = 0.5 to 1.3 V
1.0
V/V
CSREF − DROOP = 80 mV
DAC = 0.8 V to 1.2 V
−81.5
−78.5
mV
−300
300
uV
−7.5
7.5
nA
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos), note 3
Input Bias Current
CSSUM = CSSUMA = 1 V
Open Loop Gain
Current Sense Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
10
MHz
Maximum CSCOMP (A) Output Voltage
Isource = 2 mA
CSSUM(A) = CSCOMP(A)
3.5
−
−
V
Minimum CSCOMP(A) Output Voltage
Isink = 2 mA
CSSUM(A) = CSCOMP(A)
−
−
0.15
V
CSP1−3 = CSN1−3 = 1.2 V
CSPA = CSNA = 1.2 V
−50
−100
−
50
100
nA
Common Mode Input Voltage Range
CSPx = CSNx
0
−
2.0
V
Differential Mode Input Voltage Range
CSNx = 1.2 V
−100
−
100
mV
Input Offset Voltage Matching
CSPx = CSNx = 1.2 V,
Measured from the average
−1.5
−
1.5
mV
Current Sense Amplifier Gain
0 V < CSPx – CSNx < 0.1V
5.7
6.0
6.3
V/V
10 mV < CSNx = CSPx < 30m V
−3
3
%
CURRENT BALANCE AMPLIFIER
Input Bias Current
Multiphase Current Sense Gain Matching
−3 dB Bandwidth
8
MHz
INPUT SUPPLY
4.75
5.25
V
43
mA
EN = low
5
mA
VCC rising
4.5
V
Supply Voltage Range
VCC Quiescent Current
EN = high
UVLO Threshold
VCC falling
38
4.1
VCC UVLO Hysteresis
V
160
mV
2.5
mV/ms
Slew Rate Slow
5
mV/ms
Slew Rate Fast
20
mV/ms
AUX Soft Start Slew Rate
2.5
mV/ms
AUX Slew Rate Slow
2.5
mV/ms
AUX Slew Rate Fast
10
mV/ms
DAC SLEW RATE
Soft Start Slew Rate
ENABLE INPUT
External 1k pull−up to 3.3 V
−
Upper Threshold
VUPPER
0.8
Lower Threshold
VLOWER
Enable High Input Leakage Current
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1.0
mA
V
0.3
V
NCP6121
NCP6121 ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
ENABLE INPUT
Total Hysteresis
Enable Delay Time
VUPPER – VLOWER
90
Measure time from Enable
transitioning HI to when DRON
goes high, Vboot is not 0 V
mV
5.0
ms
DRVON
Output High Voltage
Sourcing 500 mA
Output Low Voltage
Sinking 500 mA
Rise/Fall Time
Internal Pull Down Resistance
3.0
V
0.1
V
CL (PCB) = 20 pF,
DVo = 10% to 90%
10
ns
EN = Low
70
kW
IOUT / IOUTA OUTPUT
Ilimit to CSREF
Input Referred Offset Voltage
Output Source Current
Current Gain
−1.5
Ilimit sink current = 80 mA
(IOUTCURRENT) /
(ILIMITCURRENT), RILIM = 20k,
RIOUT = 5.0k, DAC = 0.8 V,
1.25 V, 1.52 V
1.5
mV
800
uA
9.5
10
10.5
200
−
1000
kHz
OSCILLATOR
Switching Frequency Range
3 Phase Operation
RT = 6.98 kW
360
400
440
kHz
Rosc Output Voltage
RT = 6.98 kW
1.95
2.00
2.05
V
CSREF, CSNA
1.9
2.0
2.1
V
VSP(A) rising, DAC = 1.2 V and
1.52 V
150
175
200
mV
OUTPUT OVER VOLTAGE AND UNDER VOLTAGE PROTECTION (OVP & UVP)
Absolute Over Voltage Threshold During Soft Start
Over Voltage Threshold Above DAC
Over Voltage Delay
Under Voltage Threshold Below DAC
VSP(A) rising to PWMx low
VSP(A) falling, (DAC = 1.2 V &
1.52 V)
50
250
Under−voltage Delay
300
ns
350
5
mV
ms
VR12 DAC
System Voltage Accuracy
Droop Feed−Forward Up Current
Droop Feed−Forward Down current
1.0 V ≤ DAC < 1.52 V
0.8V< DAC < 0.995 V
0.25V < DAC < 0.795 V
−0.5
−5
−8
Measured on DROOP, DROOPA
Measured on DROOP, DROOPA
58
19
Droop Feed−Forward Pulse On−Time
65
25
0.5
5
8
%
mV
mV
72
31
mA
0.16
ms
OVERCURRENT PROTECTION (Core Rail)
ILIM Threshold Current (OCP shutdown after 50 ms
delay)
(PS0) Rlim = 20k
9.0
10
11.0
mA
ILIM Threshold Current (immediate OCP shutdown)
(PS0) Rlim = 20k
13.5
15
16.5
mA
ILIM Threshold Current (OCP shutdown after 50 ms
delay)
(PS1, PS2, PS3) Rlim = 20k, N =
number of phases in PS0 mode
10/N
mA
ILIM Threshold Current (immediate OCP shutdown)
(PS1, PS2, PS3) Rlim = 20k, N =
number of phases in PS0 mode
15/N
mA
OVERCURRENT PROTECTION (+1 Rail)
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NCP6121
NCP6121 ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
ILIM Threshold Current (OCP shutdown after 50 ms
delay)
(PS0) Rlim = 20k
8.5
10
11.5
mA
ILIM Threshold Current (immediate OCP shutdown)
(PS0) Rlim = 20k
13.5
15
16.5
mA
ILIM Threshold Current (OCP shutdown after 50 ms
delay)
(PS1, PS2, PS3) Rlim = 20k, N =
phase number in PS0 mode
10
mA
ILIM Threshold Current (Immediate OCP shutdown)
(PS1, PS2, PS3) Rlim = 20k, N =
phase number in PS0 mode
15
mA
OVERCURRENT PROTECTION (+1 Rail)
MODULATORS (PWM COMPARATORS) FOR CORE AND AUX
0% Duty Cycle
COMP voltage when the PWM
outputs remain LO
100% Duty Cycle
COMP voltage when the PWM
outputs remain HI VRMP = 12.0 V
PWM Ramp Duty Cycle Matching
COMP = 2 V, PWM Ton matching
PWM Phase Angle Error
Between adjacent phases
Ramp Feed−forward Voltage range
−
1.3
−
V
2.5
−
V
1
%
−15
15
°
5
20
V
TRBST
TRBST/COMP offset
TRBST Starts Sinking Current
TRBST Sink Capability
350
mV
500
mA
350
mV
500
mA
TRBSTA
TRBSTA/COMPA offset
TRBST Starts Sinking Current
TRBSTA Sink Capability
VR_HOT#
I_VRHOT = −4 mA
Output Low Voltage
Output Leakage Current
High Impedance State
−1.0
−
0.3
V
1.0
mA
TSENSE/TSENSEA
Alert# Assert Threshold
513
mV
Alert# De−assert Threshold
491
mV
VRHOT Assert Threshold
472
mV
VRHOT Rising Threshold
494
TSENSE Bias Current
116
120
mV
124
mA
ADC
Voltage Range
0
2
V
Total Unadjusted Error (TUE)
−1
+1
%
1
LSB
Differential Non−linearity (DNL)
8−bit
Power Supply Sensitivity
+/−1
%
Conversion Time
30
ms
Round Robin
90
ms
VR_RDY, VR_RDYA (POWER GOOD) OUTPUT
IVR_RDY(A) = 4 mA
−
−
External pull−up o f 1 kW to
3.3 V , CTOT = 45 pF, DVo = 10%
to 90%
−
100
Output Low Saturation Voltage
Rise Time
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8
0.3
V
ns
NCP6121
NCP6121 ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
VR_RDY, VR_RDYA (POWER GOOD) OUTPUT
Fall Time
External pull−up of 1 kW to 3.3 V,
CTOT = 45 pF, DVo = 90% to
10%
Output Voltage at Power−up
VR_RDY, VR_RDYA pulled up to
5 V via 2 KW
−
−
1.0
V
Output Leakage Current When High
VR_RDY and VR_RDYA = 5.0 V
−1.0
−
1.0
mA
10
ns
VR_RDY Delay (rising)
DAC = TARGET to VR_RDY
500
VR_RDY Delay (falling)
From OCP or OVP
−
5
−
ms
Output High Voltage
Sourcing 500 mA
VCC –
0.2 V
−
−
V
Output Mid Voltage
No Load, SetPS = 02
1.9
2.0
2.1
V
Output Low Voltage
Sinking 500 mA
−
−
0.7
V
Rise and Fall Time
CL (PCB) = 50 pF,
DVo = GND to VCC
−
10
ns
PWM Pin Source Current
100
mA
PWM Pin Threshold Voltage
3.3
V
Phase Detect Timer
20
ms
ms
PWM OUTPUTS
2/3 PHASE DETECTION
SCLK, SDIO
VIL
Input Low Voltage
VIH
Input High Voltage
VOH
Output High Voltage
RON
Buffer On Resistance (data line,
ALERT#, and VRHOT)
4
13
W
SDIO, SLCK, ALERT
−100
100
mA
4.0
pF
8.3
ns
Leakage Current
.45
0.65
V
V
1.05
Pad Capacitance, (Note 3)
V
VR clock to data delay (Tco), (Note 3)
4
Setup time (Tsu), (Note 3)
7
ns
Hold time (Thld), (Note 3)
14
ns
3. Guaranteed by design or characterization data, not in production test;
Table 1. VR12 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
0
0
0
0
0
0
0
0
OFF
00
0
0
0
0
0
0
0
1
0.25000
01
0
0
0
0
0
0
1
0
0.25500
02
0
0
0
0
0
0
1
1
0.26000
03
0
0
0
0
0
1
0
0
0.26500
04
0
0
0
0
0
1
0
1
0.27000
05
0
0
0
0
0
1
1
0
0.27500
06
0
0
0
0
0
1
1
1
0.28000
07
0
0
0
0
1
0
0
0
0.28500
08
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NCP6121
Table 1. VR12 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
0
0
0
0
1
0
0
1
0.29000
09
0
0
0
0
1
0
1
0
0.29500
0A
0
0
0
0
1
0
1
1
0.30000
0B
0
0
0
0
1
1
0
0
0.30500
0C
0
0
0
0
1
1
0
1
0.31000
0D
0
0
0
0
1
1
1
0
0.31500
0E
0
0
0
0
1
1
1
1
0.32000
0F
0
0
0
1
0
0
0
0
0.32500
10
0
0
0
1
0
0
0
1
0.33000
11
0
0
0
1
0
0
1
0
0.33500
12
0
0
0
1
0
0
1
1
0.34000
13
0
0
0
1
0
1
0
0
0.34500
14
0
0
0
1
0
1
0
1
0.35000
15
0
0
0
1
0
1
1
0
0.35500
16
0
0
0
1
0
1
1
1
0.36000
17
0
0
0
1
1
0
0
0
0.36500
18
0
0
0
1
1
0
0
1
0.37000
19
0
0
0
1
1
0
1
0
0.37500
1A
0
0
0
1
1
0
1
1
0.38000
1B
0
0
0
1
1
1
0
0
0.38500
1C
0
0
0
1
1
1
0
1
0.39000
1D
0
0
0
1
1
1
1
0
0.39500
1E
0
0
0
1
1
1
1
1
0.40000
1F
0
0
1
0
0
0
0
0
0.40500
20
0
0
1
0
0
0
0
1
0.41000
21
0
0
1
0
0
0
1
0
0.41500
22
0
0
1
0
0
0
1
1
0.42000
23
0
0
1
0
0
1
0
0
0.42500
24
0
0
1
0
0
1
0
1
0.43000
25
0
0
1
0
0
1
1
0
0.43500
26
0
0
1
0
0
1
1
1
0.44000
27
0
0
1
0
1
0
0
0
0.44500
28
0
0
1
0
1
0
0
1
0.45000
29
0
0
1
0
1
0
1
0
0.45500
2A
0
0
1
0
1
0
1
1
0.46000
2B
0
0
1
0
1
1
0
0
0.46500
2C
0
0
1
0
1
1
0
1
0.47000
2D
0
0
1
0
1
1
1
0
0.47500
2E
0
0
1
0
1
1
1
1
0.48000
2F
0
0
1
1
0
0
0
0
0.48500
30
0
0
1
1
0
0
0
1
0.49000
31
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10
NCP6121
Table 1. VR12 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
0
0
1
1
0
0
1
0
0.49500
32
0
0
1
1
0
0
1
1
0.50000
33
0
0
1
1
0
1
0
0
0.50500
34
0
0
1
1
0
1
0
1
0.51000
35
0
0
1
1
0
1
1
0
0.51500
36
0
0
1
1
0
1
1
1
0.52000
37
0
0
1
1
1
0
0
0
0.52500
38
0
0
1
1
1
0
0
1
0.53000
39
0
0
1
1
1
0
1
0
0.53500
3A
0
0
1
1
1
0
1
1
0.54000
3B
0
0
1
1
1
1
0
0
0.54500
3C
0
0
1
1
1
1
0
1
0.55000
3D
0
0
1
1
1
1
1
0
0.55500
3E
0
0
1
1
1
1
1
1
0.56000
3F
0
1
0
0
0
0
0
0
0.56500
40
0
1
0
0
0
0
0
1
0.57000
41
0
1
0
0
0
0
1
0
0.57500
42
0
1
0
0
0
0
1
1
0.58000
43
0
1
0
0
0
1
0
0
0.58500
44
0
1
0
0
0
1
0
1
0.59000
45
0
1
0
0
0
1
1
0
0.59500
46
0
1
0
0
0
1
1
1
0.60000
47
0
1
0
0
1
0
0
0
0.60500
48
0
1
0
0
1
0
0
1
0.61000
49
0
1
0
0
1
0
1
0
0.61500
4A
0
1
0
0
1
0
1
1
0.62000
4B
0
1
0
0
1
1
0
0
0.62500
4C
0
1
0
0
1
1
0
1
0.63000
4D
0
1
0
0
1
1
1
0
0.63500
4E
0
1
0
0
1
1
1
1
0.64000
4F
0
1
0
1
0
0
0
0
0.64500
50
0
1
0
1
0
0
0
1
0.65000
51
0
1
0
1
0
0
1
0
0.65500
52
0
1
0
1
0
0
1
1
0.66000
53
0
1
0
1
0
1
0
0
0.66500
54
0
1
0
1
0
1
0
1
0.67000
55
0
1
0
1
0
1
1
0
0.67500
56
0
1
0
1
0
1
1
1
0.68000
57
0
1
0
1
1
0
0
0
0.68500
58
0
1
0
1
1
0
0
1
0.69000
59
0
1
0
1
1
0
1
0
0.69500
5A
http://onsemi.com
11
NCP6121
Table 1. VR12 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
0
1
0
1
1
0
1
1
0.70000
5B
0
1
0
1
1
1
0
0
0.70500
5C
0
1
0
1
1
1
0
1
0.71000
5D
0
1
0
1
1
1
1
0
0.71500
5E
0
1
0
1
1
1
1
1
0.72000
5F
0
1
1
0
0
0
0
0
0.72500
60
0
1
1
0
0
0
0
1
0.73000
61
0
1
1
0
0
0
1
0
0.73500
62
0
1
1
0
0
0
1
1
0.74000
63
0
1
1
0
0
1
0
0
0.74500
64
0
1
1
0
0
1
0
1
0.75000
65
0
1
1
0
0
1
1
0
0.75500
66
0
1
1
0
0
1
1
1
0.76000
67
0
1
1
0
1
0
0
0
0.76500
68
0
1
1
0
1
0
0
1
0.77000
69
0
1
1
0
1
0
1
0
0.77500
6A
0
1
1
0
1
0
1
1
0.78000
6B
0
1
1
0
1
1
0
0
0.78500
6C
0
1
1
0
1
1
0
1
0.79000
6D
0
1
1
0
1
1
1
0
0.79500
6E
0
1
1
0
1
1
1
1
0.80000
6F
0
1
1
1
0
0
0
0
0.80500
70
0
1
1
1
0
0
0
1
0.81000
71
0
1
1
1
0
0
1
0
0.81500
72
0
1
1
1
0
0
1
1
0.82000
73
0
1
1
1
0
1
0
0
0.82500
74
0
1
1
1
0
1
0
1
0.83000
75
0
1
1
1
0
1
1
0
0.83500
76
0
1
1
1
0
1
1
1
0.84000
77
0
1
1
1
1
0
0
0
0.84500
78
0
1
1
1
1
0
0
1
0.85000
79
0
1
1
1
1
0
1
0
0.85500
7A
0
1
1
1
1
0
1
1
0.86000
7B
0
1
1
1
1
1
0
0
0.86500
7C
0
1
1
1
1
1
0
1
0.87000
7D
0
1
1
1
1
1
1
0
0.87500
7E
0
1
1
1
1
1
1
1
0.88000
7F
1
0
0
0
0
0
0
0
0.88500
80
1
0
0
0
0
0
0
1
0.89000
81
1
0
0
0
0
0
1
0
0.89500
82
1
0
0
0
0
0
1
1
0.90000
83
http://onsemi.com
12
NCP6121
Table 1. VR12 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
1
0
0
0
0
1
0
0
0.90500
84
1
0
0
0
0
1
0
1
0.91000
85
1
0
0
0
0
1
1
0
0.91500
86
1
0
0
0
0
1
1
1
0.92000
87
1
0
0
0
1
0
0
0
0.92500
88
1
0
0
0
1
0
0
1
0.93000
89
1
0
0
0
1
0
1
0
0.93500
8A
1
0
0
0
1
0
1
1
0.94000
8B
1
0
0
0
1
1
0
0
0.94500
8C
1
0
0
0
1
1
0
1
0.95000
8D
1
0
0
0
1
1
1
0
0.95500
8E
1
0
0
0
1
1
1
1
0.96000
8F
1
0
0
1
0
0
0
0
0.96500
90
1
0
0
1
0
0
0
1
0.97000
91
1
0
0
1
0
0
1
0
0.97500
92
1
0
0
1
0
0
1
1
0.98000
93
1
0
0
1
0
1
0
0
0.98500
94
1
0
0
1
0
1
0
1
0.99000
95
1
0
0
1
0
1
1
0
0.99500
96
1
0
0
1
0
1
1
1
1.00000
97
1
0
0
1
1
0
0
0
1.00500
98
1
0
0
1
1
0
0
1
1.01000
99
1
0
0
1
1
0
1
0
1.01500
9A
1
0
0
1
1
0
1
1
1.02000
9B
1
0
0
1
1
1
0
0
1.02500
9C
1
0
0
1
1
1
0
1
1.03000
9D
1
0
0
1
1
1
1
0
1.03500
9E
1
0
0
1
1
1
1
1
1.04000
9F
1
0
1
0
0
0
0
0
1.04500
A0
1
0
1
0
0
0
0
1
1.05000
A1
1
0
1
0
0
0
1
0
1.05500
A2
1
0
1
0
0
0
1
1
1.06000
A3
1
0
1
0
0
1
0
0
1.06500
A4
1
0
1
0
0
1
0
1
1.07000
A5
1
0
1
0
0
1
1
0
1.07500
A6
1
0
1
0
0
1
1
1
1.08000
A7
1
0
1
0
1
0
0
0
1.08500
A8
1
0
1
0
1
0
0
1
1.09000
A9
1
0
1
0
1
0
1
0
1.09500
AA
1
0
1
0
1
0
1
1
1.10000
AB
1
0
1
0
1
1
0
0
1.10500
AC
http://onsemi.com
13
NCP6121
Table 1. VR12 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
1
0
1
0
1
1
0
1
1.11000
AD
1
0
1
0
1
1
1
0
1.11500
AE
1
0
1
0
1
1
1
1
1.12000
AF
1
0
1
1
0
0
0
0
1.12500
B0
1
0
1
1
0
0
0
1
1.13000
B1
1
0
1
1
0
0
1
0
1.13500
B2
1
0
1
1
0
0
1
1
1.14000
B3
1
0
1
1
0
1
0
0
1.14500
B4
1
0
1
1
0
1
0
1
1.15000
B5
1
0
1
1
0
1
1
0
1.15500
B6
1
0
1
1
0
1
1
1
1.16000
B7
1
0
1
1
1
0
0
0
1.16500
B8
1
0
1
1
1
0
0
1
1.17000
B9
1
0
1
1
1
0
1
0
1.17500
BA
1
0
1
1
1
0
1
1
1.18000
BB
1
0
1
1
1
1
0
0
1.18500
BC
1
0
1
1
1
1
0
1
1.19000
BD
1
0
1
1
1
1
1
0
1.19500
BE
1
0
1
1
1
1
1
1
1.20000
BF
1
1
0
0
0
0
0
0
1.20500
C0
1
1
0
0
0
0
0
1
1.21000
C1
1
1
0
0
0
0
1
0
1.21500
C2
1
1
0
0
0
0
1
1
1.22000
C3
1
1
0
0
0
1
0
0
1.22500
C4
1
1
0
0
0
1
0
1
1.23000
C5
1
1
0
0
0
1
1
0
1.23500
C6
1
1
0
0
0
1
1
1
1.24000
C7
1
1
0
0
1
0
0
0
1.24500
C8
1
1
0
0
1
0
0
1
1.25000
C9
1
1
0
0
1
0
1
0
1.25500
CA
1
1
0
0
1
0
1
1
1.26000
CB
1
1
0
0
1
1
0
0
1.26500
CC
1
1
0
0
1
1
0
1
1.27000
CD
1
1
0
0
1
1
1
0
1.27500
CE
1
1
0
0
1
1
1
1
1.28000
CF
1
1
0
1
0
0
0
0
1.28500
D0
1
1
0
1
0
0
0
1
1.29000
D1
1
1
0
1
0
0
1
0
1.29500
D2
1
1
0
1
0
0
1
1
1.30000
D3
1
1
0
1
0
1
0
0
1.30500
D4
1
1
0
1
0
1
0
1
1.31000
D5
http://onsemi.com
14
NCP6121
Table 1. VR12 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
1
1
0
1
0
1
1
0
1.31500
D6
1
1
0
1
0
1
1
1
1.32000
D7
1
1
0
1
1
0
0
0
1.32500
D8
1
1
0
1
1
0
0
1
1.33000
D9
1
1
0
1
1
0
1
0
1.33500
DA
1
1
0
1
1
0
1
1
1.34000
DB
1
1
0
1
1
1
0
0
1.34500
DC
1
1
0
1
1
1
0
1
1.35000
DD
1
1
0
1
1
1
1
0
1.35500
DE
1
1
0
1
1
1
1
1
1.36000
DF
1
1
1
0
0
0
0
0
1.36500
E0
1
1
1
0
0
0
0
1
1.37000
E1
1
1
1
0
0
0
1
0
1.37500
E2
1
1
1
0
0
0
1
1
1.38000
E3
1
1
1
0
0
1
0
0
1.38500
E4
1
1
1
0
0
1
0
1
1.39000
E5
1
1
1
0
0
1
1
0
1.39500
E6
1
1
1
0
0
1
1
1
1.40000
E7
1
1
1
0
1
0
0
0
1.40500
E8
1
1
1
0
1
0
0
1
1.41000
E9
1
1
1
0
1
0
1
0
1.41500
EA
1
1
1
0
1
0
1
1
1.42000
EB
1
1
1
0
1
1
0
0
1.42500
EC
1
1
1
0
1
1
0
1
1.43000
ED
1
1
1
0
1
1
1
0
1.43500
EE
1
1
1
0
1
1
1
1
1.44000
EF
1
1
1
1
0
0
0
0
1.44500
F0
1
1
1
1
0
0
0
1
1.45000
F1
1
1
1
1
0
0
1
0
1.45500
F2
1
1
1
1
0
0
1
1
1.46000
F3
1
1
1
1
0
1
0
0
1.46500
F4
1
1
1
1
0
1
0
1
1.47000
F5
1
1
1
1
0
1
1
0
1.47500
F6
1
1
1
1
0
1
1
1
1.48000
F7
1
1
1
1
1
0
0
0
1.48500
F8
1
1
1
1
1
0
0
1
1.49000
F9
1
1
1
1
1
0
1
0
1.49500
FA
1
1
1
1
1
0
1
1
1.50000
FB
1
1
1
1
1
1
0
0
1.50500
FC
1
1
1
1
1
1
0
1
1.51000
FD
http://onsemi.com
15
NCP6121
Table 1. VR12 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
1
1
1
1
1
1
1
0
1.51500
FE
1
1
1
1
1
1
1
1
1.52000
FF
12V
5V
VR12_EN
SVID bus idle
SCLK
SDIO
VSPA
VID PKT
VSP
VID pkt
Status PKT
VSPA
VSP
SVID Alert
VR_RDYA
VR_RDY
Figure 3. Start−Up Timing Diagram
CPU Driving, Single Data Rate
VR Driving, Single Data Rate
SCLK
SCLK
CPU
send
VR
send
VR latch
SDIO
CPU latch
SDIO
TCO _CPU tSU
thld
TCO _CPU
TCO_VR
t SU
thld
Tco_VR = clock to data delay in VR
tsu =T −2*Tfly −Tco_VR
thld =2*Tfly +Tco_VR
Tfly propagation time on Serial VID bus
Tco_CPU = clock to data delay in CPU
tsu =0.5*T −Tco_CPU
thld =0.5*T +Tco_CPU
Figure 4. SVID Timing Diagram
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NCP6121
Table 2. STATE TRUTH TABLE
STATE
VR_RDY(A) Pin
Error AMP
Comp(A)
Pin
POR
0 < VCC < UVLO
N/A
N/A
N/A
Resistive pull
down
Disabled
EN < threshold
UVLO >threshold
Low
Low
Disabled
Low
Start up Delay &
Calibration
EN > threshold
UVLO > threshold
Low
Low
Disabled
Low
DRVON Fault
EN > threshold
UVLO > threshold
DRVON < threshold
Low
Low
Disabled
Resistive pull up
Soft−Start
EN > threshold
UVLO >threshold
DRVON > High
Low
Operational
Active /
No latch
High
Normal Operation
EN > threshold
UVLO >threshold
DRVON > High
High
Operational
Active /
Latching
High
Over Voltage
Low
N/A
DAC +
150 mV
High
Over Current
Low
Operational
Last DAC
Code
Low
VID Code = 00h
Low: if Reg34h:bit0 = 0;
High:if Reg34h:bit0 = 1;
Clamped
Disabled
High,
PWM outputs in
low state
OVP(A) and
UVP(A)
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DRVON PIN
Method of
Reset
Driver must release
DRVON to high
N/A
NCP6121
VCC > UVLO
Controller
POR
Disable
EN = 0
VCC < UVLO
EN = 1
Calibrate
Drive Off
3 . 5 ms and CAL DONE
VDRP > ILIM
NO _ CPU
INVALID VID
Phase
Detect
VCCP >
UVLO and DRON HIGH
Soft Start
Ramp
DAC = Vboot
Soft Start
Ramp
OVP
DAC = VID
VS > OVP
Normal
VR _ RDY
VS > UVP
VS < UVP
UVP
Figure 5. State Diagram
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NCP6121
General
The NCP6121 is a dual output four/three phase plus one phase dual edge modulated multiphase PWM controller designed
to meet the Intel VR12 specifications with a serial SVID control interface. The NCP6121 implements PS0, PS1, PS2 and PS3
power saving states. It is designed to work in notebook, desktop, and server applications.
For Core Rail:
Power Status
PWM Output Operating Mode
PS0
Multi−phase PWM interleaving output
PS1
Single−phase RPM CCM mode (PWM1 only, PWM2~3 stay in Mid)
PS2
Single−phase RPM DCM mode (PWM1 only, PWM2~3 stay in Mid)
PS3
Existing definition is same as PS2
For AUX Rail:
Power Status
PWM Output Operating Mode
PS0
Single−phase RPM output
PS1
Single−phase RPM CCM mode
PS2
Single−phase RPM DCM mode
PS3
Existing definition is same as PS2
VID code change is supported by SVID interface with three options as below:
Option
SVID Command
Code
Feature
Register Address
(Indicating the Slew Rate of VID Code Change)
SetVID_Fast
01h
> 10 mV/ms VID code change
slew rate
24h
SetVID_Slow
02h
= 1/4 of SetVID_Fast VID
code change slew rate
25h
SetVID_Decay
03h
No control, VID code down
N/A
Serial VID
The NCP6121 supports the Intel serial VID interface. It communicates with the microprocessor through three wires (SCLK,
SDIO, ALERT#). The table of supported registers is shown below.
Index
Name
00h
Vendor ID
01h
Product ID
02h
Product
Revision
05h
06h
07h
Description
Access
Default
Uniquely identifies the VR vendor. The vendor ID assigned by Intel to ON Semiconductor is 0x1Ah
R
0x1Ah
Uniquely identifies the VR product. The VR vendor assigns this number.
R
0x51
Uniquely identifies the revision or stepping of the VR control IC. The VR vendor assigns this data.
R
0x0A
Protocol ID
Identifies the SVID Protocol the controller supports
R
0x01
Capability
Informs the Master of the controller’s Capabilities, 1 = supported, 0 = not supported
Bit 7 = Iout_format. Bit 7 = 0 when 1A = 1LSB of Reg 15h. Bit 7 = when Reg 15 FFh =
Icc_Max. Default = 1
Bit 6 = ADC Measurement of Temp Supported = 1
Bit 5 = ADC Measurement of Pin Supported = 0
Bit 4 = ADC Measurement of Vin Supported = 0
Bit 3 = ADC Measurement of Iin Supported = 0
Bit 2 = ADC Measurement of Pout Supported = 1
Bit 1 = ADC Measurement of Vout Supported = 1
Bit 0 = ADC Measurement of Iout Supported = 1
R
0xC7
Generic ID
51h or 31h, depending on the generic
R
51h or
31h
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NCP6121
Index
Name
10h
Status_1
Description
Access
Default
Data register read after the ALERT# signal is asserted. Conveying the status of the
VR.
R
00h
Data register showing optional status_2 data.
R
00h
Data register showing temperature zones the system is operating in
R
00h
11h
Status_2
12h
Temp zone
15h
I_out
8 bit binary word ADC of current. This register reads 0xFF when the output current is
at Icc_Max
R
01h
16h
V_out
8 bit binary word ADC of output voltage, measured between VSP and VSN. LSB size
is 8 mV
R
01h
17h
VR_Temp
8 bit binary word ADC of voltage. Binary format in deg C, IE 100C = 64h. A value of
00h indicates this function is not supported
R
01h
18h
P_out
8 bit binary word representative of output power. The output voltage is multiplied by
the output current value and the result is stored in this register. A value of 00h indicates this function is not supported
R
01h
1Ch
Status 2
Last read
When the status 2 register is read its contents are copied into this register. The format
is the same as the Status 2 Register.
R
00h
21h
ICC_Max
Data register containing the Icc_Max the platform supports. The value is measured on
the ICCMAX pin on power up and placed in this register. From that point on the register is read only.
R
00h
22h
Temp_Max
Data register containing the max temperature the platform supports and the level
VR_hot asserts. This value defaults to 100°C and programmable over the SVID Interface
R/W
64h
24h
SR_fast
Slew Rate for SetVID_fast commands. Binary format in mV/us.
R
0Ah
25h
SR_slow
Slew Rate for SetVID_slow commands. It is 4X slower than the SR_fast rate. Binary
format in mV/us
R
02h
26h
Vboot
The Vboot is programmed using resistors on the Vboot pin which is sensed on power
up. The controller will ramp to Vboot and hold at Vboot until it receives a new SVID
SetVID command to move to a different voltage. Default value = 0, i.e. this occurs if no
resistor is connected to the Vboot pin. IN this case the controller will wait till it gets an
SVID command to set the output voltage., VR12 VID format, IE 97h = 1.0 V
R
00h
30h
Vout_Max
Programmed by master and sets the maximum VID the VR will support. If a higher
VID code is received, the VR should respond with “not supported” acknowledge. VR
12 VID format.
RW
FBh
31h
VID setting
Data register containing currently programmed VID voltage. VID data format.
RW
00h
32h
Pwr State
Register containing the current programmed power state.
RW
00h
33h
Offset
Sets offset in VID steps added to the VID setting for voltage margining. Bit 7 is sign
bit, 0 = positive margin, 1 = negative margin. Remaining 7 BITS are # VID steps for
margin 2s complement.
00h = no margin
01h = +1 VID step
02h = +2 VID steps
Ffh = −1 VID step
Feh = −2 VID steps.
RW
00h
34h
MultiVR
Config
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NCP6121
BOOT VOLTAGE PROGRAMMING
The NCP6121 has a Vboot voltage register that can be
externally programmed for each output. The VBOOTA also
provides a feature that allows the “+1” single phase output
to be disabled and effectively removed from the SVID bus.
If the single phase output is disabled it alters the SVID
address setting table to allow the multi−phase rail to show up
at an even or odd address. See the Boot Voltage Table below.
Table 5. SINGLE SVID ADDRESS TABLE
Table 3. BOOT VOLTAGE TABLE
Boot Voltage (V)
Resistor Value (W)
0
10k
0.9
25k
1.0
45k
1.1
70k
1.2
95k
1.35
125k
1.5
165k
VCC
Shutdown (VbootA only)
Resistor
Value
Main Rail SVID Address
(VBOOTA tied to VCC)
10k
0000
22k
0001
36k
0010
51k
0011
68k
0100
91k
0101
120k
0110
160k
0111
220k
1000
Remote Sense Amplifier
A high performance high input impedance true
differential amplifier is provided to accurately sense the
output voltage of the regulator. The VSP and VSN inputs
should be connected to the regulator’s output voltage sense
points. The remote sense amplifier takes the difference of
the output voltage with the DAC voltage and adds the droop
voltage to
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier. The non−inverting input of the error
amplifier is connected to the same 1.3 V reference used for
the differential sense amplifier output bias.
ADDRESSING PROGRAMMING
The NCP6121 supports seven possible dual SVID device
addresses and eight possible single device addresses. Pin 32
(PWM1/ADDR) is used to set the SVID address. On power
up a 10 mA current is sourced from this pin through a resistor
connected to this pin and the resulting voltage is measured.
The two tables below provide the resistor values for each
corresponding SVID address. For dual addressing follow
the Dual SVID Address Table. The address value is latched
at start−up. If VBOOTA is pulled to VCC the aux rail will
be removed from the SVID bus, the address will then follow
the Single Address SVID table below.
V DIFOUT + ǒV VSP * V VSNǓ ) ǒ1.3 V * V DACǓ
) ǒV DROOP * V CSREFǓ
(eq. 1)
High Performance Voltage Error Amplifier
A high performance error amplifier is provided for high
bandwidth transient performance. A standard Type 3
compensation circuit is normally used to compensate the
system.
Table 4. DUAL SVID ADDRESS TABLE
Resistor
Value
Main Rail SVID Address
Aux Rail SVID
Address
10k
0000
0001
Differential Current Feedback Amplifiers
25k
0010
0011
45k
0100
0101
70k
0110
0111
95k
1000
1001
125k
1010
1011
165k
1100
1101
Each phase has a low offset differential amplifier to sense
that phase current for current balance. The inputs to the
CSNx and CSPx pins are high impedance inputs. It is
recommended that any external filter resistor RCSN not
exceed 10 kW to avoid offset issues with leakage current. It
is also recommended that the voltage sense element be no
less than 0.5 mW for accurate current balance. Fine tuning
of this time constant is generally not required.
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NCP6121
voltage from CSCOMP to CSREF is less than 100 mV at
ICCMAX then it is recommend to increase the gain of the
CSCOMP amp and add a resister divider to the Droop pin
filter. This is required to provide a good current signal to
offset voltage ratio for the ILIMIT pin. When no droop is
needed, the gain of the amplifier should be set to provide
~100 mV across the current limit programming resistor at
full load. The values of Rcs1 and Rcs2 are set based on the
100k NTC and the temperature effect of the inductor and
should not need to be changed. The NTC should be placed
near the closest inductor. The output voltage droop should
be set with the droop filter divider.
The pole frequency in the CSCOMP filter should be set
equal to the zero from the output inductor. This allows the
circuit to recover the inductor DCR voltage drop current
signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning
of the time constant using commonly available values. It is
best to fine tune this filter during transient testing.
C CSN * DCR
RCSN
CSNx
L PHASE
CSPx
R CSN +
CCSN
SWNx
VOUT
DCR
1
LPHASE
2
Figure 6.
The individual phase current is summed into to the PWM
comparator feedback in this way current is balanced is via
a current mode control approach.
Total Current Sense Amplifier
The NCP6121 uses a patented approach to sum the phase
currents into a single temperature compensated total current
signal. This signal is then used to generate the output voltage
droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to
CSREF. The current signal is the difference between
CSCOMP and CSREF. The Ref(n) resistors sum the signals
from the output side of the inductors to create a low
impedance virtual ground. The amplifier actively filters and
gains up the voltage applied across the inductors to recover
the voltage drop across the inductor series resistance (DCR).
Rth is placed near an inductor to sense the temperature of the
inductor. This allows the filter time constant and gain to be
a function of the Rth NTC resistor and compensate for the
change in the DCR with temperature.
FZ +
FP +
DCR@25° C
2 * PI * L PHASE
(eq. 3)
(eq. 4)
1
2 * PI * ǒRcs1 ) Rcs1)Rth@25° C * (Ccs1 ) Ccs2)
Rcs1*Rth@25° C
Programming the Current Limit
The current limit thresholds are programmed with a
resistor between the ILIMIT and CSCOMP pins. The
ILIMIT pin mirrors the voltage at the CSREF pin and
mirrors the sink current internally to IOUT (reduced by the
IOUT Current Gain) and the current limit comparators. The
100% current limit trips if the ILIMIT sink current exceeds
10 mA for 50 ms. The 150% current limit trips with minimal
delay if the ILIMIT sink current exceeds 15 mA. Set the
value of the current limit resistor based on the
CSCOMP−CSREF voltage as shown below.
Rcs1*Rth
R LIMIT +
* ǒIout LIMIT * DCRǓ
Rcs2 ) Rcs1)Rth
Rph
10m
(eq. 5)
or
R LIMIT + LIMIT +
V CSCOMPudahsCSREF@ILIMIT
(eq. 6)
10m
Programming DROOP and DAC Feed−Forward Filter
The signals DROOP and CSREF are differentially
summed with the output voltage feedback to add precision
voltage droop to the output voltage. The total current
feedback should be filtered before it is applied to the
DROOP pin. This filter impedance provides DAC
feed−forward during dynamic VID changes. Programming
this filter can be made simpler if CSCOMP−CSREF is equal
to the droop voltage. Rdroop sets the gain of the DAC
feed−forward and Cdroop provides the time constant to
cancel the time constant of the system per the following
Figure 7.
The DC gain equation for the current sensing:
Rcs1*Rth
V CSCOMP−CSREF + −
Rcs2 ) Rcs1)Rth
Rph
* ǒI outTotal * DCRǓ
(eq. 2)
Set the gain by adjusting the value of the Rph resistors.
The DC gain should set to the output voltage droop. If the
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NCP6121
Programming ICC_MAX and ICC_MAXA
Cdroop
CSREF
CSSUM
5
6
DROOP
equations. Cout is the total output capacitance and Rout is the
output impedance of the system.
+
The SVID interface provides the platform ICC_MAX
value at register 21h for both the multiphase and the single
phase rail. A resistor to ground on the IMAX and IMAXA
pins program these registers at the time the part in enabled.
10 mA is sourced from these pins to generate a voltage on the
program resistor. The value of the register is 1 A per LSB
and is set by the equation below. The resistor value should
be no less than 10k.
Rdroop
ICC_MAX 21h +
CSCOMP
7
−
Rdroop + Cout * Rout * 453.6
Cdroop +
2V
Two temperature sense inputs are provided. A precision
current is sourced out the output of the TSENSE and
TSENSEA pins to generate a voltage on the temperature
sense network. The voltages on the temperature sense inputs
are sampled by the internal A/D converter. A 100k NTC
similar to the VISHAY ERT−J1VS104JA should be used.
Rcomp1 is mainly used for noise. See the specification table
for the thermal sensing voltage thresholds and source
current.
R out * C out
Rdroop
If the Droop at maximum load is less than 100mV at
ICCMAX we recommend altering this filter into a voltage
divider such that a larger signal can be provided to the
ILIMIT resistor by increasing the CSCOMP amp gain for
better current monitor accuracy. The DROOP pin divider
gain should be set to provide a voltage from DROOP to
CSREF equal to the amount of voltage droop desired in the
output. A current is applied to the DROOP pin during
dynamic VID. In this case Rdroop1 in parallel with Rdroop2
should be equal to Rdroop.
TSENSE
Rcomp1
0.0
DROOP
Cfilter
0.1uF
Cdroop
Rcomp2
8.2K
Rdroop1
AGND
CSREF
CSSUM
5
6
+
7
AGND
−
Precision Oscillator
A programmable precision oscillator is provided. The
clock oscillator serves as the master clock to the ramp
generator circuit. This oscillator is programmed by a resistor
to ground on the ROSC pin. The oscillator frequency range
is between 200 kHz/phase to 1 MHz/phase. The ROSC pin
provides approximately 2 V out and the source current is
mirrored into the internal ramp oscillator. The oscillator
frequency is approximately proportional to the current
flowing in the ROSC resistor.
NCP6121 Operating Frequency versus Rosc
Programming IOUT
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
scaled with an external resistor to ground such that a load
equal to ICCMAX generates a 2 V signal on IOUT. A
pull−up resistor from 5 V VCC can be used to offset the
IOUT signal positive if needed.
2.0 V * R LIMIT
10 *
RNTC
100K
Figure 10.
CSCOMP
Figure 9.
R IOUT +
(eq. 8)
Programming TSENSE and TSENSEA
10 6
Figure 8.
Rdroop2
R * 10 mA * 256 A
Rcs1*Rth
Rcs2)
Rcs1)Rth
Rph
6.98 kW
(eq. 7)
400 kHz
Fs
* ǒIout ICC_MAX * DCRǓ
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+ R OSC
(eq. 9)
NCP6121
The oscillator generates triangle ramps that are 0.5 ~ 2.5 V
in amplitude depending on the VRMP pin voltage to provide
input voltage feed forward compensation. The ramps are
equally spaced out of phase with respect to each other and
the signal phase rail is set half way between phases 1 and 2
of the multi phase rail for minimum input ripple current.
Cboost2
FB
Rbst1
Programming the Ramp Feed−Forward Circuit
PP
+ 0.1 * V VRMP
TRBST
Figure 12.
PWM Comparators
During steady state operation, the duty cycle is centered
on the valley of the triangle ramp waveform and both edges
of the PWM signal are modulated. During a transient event
the duty will increase rapidly and proportionally turning on
all phases as the error amp signal increases with respect to
the ramps to provide a highly linear and proportional
response to the step load.
(eq. 10)
Vin
Vramp_pp
Comp−IL
Rbst2
Cboost1
The ramp generator circuit provides the ramp used by the
PWM comparators. The ramp generator provides voltage
feed−forward control by varying the ramp magnitude with
respect to the VRMP pin voltage. The VRMP pin also has
a 4 V UVLO function. The VRMP UVLO is only active
after the controller is enabled. The VRMP pin is high
impedance input when the controller is disabled.
The PWM ramp time is changed according to the
following,
V RAMPpk+pk
Rbst3
Phase Detection Sequence
During start−up, the number of operational phases and
their phase relationship is determined by the internal
circuitry monitoring the PWM outputs. Normally, NCP6121
operates as a 3−phase Vcore + 1−phase VAUX PWM
controller. Connecting PWM2 pin to VCC programs
2−phase operation.
The Aux rail can be disabled by pulling the VBOOTA
signal to VCC. This changes the SVID address scheme to
allow the multiphase to be programmed to any SVID
Address odd or even. See the register resistor programming
table.
Duty
Figure 11.
Programming TRBST
The TRBST pin provides a signal to offset the output after
load release overshoot. This network should be fine tuned
during the board tuning process and is only necessary in
systems with significant load release overshoot. The
TRBST network allows maximum boost for low frequency
load release events to minimize load release undershoot. The
network time constants are set up to provide a TRBST roll
of at higher frequencies where it is not needed. Cboost1 *
Rbst1 controls the time constant of the load release boost.
This should be set to counter the under shoot after load
release. Rbst1 + Rbst2 controls the maximum amount of
boost during rapid step loading. Rbst2 is generally much
larger then Rbst1. The Cboost2 * Rbst2 time constant
controls the roll off frequency of the TRBST function.
Table 6. PHASE COUNT TABLE − NCP6121
Number of Phases
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NCP6121
3+1
PWM2 connected, VbootA programmed
2+1
PWM2 tied to VCC, VbootA programmed
3+0
PWM2 connected, VbootA tied to
VCC
2+0
PWM2 tied to VCC, VbootA tied to
VCC
NCP6121
Table 7. 2+1 UNUSED PIN CONNECTION TABLE −
NCP6121
Table 9. 2+0 UNUSED PIN CONNECTION TABLE −
NCP6121
Unused Pin
Connect to
Unused Pin
Connect to
PWM2
VCC
PWM2
VCC
CSN2
GND or VCC
CSN2
GND or VCC
CSP2
Same as CSN2
CSP2
Same as CSN2
VBOOTA
VCC
Table 8. 3+0 UNUSED PIN CONNECTION TABLE −
NCP6121
VSPA
GND
VSNA
GND
Unused Pin
Connect to
DIFFOUTA
float
VBOOTA
VCC
FBA
COMPA
VSPA
GND
COMPA
FBA
VSNA
GND
TRBSTA
float
DIFFOUTA
float
CSPA
GND
FBA
COMPA
CSNA
GND
COMPA
FBA
CSCOMPA
CSSUMA
TRBSTA
float
CSSUMA
CSCOMPA
CSPA
GND
DROOPA
GND or CSCOMPA
CSNA
GND
ILIMA
float
CSCOMPA
CSSUMA
IOUTA
GND
CSSUMA
CSCOMPA
TSENSEA
GND
DROOPA
GND or CSCOMPA
PWMA
float
ILIMA
float
IOUTA
GND
TSENSEA
GND
PWMA
float
PROTECTION FEATURES
Input Under Voltage Protection
NCP6121 monitors the 5 V VCC supply and the VRMP
pin for under voltage protection. The gate driver monitors
both the gate driver VCC and the BST voltage (12 V drivers
only). When the voltage on the gate driver is insufficient it
will pull DRVON low and notify the controller the power is
not ready. The gate driver will hold DRVON low for a
minimum period of time to allow the controller to restart its
start−up sequence. In this case the PWM is set back to the
MID state and soft start would begin again. See the figure
below.
DAC
If DRVON is pulled low the
controller will hold off its
startup
Gate Driver Pulls DRVON
Low during driver UVLO
and Calibration
Figure 13. Gate Driver UVLO Restart
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NCP6121
Soft−Start
Under Voltage Monitor
Soft−start is implemented internally. A digital counter
steps the DAC up from zero to the target voltage based on the
predetermined slew rate in the spec table. For NCP6121, the
PWM signals will start out open with a test current to collect
data on phase count and for setting internal registers. After
the configuration data is collected the controller enables and
sets the PWM signal to the 2.0 V MID state to indicate that
the drivers should be in diode mode. DRVON will then be
asserted and the COMP pin released to begin soft−start. The
DAC will ramp from Zero to the target DAC codes and the
PWM outputs will begin to fire. Each phase will move out
of the MID state when the first PWM pulse is produced
preventing the discharge of a pre−charged output.
The output voltage is monitored at the output of the
differential amplifier for UVLO. If the output falls more
than 300 mV below the DAC−DROOP voltage the UVLO
comparator will trip sending the VR_RDY signal low.
Over Voltage Protection
During normal operation the output voltage is monitored
at the differential inputs VSP and VSN. If the output voltage
exceeds the DAC voltage by approximately 175 mV, PWMs
will be forced low until the voltage drops below the OVP
threshold after the first OVP trip the DAC will ramp down
to zero to avoid a negative output voltage spike during
shutdown. When the DAC gets to zero the PWMs will be
forced low and the DRVON will remain high. To reset the
part the Enable pin must be cycled low. During soft−start, the
OVP threshold is set to 2.2 V. This allows the controller to
start up without false triggering the OVP. Prior to soft−start
the gate drivers will provide OVP protection directly at the
switching nodes.
OVP Threshold
DAC
VSP_VSN
OVP
Triggered
PWM
Figure 14. Soft−Start Sequence
Figure 15. OVP Threshold Behavior
Over Current Latch− Off Protection
During normal operation a programmable total current
limit is provided that scales with the phase count during
power saving operation. The level of total current limit is set
with the resistor from the ILIM pin to CSCOMP. The current
through the external resistor connected between ILIM and
CSCOMP is then compared to the internal current of 10 mA
and 15 mA. If the current into the ILIM pin exceeds the 10 A
level an internal latch−off counter starts. The controller
shuts down if the fault is not removed after 50 ms. If the
current into the pin exceeds 15 mA the controller will shut
down immediately. To recover from an OCP fault the EN pin
must be cycled low.
The over−current limit is programmed by a resistor on the
ILIM pin. The resistor value can be calculated by the
following equation:
R ILIM +
V CSCOMP * V CSREF
10 mA
Latch Off
Layout Notes
The NCP6121 has differential voltage and current
monitoring. This improves signal integrity and reduces
noise issues related to layout for easy design use. To insure
proper function there are some general rules to follow.
Always place the inductor current sense RC filters as close
to the CSN and CSP pins on the controller as possible. Place
the VCC decoupling cap as close as possible to the controller
VCC pin, the resistor in series should always be no higher
than 2.2 W to avoid large voltage drop. The high frequency
filter cap on CSREF and the 10 W CSREF resistors should
be placed close to the controller. The small high feed back
cap from COMP to FB should be as close to the controller
as possible. Please minimize the capacitance to ground of
the FB traces by keeping them short. The filter cap from
CSCOMP to CSREF should also be close to the controller.
(eq. 11)
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NCP6121
ORDERING INFORMATION
Device
NCP6121S52MNR2G
Package
Shipping†
QFN52
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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27
NCP6121
PACKAGE DIMENSIONS
QFN52 6x6, 0.4P
CASE 485BE
ISSUE B
PIN ONE
LOCATION
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
L1
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
EXPOSED Cu
TOP VIEW
A
(A3)
DETAIL B
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
L2
ÉÉÉ
ÉÉÉ
0.10 C
0.10 C
L
L
A B
D
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
0.08 C
A1
NOTE 4
SIDE VIEW
C
D2
DETAIL C
SEATING
PLANE
K
14
L2
DETAIL A
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.15
0.25
6.00 BSC
4.60
4.80
6.00 BSC
4.60
4.80
0.40 BSC
0.30 REF
0.25
0.45
0.00
0.15
0.15 REF
L2
27
DETAIL C
8 PLACES
SOLDERING FOOTPRINT*
E2
52X
6.40
4.80
L
52X
0.63
1
52
40
e
52X
BOTTOM VIEW
b
0.07 C A B
0.05 C
NOTE 3
4.80
6.40
0.11
PKG
OUTLINE
0.49
DETAIL D
0.40
PITCH
52X
DETAIL D
8 PLACES
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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For additional information, please contact your local
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NCP6121/D