TI1 DCR010503U 1-w, 1000-vrms isolated, regulated dcâ dc converter module Datasheet

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DCR010503, DCR012405, DCR010505
DCR011203, DCR011205, DCR012403
SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
DCR01 Series, 1-W, 1000-Vrms Isolated, Regulated DC–DC Converter Modules
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
The DCR01 family is a series of high-efficiency, inputisolated, output-regulated DC–DC converters. In
addition to 1 W nominal, galvanically-isolated output
power capability, this range of DC–DCs offer very low
output noise, thermal protection, and high accuracy.
1
1000-Vrms Isolation (Operational)
UL1950 Recognized Component
53 W/in3 (3.3W/cm3) Power Density
10-Pin PDIP and 12-Pin SOP Packages
Device-to-Device Synchronization
Thermal Protection
400-kHz Switching
125 FITs at 55ºC
±10% Input Range
Short-Circuit Protected
5-V, 12-V, and 24-V Inputs
3.3-V and 5-V Outputs
High Efficiency
This combination of features and small size makes
the DCR01 series of devices suitable for a wide
range of applications, and is an easy-to-use solution
in applications requiring signal path isolation.
CAUTION
This
product
has
operational isolation and is
intended for signal isolation
only. It must not be used
as a part of a safety
isolation circuit requiring
reinforced isolation. See
definitions
in
Feature
Description.
2 Applications
•
•
•
•
Point-of-Use Power Conversion
Digital Interface Power
Ground Loop Elimination
Power-Supply Noise Reduction
Device Information(1)
PART NUMBER
DCR01
PACKAGE
BODY SIZE (NOM)
PDIP (10)
22.86 mm × 6.61 mm
SOP (12)
17.90 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DCR01 Block Diagram
+VS
VREC
+VOUT
SYNC
Input
Controller
LDO
Regulator
ERROR
ENABLE
-VS
-VOUT
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DCR010503, DCR012405, DCR010505
DCR011203, DCR011205, DCR012403
SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Examples................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Receiving Notification of Documentation Updates
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision C (May 2003) to Revision D
Page
•
Added Device Information table, Device Comparison table, ESD Ratings table, Thermal Information table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
•
Removed Package/Ordering Information table, see POA at the end of the data sheet ....................................................... 1
•
Added additional graphs to the Typical Characteristics section ............................................................................................ 7
•
Added Isolation section to the Feature Description section ................................................................................................ 11
•
Added a typical application design to the Application Information section .......................................................................... 15
2
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
5 Device Comparison Table
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic (unless
otherwise noted)
DEVICE NUMBER
(1)
INPUT
VOLTAGE
VS (V)
OUTPUT
VOLTAGE
VO (V)
TYP
DCR010503P
DCR010503U
DCR010505P
5
3.3
12
5
DCR011205U
DCR012403P
DCR012403U
DCR012405P
3.3
24
5
DCR012405U
(1)
(2)
(3)
MAX
RIPPLE (2)
(mVp-p)
NOISE (3)
(mVp-p)
SUPPLY CURRENT (mA)
IO = 0 mA
IO = 10 mA
IO = 100%
LOAD
TYP
TYP
TYP
TYP
TYP
5
35
18
28
335
8
23
24
33
339
6
20
25
40
306
9
20
25
40
306
390
10
54
13
17
173
300
8
22
13
17
136
6
45
13
18
125
6
21
14
19
123
390
10
22
17
18
97
300
8
22
15
17
75
10
22
15
18
69
13
32
15
18
67
300
5
DCR011203P
DCR011205P
TYP
3.3
DCR010505U
DCR011203U
OUTPUT
CURRENT
(mA)
200
200
200
The last character in the part number denotes the package type; P = PDIP, U = SOP
20-MHz Bandwidth, 50% Load
100-MHz Bandwidth, 50% Load
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
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6 Pin Configuration and Functions
NVE Package
10-Pin PDIP
Top View
DVB Package
12-Pin SOP
Top View
+VS
1
18
SYNC
NC
2
17
-VS
+VS
1
28
SYNC
+VS
2
27
-VS
NC
3
26
-VS
DCR01P
DCR01U
VREC
7
12
ERROR
-VOUT
8
11
ENABLE
+VOUT
9
10
DNC
VREC
12
17
ERROR
-VOUT
13
16
ENABLE
+VOUT
14
15
DNC
Pin Functions
PIN
NAME
PDIP
SOP
ENABLE
11
16
ERROR
12
DNC
10
NC
I/O
DESCRIPTION
I
Output Voltage Enable
17
O
Error Flag Active Low
15
—
Do Not Connect
2
3
—
No Connection
SYNC
18
28
I
Synchronization Input
–VOUT
8
13
O
Output Ground
+VOUT
9
14
O
Voltage Output
VREC
7
12
O
Rectified Output
–VS
17
26, 27
I
Input Ground
+VS
1
1, 2
I
Voltage Input
4
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Input voltage
7
12-V input devices
15
24-V input devices
29
Lead temperature
PDIP package
Surface temperature of device body or pins
(maximum 10 s)
Reflow solder temperature
SOP package
Surface temperature of device body or pins
Storage temperature, Tstg
(1)
(2)
MAX
5-V input devices
–60
UNIT
V
270
°C
260
°C
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the package option addendum at the end of the datasheet for additional package information.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
MIN
NOM
MAX
5-V input devices
4.5
5
5.5
12-V input devices
10.8
12
13.2
24-V input devices
21.6
24
26.4
Operating temperature
–40
UNIT
V
85
°C
7.4 Thermal Information
DCR01
THERMAL METRIC (1)
NVE (PDIP)
DVB (SOP)
UNIT
10 PINS
12 PINS
RθJA
Junction-to-ambient thermal resistance
60
60
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26
26
°C/W
RθJB
Junction-to-board thermal resistance
24
24
°C/W
ψJT
Junction-to-top characterization parameter
7
7
°C/W
ψJB
Junction-to-board characterization parameter
24
24
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Nominal output voltage (+VOUT)
DCR01xx03
3.3
DCR01xx05
5
Setpoint accuracy
0.5%
Output short-circuit protected
Duration
V
2%
Infinite
Line regulation
1
Over line and load
IO = 10 mA to Full Load, Over +VS range
1%
Temperature variation
–40°C ≤ TA ≤ +85°C
1%
mV/V
2.5%
INPUT
Nominal input voltage (+VS)
DCR0105xx
5
DCR0112xx
12
DCR0124xx
24
Voltage range
–10%
Reflected ripple current
V
20-MHz Bandwidth, IO = 100% Load
10%
8
mAp-p
ISOLATION
Voltage
1-s Flash Test
Isolation
Continuous working
voltage across isolation
barrier
1
kVrms
dV/dt
500
V/s
Leakage Current
30
nA
DC
60
VDC
42.5
VAC
AC
Barrier capacitance
25
pF
OUTPUT ENABLE CONTROL
Logic high input voltage
Logic high input current
2
2 < VENABLE < VREC
Logic low input voltage
Logic low input current
Rectified output, VREC
VREC
100
–0.2
0.5
0 < VENABLE < 0.5
100
All 3.3-V Outputs
3.3
All 5-V Outputs
V
nA
V
nA
V
5
ERROR FLAG
Logic high open-collector leakage
VERROR = 5 V
10
µA
Logic low output voltage
Sinking 2 mA
0.4
V
THERMAL SHUTDOWN
Junction temperature
Temperature Activated
150
Temperature Deactivated
130
°C
SYNCHRONIZATION PIN
Max external capacitance on SYNC pin
3
pF
880
kHz
720
880
kHz
2.5
3
V
0
0.4
V
–40
85
°C
Internal oscillator frequency
720
External synchronization frequency
External synchronization signal high
External synchronization signal low
800
TEMPERATURE RANGE
Operating
6
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
7.6 Typical Characteristics
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2 µF, CFILTER = 1 µF, COUT = 0.1 µF, (unless otherwise noted)
80
70
85°C
60
+25°C
60
Effeciency (%)
50
Efficiency (%)
+85°C
70
–40°C
40
25°C
30
20
50
40
–40°C
30
20
10
10
0
0
0
10
20
30
40
50
60
70
80
90
0
100
10
20
30
40
DCR010503P,
DCR011205P,
DCR010503U
DCR011205U
DCR010505P,
DCR011205P,
60
70
80
90
100
90
100
DCR010505U
DCR011205U
Figure 2. Efficiency vs Load
60
70
50
60
50
40
Efficiency (%)
Efficiency (%)
Figure 1. Efficiency vs Load
30
20
40
30
20
10
10
0
0
0
10
20
30
40
50
60
70
80
90
0
100
10
20
DCR012403P
30
40
50
60
70
80
Load (%)
Load%
DCR012403U
DCR010505U
Figure 3. Efficiency vs Load
DCR011205U
Figure 4. Efficiency vs Load
18
70
16
Ripple Voltage (mVp-p)
60
50
Efficiency (%)
50
Load (%)
Load (%)
40
30
20
10
14
12
10
8
6
4
2
0
0
0
10
20
30
40
50
60
70
80
Load (%)
DCR012405P
DCR012405U
Figure 5. Efficiency vs Load
Copyright © 2001–2016, Texas Instruments Incorporated
90
100
0
20
40
60
80
100
Load (%)
All devices except for DCR011203P & DCR012403P
20-MHz Bandwidth
Figure 6. Output Voltage Ripple
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Typical Characteristics (continued)
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2 µF, CFILTER = 1 µF, COUT = 0.1 µF, (unless otherwise noted)
80
30.0
70
60
20.0
Noise (mVp-p)
Ripple Voltage (mVp-p)
25.0
15.0
10.0
50
40
30
20
5.0
10
0
0
0
20
40
60
80
100
0
20
Load (%)
DCR011203P
DCR012403P
20-MHz Bandwidth
All 5-V Input Devices
80
100
100-MHz Bandwidth
Figure 8. Output Voltage Noise
60.0
100.0
50.0
80.0
40.0
Noise (mVp-p)
120.0
60.0
40.0
20.0
30.0
20.0
10.0
0
0
0
20
40
60
80
100
0%
20%
40%
Load (%)
DCR011203P
100-MHz Bandwidth
Figure 9. Output Voltage Noise
All 5-V Output Devices
Figure 11. 5-V Output Load Regulation
8
60
Load (%)
Figure 7. Output Voltage Ripple
Noise (mVp-p)
40
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60%
80%
100%
Load%
DCR011205P
100-MHz Bandwidth
Figure 10. Output Voltage Noise
All 3.3-V output devices except DCR010503P
Figure 12. 3.3-V Output Load Regulation
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
Typical Characteristics (continued)
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2 µF, CFILTER = 1 µF, COUT = 0.1 µF, (unless otherwise noted)
3.305
85°C
3.3
3.29
20mA/div
VOUT (V)
3.295
3.285
25°C
3.28
3.275
3.27
–40°C
3.265
0
10
20
30
40
50
60
70
80
90
100
Load (%)
500ns/div
DCR010503P
20-MHz Bandwidth
Figure 14. Input Current Reflected Ripple
5mV/div
40mA/div
Figure 13. 3.3-V Output Load Regulation
500ns/div
200ns/div
100-MHz Bandwidth
20-MHz Bandwidth
Figure 16. DCR010505P Output Voltage Ripple
at 100% Load
5mV/div
20mV/div
Figure 15. Input Current Reflected Ripple
200ns/div
100-MHz Bandwidth
Figure 17. DCR010505P Output Voltage Noise
at 100% Load
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200ns/div
20-MHz Bandwidth
Figure 18. DCR010503P Output Voltage Ripple
at 100% Load
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Typical Characteristics (continued)
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2 µF, CFILTER = 1 µF, COUT = 0.1 µF, (unless otherwise noted)
Load Current
20mV/div
30mA Changing
to 325mA
Load Current
Output Voltage
200mV/div
Output Voltage
200ns/div
100-MHz Bandwidth
10µs/div
Figure 20. DCR010503P Load Transient Response
200mV/div
20mA Changing
to 200mA
Load Current
Output Voltage
Load Current
Output Voltage
10µs/div
10µs/div
Figure 21. DCR010503P Load Transient Response
Figure 22. DCR010505P Load Transient Response
200mV/div
100mA Changing
to 200mA
200mV/div
150mA Changing
to 300mA
Figure 19. DCR010503P Output Voltage Noise
at 100% Load
Load Current
Output Voltage
10µs/div
Figure 23. DCR010505P Load Transient Response
10
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8 Detailed Description
8.1 Overview
The DCR01 series of power modules offer isolation from a regulated power supply operating from a choice of
input voltages. The DCR01s provide a regulated 3.3-V or 5-V output voltage at a nominal output power of 1 W or
above. The DCR01 devices include a low dropout linear regulator internal to the device to achieve a wellregulated output voltage. The DCR01 devices are specified for operational isolation only. The circuit design uses
an advanced BiCMOS/DMOS process.
8.2 Functional Block Diagram
SYNC
+VS
Oscillator
800 kHz
VREC
+VOUT
Divide-by-2
Reset
Watchdog
Startup
LDO
Regulator
Power
Stage
ERROR
ENABLE
PSU Thermal
Shutdown
Input
Controller
-VS
-VOUT
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8.3 Feature Description
8.3.1 Isolation
Underwriters Laboratories, UL™, defines several classes of isolation that are used in modern power supplies.
Safety extra low voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit which is so
designated and protected that under normal and single fault conditions the voltage between any two accessible
parts, or between an accessible part and the equipment earthing terminal for operational isolation does not
exceed steady state 42.4 VRMS or 60 VDC peak.
8.3.1.1 Operation or Functional Isolation
The type of isolation used in the DCR01 products is referred to as operational or functional isolation. Insulated
wire used in the construction of the transformer acts as the primary isolation barrier. A high-potential (hipot), onesecond duration test (dielectric voltage, withstand test) is a production test used to verify that the isolation barrier
is functioning. Products with operational isolation must never be used as an element in a safety-isolation system.
8.3.1.2 Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and
secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the insulated
wire in the construction of the transformer. Input and output circuits must also be physically separated by
specified distances.
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Feature Description (continued)
NOTE
The DCR01 products DO NOT provide basic or enhanced isolation.
8.3.1.3 Working Voltage
For a device with operational isolation, the continuous working voltage that can be applied across the device in
normal operation must be less than 42.4 VRMS or 60 VDC, (SELV limits).
WARNING
Do not use the device as an element of a safety isolation system if SELV is
exceeded.
If the device is expected to function correctly with more than 42.4 VRMS or 60 VDC applied continuously across the
isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe
voltage, and further isolation or insulation systems must form a barrier between these circuits and any useraccessible circuitry according to safety standard requirements.
8.3.1.4 Isolation Voltage Rating
The terms Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation test
voltage are all terms that relate to the same thing; a test voltage applied for a specified time across a component
designed to provide electrical isolation to verify the integrity of that isolation. TI’s DCR01 series of DC-DC
converters are all 100% production tested at 1 kVAC for one second.
8.3.1.5 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending on
materials, construction, and environment. The DCV01 series of DC–DC converters have toroidal, enameled, wire
isolation transformers with no additional insulation between the primary and secondary windings. While a device
can be expected to withstand several times the stated test voltage, the isolation capability depends on the wire
insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual chemical
degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-voltage tests
and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage by 20% from
specified test voltage with a duration limit of one second per test.
8.3.2 Power Stage
The DCR01 series of devices use a push-pull, center-tapped topology. The DCV01 devices switch at 400 kHz
(divide-by-2 from an 800-kHz oscillator).
8.3.3 Rectification
The transformer’s output is full wave rectified and filtered by the external 1-μF ceramic capacitor connected to
VREC.
8.3.4 Regulator
The internal low dropout linear regulator provides a well-regulated output voltage throughout the operating range
of the device.
8.3.5 Oscillator and Watchdog
The onboard, 800-kHz oscillator generates the switching frequency through a divide-by-2 circuit. The oscillator
can be synchronized to other DCR01 device circuits or an external source, and is used to minimize system
noise.
12
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
Feature Description (continued)
A watchdog circuit monitors the operation of the oscillator circuit. The oscillator can be disabled by pulling the
SYNC pin low. When the SYNC pin goes low, the output pins transition into tri-state mode, which occurs within
2 μs.
8.3.6 ERROR Flag
The DCR01 has an ERROR pin which provides a power good flag, as long as the internal regulator is in
regulation. If the ERROR output is required, place a 10-kΩ resistor between the ERROR pin and the output
voltage.
8.3.7 Synchronization
When more than one DC–DC converter is switching in an application, beat frequencies and other electrical
interference can be generated. This interference occurs because of the small variations in switching frequencies
between the DC–DC converters.
The DCR01 series of devices overcome this interference by allowing devices to be synchronized to one another.
Synchronize up to eight devices by connecting the SYNC pins of each device, taking care to minimize the
capacitance of tracking. Stray capacitance (greater than 3 pF) reduces the switching frequency, or can
sometimes stop the oscillator circuit. The maximum recommended voltage applied to the SYNC pin is 3 V.
For an application that uses more than eight synchronized devices use an external device to drive the SYNC
pins. The application report External Synchronization of the DCP01/02 Series of DC/DC Converters describes
this configuration.
NOTE
During the start-up period, all synchronized devices draw maximum current from the input
simultaneously. If the input voltage falls below approximately 4 V, the devices may not
start up. A ceramic capacitor should be connected close to each device's input pin. Use a
2.2-μF capacitor for 5-V input devices, and a 0.47-μF capacitor for the 12-V and 24-V
devices.
8.3.8 Construction
The basic construction of the DCR01 series of devices is the same as standard integrated circuits. The molded
package contains no substrate. The DCV01 series of devices are constructed using an IC, low dropout linear
regulator, rectifier diodes, and a wound magnetic toroid on a leadframe. Because the package contains no
solder, the devices do not require any special printed-circuit board (PCB) assembly processing. This architecture
results in an isolated DC–DC converter with inherently high reliability.
8.3.9 Thermal Considerations
Due to the high power density of this device, it is advisable to provide ground planes on the input and output
rails. The output regulator is mounted on a copper leadframe, and a ground plane serves as an efficient heatsink.
8.3.10 Decoupling – Ripple Reduction
Due to the very low forward resistance of the DMOS switching transistors, high current demands are placed upon
the input supply for a short time. By using a good quality low Equivalent Series Resistance (ESR) capacitor of
2.2 μF (minimum) for the 5-V input devices and a 0.47-μF capacitor for the 12-V and 24-V devices, placed close
to the IC supply input pins, the effects on the power supply can be minimized.
The high switching frequency of 400 kHz allows relatively small values of capacitors to be used for filtering the
rectified output voltage. A good-quality, low-ESR, 1-μF ceramic capacitor placed close to the VREC pin and
output ground is required and reduces the ripple. The output at VREC is full wave rectified and produces a ripple
of 800 kHz.
TI recommends that a 0.1-μF, low-ESR, ceramic capacitor is connected close to the output pin and ground to
reduce noise on the output. The capacitor values listed are minimum values. If lower ripple is required, the filter
capacitor should be increased in value to 2.2 μF.
Copyright © 2001–2016, Texas Instruments Incorporated
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
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Feature Description (continued)
As with all switching power supplies, the best performance is obtained with low ESR,ceramic capacitors
connected close to the device pins. If low ESR, ceramic capacitors are not used, the ESR generates a voltage
drop when the capacitor is supplying the load power. Often a larger capacitor is chosen for this purpose, when a
low ESR, smaller capacitor would perform as well.
NOTE
TI does not recommend that the DCR01 be fitted using an IC socket, as this degrades
performance.
8.4 Device Functional Modes
8.4.1 Device Disable and Enable
Each of the DCR01 series devices can be disabled or enabled by driving the SYNC pin using an open-drain
CMOS gate. If the SYNC pin is pulled low, the DCR01 becomes disabled. The disable time depends upon the
external loading. The internal disable function is implemented in 2 μs. Removal of the pulldown causes the
DCR01 to be enabled.
Capacitive loading on the SYNC pin must be minimized (≤ 3 pF) to prevent a reduction in the oscillator
frequency. The application report External Synchronization of the DCP01/02 Series of DC/DC Converters
describes disable and enable control circuitry. This document contains information on how to null the effects of
additional capacitance on the SYNC pin. The oscillator’s frequency can be measured at VREC, as this is the
fundamental frequency of the ripple component.
8.4.2 Regulated Output Disable and Enable
The regulated output of the DCR01 can be disabled by pulling the ENABLE pin LOW. Disabling the output
voltage this way still produces a voltage on the VREC pin. When using the ENABLE control, TI recommends
placing a 10-kΩ resistor between the VREC and ENABLE pins. The ENABLE pin only controls the internal linear
regulator.
If disabling the regulated output is not required, pull the ENABLE pin HIGH by shorting it directly to the VREC pin.
This enables the regulated output voltage, thus allowing the output to be controlled from the isolated side.
14
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www.ti.com
SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 DCR01 Single Voltage Output
The DCR01 can be used to provide a single voltage output by connecting it as shown in Figure 24. The ERROR
output signal will be pulled up to the value of VOUT . The value of RERR will depend on the loading on the ERROR
line; however, the total load on the ERROR line must not exceed the value given in Electrical Characteristics.
The output may be permanently enabled by connecting the ENABLE pin to the VREC pin. The DCR01 may be
enabled remotely by connecting the ENABLE pin to VREC through a pullup resistor (REN); the value of this resistor
is not critical for the DCR01 as only a small current flows. The switch SW1 can be used to pull the ENABLE pin
LOW, thus disabling the output. The switching devices can be a bipolar transistor, FET, or a mechanical device;
the main load that it sees is REN.
SYNC
VIN
+VOUT
ERROR
+VS
+VOUT
RERR
10 k
ERROR
VREC
REN
DCR01
(1)
CIN
ENABLE
10k
SW1
±VS
COUT
0.1 µF
±VOUT
CFILTER
1 µF
±VOUT
(1) CIN = 2.2 μF for 5-V input devices and 0.47 μF for 12-V and 24-V input devices. Low ESR, ceramic capacitors are
required.
Figure 24. DCR01 Single Output Voltage
Copyright © 2001–2016, Texas Instruments Incorporated
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
www.ti.com
Application Information (continued)
9.1.2 Generating Two Positive Output Voltages
Two DCR01s can be used to create output voltages of +3.3 V and +5 V, as shown in Figure 25. The two
DCR01s are connected in self-synchronization, thus locking the oscillators of both devices to a single frequency.
The ERROR and ENABLE facilities may be used in a similar configuration for a single DCR01. The filter
capacitors connected to the VREC pins (CFILTER) must be kept separate from each other and connected in close
proximity to their respective DCR01.
VIN
+VOUT
+VS
CIN
ERROR
(1)
+VOUT1
RERR
10 k
ERROR1
VREC
DCR01
COUT
0.1 µF
ENABLE
CFILTER
1 µF
±VS
SYNC
±VOUT
-VOUT
+VOUT
SYNC
VIN
ERROR
+VS
+VOUT2
RERR
10 k
ERROR2
VREC
CIN
DCR01
(1)
±VS
ENABLE
COUT
0.1 µF
CFILTER
1 µF
±VOUT
(1) CIN = 2.2 μF for 5-V input devices and 0.47 μF for 12-V and 24-V input devices. Low ESR, ceramic capacitors are
required.
Figure 25. Two Positive Voltages from Self-Synchronized DCR01s
9.1.3 Generation of Dual Polarity Voltages from Two Self-Synchronized DCR01s
Two DCR01s can be configured to produce a dual polarity supply (that is, ±5 V); the circuit must be connected as
shown in Figure 26.
It must be observed that both devices are producing a positive regulated output; therefore the ERROR, ENABLE,
and VREC are all relative to that particular device's –VOUT pin and must not be directly connected together, or in
the case of the negative output device, connected to the common 0-V output.
VIN
+VOUT
+VS
CIN
VPOS O/P
ERROR
(1)
VREC
DCR01
ENABLE
±VS
SYNC
COUT
0.1 µF
CFILTER
1 µF
±VOUT
0V
+VOUT
SYNC
VIN
ERROR
+VS
VREC
CIN
DCR01
(1)
±VS
ENABLE
COUT
0.1 µF
CFILTER
1 µF
VNEG O/P
±VOUT
(1) CIN = 2.2 μF for 5-V input devices and 0.47 μF for 12-V and 24-V input devices. Low ESR, ceramic capacitors are
required.
Figure 26. Dual Polarity Voltage Generation
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www.ti.com
SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
9.2 Typical Application
SYNC
DCR010505
+VOUT = 5V
+VOUT
RERR
10 k
VIN = 5V
+VS
ERROR
CIN
2.2 µF
COUT
0.1 µF
VREC
ENABLE
±VS
CFILTER
1.0 µF
±VOUT
±VOUT
Copyright © 2016, Texas Instruments Incorporated
Figure 27. DCR01 Typical Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 and follow the design procedure.
Table 1. Design Example Parameters
DESIGN PARAMETER
VALUE
Input Voltage VIN
5 V typical
Output Voltage VOUT
5 V regulated
Output Current Rating
200 mA
Isolation
1000-V operational
9.2.2 Detailed Design Procedure
9.2.2.1 Input Capacitor
For this design, a 2.2-μF, ceramic capacitor is required for the input decoupling capacitor.
9.2.2.2 Output Capacitor
For this design, a 0.1-μF, ceramic capacitor is required for between +VOUT and –VOUT.
9.2.2.3 Filter Capacitor
A high-quality, low-ESR, 1-μF, ceramic capacitor placed close to the VREC pin and output ground is required to
reduce output voltage ripple.
9.2.2.4 ERROR Flag
Place a 10-kΩ resistor between the ERROR pin and the output voltage to provide a power good signal when the
internal regulator is in regulation.
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
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9.2.3 Application Curves
80
+85°C
70
+25°C
Effeciency (%)
60
50
40
–40°C
30
20
10
0
0
10
20
30
40
50
60
70
80
90
100
Load (%)
Figure 28. DCR010505 Efficiency
Figure 29. DCR010505 Load Regulation
10 Power Supply Recommendations
The DCR01 is a switching power supply, and as such can place high peak current demands on the input supply.
To avoid the supply falling momentarily during the fast switching pulses, ground and power planes must be used
to connect the power to the input of DCR01. If this connection is not possible, then the supplies must be
connected in a star formation with the traces made as wide as possible.
11 Layout
11.1 Layout Guidelines
Carefully consider the layout of the PCB in order for the best results to be obtained.
Input and output power and ground planes provide a low-impedance path for the input and output power. For the
output, the positive and negative voltage outputs conduct through wide traces to minimize losses.
A good-quality, low-ESR, ceramic capacitor placed as close as practical across the input reduces reflected ripple
and ensure a smooth start-up.
A good-quality, low-ESR, ceramic capacitor placed as close as practical across the rectifier output terminal and
output ground gives the best ripple and noise performance.
The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the
effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the
input decoupling capacitor, because this capacitor supplies the transient current associated with the fast
switching waveforms of the power drive circuits.
If the SYNC pin is being used, the tracking between device SYNC pins must be short to avoid stray capacitance.
Never connect a capacitor to the SYNC pin. If the SYNC pin is not being used it is advisable to place a guard
ring (connected to input ground) around this pin to avoid any noise pick-up. Ensure that no other trace is in close
proximity to this trace SYNC trace to decrease the stray capacitance on this pin. The stray capacitance affects
the performance of the oscillator.
Figure 30 shows a schematic for a single DCR01, SOP package device. Figure 31 and Figure 32 show a typical
layout for the SOP package DCR01 device. The layout shows proper placement of capacitors and power planes.
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www.ti.com
SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
11.2 Layout Examples
+VS
1
DCR01U
+VS
2
+VS
C1
U1
SYNC 28
-VS
26 ±VS
27 ±VS
VREC
ERROR 17
12 VREC
C2
ENABLE 16
-VOUT
C3
+VOUT
13 ±VOUT
14 +VOUT
Figure 30. DCR01 PCB Schematic, U Package
U1
SYNC
+VS
SYNC
+VS
-VS
C1
-VS
VREC
C2
VREC
ERROR
ERROR
ENABLE
-VOUT
+VOUT
ENABLE
-VOUT
C3
Figure 31. PCB Layout Example,
Component-Side View
Copyright © 2001–2016, Texas Instruments Incorporated
+VOUT
Figure 32. PCB Layout Example,
Non-Component-Side View
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SBVS013D – OCTOBER 2001 – REVISED JUNE 2016
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DCR010503
Click here
Click here
Click here
Click here
Click here
DCR012405
Click here
Click here
Click here
Click here
Click here
DCR010505
Click here
Click here
Click here
Click here
Click here
DCR011203
Click here
Click here
Click here
Click here
Click here
DCR011205
Click here
Click here
Click here
Click here
Click here
DCR012403
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
Underwriters Laboratories, UL are trademarks of UL LLC.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DCR010503P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCR010503P
DCR010503U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010503U
DCR010503U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010503U
DCR010503UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010503U
DCR010505P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCR010505P
DCR010505U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010505U
DCR010505U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010505U
DCR010505U/1KE4
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010505U
DCR010505UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010505U
DCR011203P
ACTIVE
PDIP
NVE
10
20
TBD
CU NIPDAU
Level---
-40 to 85
DCR011203P
DCR011203U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011203U
DCR011203U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011203U
DCR011203UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011203U
DCR011205P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCR011205P
DCR011205U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011205U
DCR011205U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011205U
DCR011205UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011205U
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DCR012403P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCR012403P
DCR012403U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR012403U
DCR012405P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCR012405P
DCR012405U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR012405U
DCR012405U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR012405U
DCR012405UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR012405U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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Addendum-Page 3
MECHANICAL DATA
MPDI055 – APRIL 2001
NVE (R-PDIP-T10/18)
PLASTIC DUAL-IN-LINE
0.920 (23,37)
0.880 (22,35)
D
18
10
0.280 (7,11)
0.240 (6,10)
D
1
9
Index
Area
E
0.070 (1,78)
0.045 (1,14)
0.195 (4,95)
0.115 (2,92)
Base
Plane
–C–
Seating
Plane
0.325 (8,26)
0.300 (7,62)
0.210 (5,33)
MAX
E
0.005 (0,13)
MIN 4 PL
Full Lead D
0.100 (2,54)
0.022 (0,56)
0.014 (0,36)
0.010 (0,25) M C
0.150 (3,81)
0.115 (2,92)
0.300 (7,63)
0.014 (0,36)
0.008 (0,20)
0.015 (0,38)
MIN
0.060 (1,52)
0.000 (0,00)
0.430 (10,92)
MAX
F
F
4202497/A 03/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001-AC with the exception
of lead count.
D. Dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 (0,25).
E. Dimensions measured with the leads constrained to be
perpendicular to Datum C.
F. Dimensions are measured at the lead tips with the
leads unconstrained.
G. A visual index feature must be located within the
cross-hatched area.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
PACKAGE OUTLINE
DVB0012A
SOP - 2.65 mm max height
SCALE 0.900
PLASTIC SMALL OUTLINE
C
10.65
10.01
SEATING PLANE
PIN 1 ID
AREA
A
28
1
18.1
17.7
NOTE 3
0.1 C
8X 1.27
2X 16.51
14
15
B
7.6
7.4
12X
0.51
0.33
0.25
C A
B
0.32
TYP
0.23
SEE DETAIL A
2.65 MAX
8
0
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4222497/A 10/2015
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DVB0012A
SOP - 2.65 mm max height
PLASTIC SMALL OUTLINE
12X (2)
SYMM
1
28
12X (0.6)
(R0.05)
TYP
SYMM
(16.51)
8X (1.27)
14
15
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222497/A 10/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DVB0012A
SOP - 2.65 mm max height
PLASTIC SMALL OUTLINE
12X (2)
1
SYMM
28
12X (0.6)
(R0.05)
SYMM
(16.51)
8X (1.27)
14
15
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222497/A 10/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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