HP HCPL-315J-XXXE 0.5 amp output current igbt gate drive optocoupler Datasheet

0.5 Amp Output Current IGBT
Gate Drive Optocoupler
Technical Data
HCPL-3150 (Single Channel)
HCPL-315J (Dual Channel)
Features
• 0.5 A Minimum Peak Output
Current
• 15 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 1500 V
• 1.0 V Maximum Low Level
Output Voltage (VOL)
Eliminates Need for
Negative Gate Drive
• ICC = 5 mA Maximum Supply
Current
• Under Voltage Lock-Out
Protection (UVLO) with
Hysteresis
• Wide Operating VCC Range:
15 to 30 Volts
• 0.5 µs Maximum
Propagation Delay
• +/– 0.35 µs Maximum Delay
Between Devices/Channels
• Industrial Temperature
Range:
-40°C to 100°C
• HCPL-315J: Channel One to
Channel Two Output
Isolation = 1500 Vrms/1 min.
• Safety and Regulatory
Approval:
UL Recognized (UL1577)
3750 Vrms/1 min.
IEC/EN/DIN EN 60747-5-2
Approved
VIORM = 630 Vpeak
(HCPL-3150 Option 060 only)
VIORM = 891 Vpeak (HCPL315J) CSA Certified
Applications
• Isolated IGBT/MOSFET
Gate Drive
• AC and Brushless DC Motor
Drives
• Industrial Inverters
• Switch Mode Power
Supplies (SMPS)
• Uninterruptable Power
Supplies (UPS)
Functional Diagram
N/C
8
1
VCC
ANODE
2
7
VO
CATHODE
3
6
VO
N/C
4
5
VEE
SHIELD
Description
The HCPL-315X consists of a
LED optically coupled to an
integrated circuit with a power
output stage. This optocoupler is
ideally suited for driving power
IGBTs and MOSFETs used in
motor control inverter applications. The high operating voltage
range of the output stage provides the drive voltages required
by gate controlled devices. The
voltage and current supplied by
this optocoupler makes it ideally
suited for directly driving IGBTs
with ratings up to 1200 V/50 A.
For IGBTs with higher ratings,
the HCPL-3150/315J can be used
to drive a discrete power stage
which drives the IGBT gate.
N/C
1
16 VCC
15 VO
ANODE
2
CATHODE
3
ANODE
6
11 VCC
CATHODE
7
10 VO
N/C
8
HCPL-3150
14 VEE
SHIELD
9
SHIELD
VEE
HCPL-315J
TRUTH TABLE
LED
VCC - VEE
“Positive Going”
(i.e., Turn-On)
VCC - VEE
“Negative-Going”
(i.e., Turn-Off)
VO
OFF
ON
ON
ON
0 - 30 V
0 - 11 V
11 - 13.5 V
13.5 - 30 V
0 - 30 V
0 - 9.5 V
9.5 - 12 V
12 - 30 V
LOW
LOW
TRANSITION
HIGH
A 0.1 µF bypass capacitor must be connected between the VCC and VEE pins for each channel.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
Selection Guide: Invertor Gate Drive Optoisolators
Package Type
8-Pin DIP (300 mil)
Part Number HCPL-3150 HCPL-3120 HCPL-J312 HCPL-J314
Number of
1
1
1
1
Channels
IEC/EN/DIN EN
VIORM
VIORM
60747-5-2
630 Vpeak
891Vpeak
Approvals
Option 060
UL
3750
3750
Approval
Vrms/1 min.
Vrms/1 min.
Output Peak
0.5A
2A
2A
0.4A
Current
CMR
15 kV/µs
10 kV/µs
(minimum)
UVLO
Yes
No
Fault Status
No
Widebody
(400 mil)
HCNW-3120
1
Small Outline SO-16
HCPL-315J
HCPL-316J
HCPL-314J
2
1
2
VIORM
1414 Vpeak
VIORM
891 Vpeak
5000
Vrms/1min.
2A
3750
Vrms/1 min.
2A
0.5A
15 kV/µs
0.4A
10 kV/µs
Yes
Yes
No
No
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example
HCPL-315Y#XXXX
No Option = Standard DIP package, 50 per tube.
060 = IEC/EN/DIN EN 60747-5-2 VIORM = 630 Vpeak Option, 50 per tube.
(HCPL-3150 only)
300 = Gull Wing Surface Mount Option, 50 per tube. (HCPL-3150 only)
500 = Tape and Reel Packaging Option.
HCPL-3150; 1000 per reel.
HCPL-315J; 850 per reel.
XXXE = Lead Free Option
∅ = Single Channel, 8-pin PDIP.
J = Dual Channel, SO16.
Option data sheets available. Contact Agilent sales representative or authorized distributor.
Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use “–”
Package Outline Drawings
Standard DIP Package
9.40 (0.370)
9.90 (0.390)
8
7
6
5
OPTION CODE*
YYWW
PIN ONE
1.19 (0.047) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
1
2
3
7.36 (0.290)
7.88 (0.310)
5° TYP.
4
1.78 (0.070) MAX.
4.70 (0.185) MAX.
DIMENSIONS PIN
IN MILLIMETERS
AND (INCHES).
DIAGRAM
PIN ONE
0.51 (0.020) MIN.
2.92 (0.115) MIN.
0.76 (0.030)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
6.10 (0.240)
6.60 (0.260)
DATE CODE
A 3150 Z
0.65 (0.025) MAX.
2.28 (0.090)
2.80 (0.110)
* MARKING1 CODE
8 OPTION NUMBERS.
VDD1LETTER
VDD2FOR
"V" = OPTION 060.
OPTION NUMBERS
AND 500
7 NOT MARKED.
2 VIN+ 300
VOUT+
NOTE: FLOATING
IS 0.25 mm (10 mils) MAX.
6
3 V LEAD
V PROTRUSION
IN–
4
OUT–
GND1 GND2 5
3
Package Outline Drawings
Gull-Wing Surface-Mount Option 300
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
6
7
8
OPTION
CODE*
5
A 3150 Z
6.350 ± 0.25
(0.250 ± 0.010)
YYWW
1
MOLDED
3
2
1.016 (0.040)
10.9 (0.430)
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.20 (0.008)
0.33 (0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
2.540
(0.100)
BSC
12° NOM.
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
*MARKING CODE LETTER FOR OPTION
NUMBERS.
"V" = OPTION 060.
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
16 - Lead Surface Mount
9
VO2
11 10
GND2
VO1
10.36 ± 0.20
(0.408 ± 0.008)
GND1
VCC1
16 15 14
VCC2
LAND PATTERN RECOMMENDATION
(0.295 ± 0.004)
7.49 ± 0.10
NC
VIN1
V1
VIN2
V2
NC
HCPL-315J
1
2
3
6
7
8
(0.458) 11.63
(0.085) 2.16
(0.025) 0.64
(0.004 – 0.011)
0.10 – 0.30
STANDOFF
(0.345 ± 0.008)
8.76 ± 0.20
VIEW
FROM
PIN 16
0 - 8°
9°
(0.025 MIN.)
0.64
VIEW
FROM
PIN 1
(0.138 ± 0.005)
3.51 ± 0.13
(0.0091 – 0.0125)
0.23 – 0.32
(0.408 ± 0.008)
10.36 ± 0.20
ALL LEADS TO BE COPLANAR ± (0.002 INCHES) 0.05 mm.
(0.018)
(0.050)
0.457
1.27
(0.406 ± 0.007)
10.31 ± 0.18
DIMENSIONS IN (INCHES) AND MILLIMETERS.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
4
Solder Reflow Thermal Profile
Regulatory Information
The HCPL-3150 and HCPL-315J
have been approved by the
following organizations:
300
TEMPERATURE (°C)
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
200
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
30
SEC.
160°C
150°C
140°C
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
0
100
150
200
TIME (SECONDS)
Recommended Pb-Free IR Profile
tp
Tp
TL
TEMPERATURE
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
PEAK
TEMP.
230°C
Tsmax
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
260 +0/-5 °C
217 °C
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
tL
60 to 150 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
250
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01.
(Option 060 and HCPL-315J only)
5
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics
Description
Symbol HCPL-3150#060
Installation classification per DIN VDE
0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
I-IV
for rated mains voltage ≤ 600 Vrms
I-III
Climatic Classification
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
Maximum Working Insulation Voltage
VIORM
630
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec,
VPR
1181
Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample
Test, tm = 60 sec,
VPR
945
Partial discharge < 5 pC
Highest Allowable Overvoltage*
VIOTM
6000
(Transient Overvoltage tini = 10 sec)
Safety-Limiting Values – Maximum Values
Allowed in the Event of a Failure, Also
See Figure 37, Thermal Derating Curve.
Case Temperature
TS
175
Input Current
IS, INPUT
230
Output Power
PS, OUTPUT
600
Insulation Resistance at TS, VIO = 500 V
RS
≥ 109
HCPL-315J**
Unit
I-IV
I-III
I-II
55/100/21
2
891
Vpeak
1670
Vpeak
1336
Vpeak
6000
Vpeak
175
400
1200
≥ 109
°C
mA
mW
Ω
**Approval Pending.
*Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section IEC/EN/DIN EN
60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits
in application.
6
Insulation and Safety Related Specifications
Parameter
Minimum External
Air Gap
(External Clearance)
Minimum External
Tracking
(External Creepage)
Minimum Internal
Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking
Index)
Isolation Group
Symbol
L(101)
HCPL-3150
7.1
HCPL-315J
8.3
Units
mm
L(102)
7.4
8.3
mm
0.08
≥ 0.5
mm
≥ 175
≥ 175
Volts
IIIa
IIIa
CTI
Conditions
Measured from input terminals
to output terminals, shortest
distance through air.
Measured from input terminals
to output erminals, shortest
distance path along body.
Through insulation distance
conductor to conductor.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110,
1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance wtih CECC 00802.
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Average Input Current
Peak Transient Input Current
(<1 µs pulse width, 300 pps)
Reverse Input Voltage
“High” Peak Output Current
“Low” Peak Output Current
Supply Voltage
Output Voltage
Output Power Dissipation
Total Power Dissipation
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
TS
TA
IF(AVG)
IF(TRAN)
Min.
-55
-40
Symbol
(VCC - VEE)
IF(ON)
VF(OFF)
TA
Units
°C
°C
mA
A
Note
1, 16
VR
5
Volts
IOH(PEAK)
0.6
A
2, 16
IOL(PEAK)
0.6
A
2, 16
(VCC - VEE)
0
35
Volts
VO(PEAK)
0
VCC
Volts
PO
250
mW
3, 16
PT
295
mW
4, 16
260°C for 10 sec., 1.6 mm below seating plane
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter
Power Supply Voltage
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
Max.
125
100
25
1.0
Min.
15
7
-3.0
-40
Max.
30
16
0.8
100
Units
Volts
mA
V
°C
7
Electrical Specifications (DC)
Over recommended operating conditions (TA = -40 to 100°C, I F(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground, each channel) unless otherwise specified.
Parameter
High Level
Symbol
Min.
Typ.*
IOH
0.1
0.4
Output Current
Low Level
Max.
Units
A
IOL
0.1
Fig.
Note
VO = (VCC - 4 V)
2, 3,
17
5
VO = (VCC - 15 V)
0.5
Output Current
Test Conditions
0.6
A
VO = (VEE + 2.5 V)
VO = (VEE + 15 V)
0.5
High Level Output
Voltage
VOH
V
IO = -100 mA
1, 3,
19
Low Level Output
Voltage
VOL
0.4
1.0
V
IO = 100 mA
4, 6,
20
High Level
Supply Current
ICCH
2.5
5.0
mA
Output Open,
IF = 7 to 16 mA
7, 8
Low Level
Supply Current
ICCL
2.7
5.0
mA
Output Open,
VF = -3.0 to +0.8 V
Threshold Input
Current Low to High
IFLH
2.2
5.0
mA
HCPL-3150
2.6
6.4
Threshold Input
Voltage High to Low
VFHL
0.8
VF
1.2
Input Forward Voltage
Temperature
Coefficient of
Forward Voltage
Input Reverse
Breakdown Voltage
Input Capacitance
UVLO Threshold
UVLO Hysteresis
(VCC - 4) (VCC - 3)
5, 6,
18
∆VF /∆TA
BVR
1.5
1.8
1.6
1.95
V
HCPL-3150
IF = 10 mA
16
HCPL-315J
mV/°C IF = 10 mA
5
V
3
70
VUVLO+
11.0
12.3
13.5
VUVLO-
9.5
10.7
12.0
UVLOHYS
9, 15,
21
V
-1.6
CIN
HCPL-315J
IO = 0 mA,
VO > 5 V
1.6
HCPL-3150
IR = 10 µA
HCPL-315J
IR = 10 µA
pF
f = 1 MHz, VF = 0 V
V
VO > 5 V,
IF = 10 mA
V
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
22,
36
2
5
2
6, 7
16
8
Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground, each channel) unless otherwise specified.
Parameter
Propagation Delay
Time to High
Output Level
Symbol
tPLH
Min.
0.10
Propagation Delay
tPHL
0.10
Time to Low
Output Level
Pulse Width
PWD
Distortion
Propagation Delay
PDD
-0.35
Difference Between (tPHL - t PLH)
Any Two Parts
or Channels
Rise Time
tr
Fall Time
tf
UVLO Turn On
tUVLO ON
Delay
UVLO Turn Off
tUVLO OFF
Delay
Output High Level
|CMH|
15
Common Mode
Transient
Immunity
Output Low Level
|CML|
15
Common Mode
Transient
Immunity
Typ.*
0.30
Max.
0.50
Units
µs
Test Conditions
Rg = 47 Ω,
Cg = 3 nF,
f = 10 kHz,
Duty Cycle = 50%
Fig.
10, 11,
12, 13,
14, 23
0.3
0.50
µs
0.3
µs
0.35
µs
34,35
0.1
0.1
0.8
µs
µs
µs
23
0.6
µs
30
kV/µs
30
kV/µs
Note
14
15
VO > 5 V,
IF = 10 mA
VO < 5 V,
IF = 10 mA
TA = 25°C,
IF = 10 to 16 mA,
VCM = 1500 V,
VCC = 30 V
TA = 25°C,
VCM = 1500 V,
VF = 0 V,
VCC = 30 V
10
22
24
11, 12
11, 13
9
Package Characteristics (each channel, unless otherwise specified)
Parameter
Symbol
Input-Output
VISO
Momentary
Withstand Voltage**
Output-Output
VO-O
Momentary
Withstand Voltage**
Resistance
RI-O
(Input - Output)
Capacitance
CI-O
(Input - Output)
LED-to-Case
Thermal Resistance
LED-to-Detector
Thermal Resistance
Detector-to-Case
Thermal Resistance
Device
HCPL-3150
Min.
3750
HCPL-315J
HCPL-315J
3750
1500
Typ.*
Max. Units
Vrms
1012
Ω
Test Conditions
RH < 50%,
t = 1 min.,
TA = 25°C
RH < 50%
t = 1 min.,
TA = 25°C
VI-O = 500 VDC
0.6
1.3
391
pF
f = 1 MHz
θLC
HCPL-3150
HCPL-315J
HCPL-3150
°C/W
θLD
HCPL-3150
439
°C/W
θDC
HCPL-3150
119
°C/W
Vrms
Thermocouple
located at center
underside of
package
Fig.
Note
8, 9
17
9
28
18
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
**The Input-Output/Output-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an inputoutput/output-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent
Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70°C free-air
temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs,
maximum duty cycle = 0.2%. This
value is intended to allow for
component tolerances for designs
with IO peak minimum = 0.5 A. See
Applications section for additional
details on limiting IOH peak.
3. Derate linearly above 70°C free-air
temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70°C free-air
temperature at a rate of 5.4 mW/°C.
The maximum LED junction temperature should not exceed 125°C.
5. Maximum pulse width = 50 µs,
maximum duty cycle = 0.5%.
6. In this test VOH is measured with a dc
load current. When driving capacitive
loads VOH will approach VCC as IOH
approaches zero amps.
7. Maximum pulse width = 1 ms,
maximum duty cycle = 20%.
8. In accordance with UL1577, each
HCPL-3150 optocoupler is proof
tested by applying an insulation test
voltage ≥ 4500 Vrms (≥ 5000 Vrms
for the HCPL-315J) for 1 second
(leakage detection current limit, I I-O
≤ 5 µA). This test is performed
before the 100% production test for
partial discharge (method b) shown
in the IEC/EN/DIN EN 60747-5-2
Insulation Characteristics Table, if
applicable.
9. Device considered a two-terminal
device: pins on input side shorted
together and pins on output side
shorted together.
10. The difference between tPHL and tPLH
between any two parts or channels
under the same test condition.
11. Pins 1 and 4 (HCPL-3150) and pins 3
and 4 (HCPL-315J) need to be
connected to LED common.
12. Common mode transient immunity in
the high state is the maximum
13.
14.
15.
16.
17.
18.
tolerable |dVCM /dt| of the common
mode pulse, VCM, to assure that the
output will remain in the high state
(i.e., VO > 15.0 V).
Common mode transient immunity in
a low state is the maximum tolerable
|dVCM /dt| of the common mode
pulse, VCM, to assure that the output
will remain in a low state (i.e.,
VO < 1.0 V).
This load condition approximates the
gate load of a 1200 V/25 A IGBT.
Pulse Width Distortion (PWD) is
defined as |tPHL-t PLH| for any given
device.
Each channel.
Device considered a two terminal
device: Channel one output side pins
shorted together, and channel two
output side pins shorted together.
See the thermal model for the
HCPL-315J in the application
section of this data sheet.
-2
-3
-4
-40 -20
0
20
40
60
80
100
0.40
0.35
0.30
0.25
-40 -20
60
40
80
100
0.2
0
-40 -20
0
20
40
60
80
100
0.8
0.6
0.4
VF(OFF) = -3.0 to 0.8 V
VOUT = 2.5 V
VCC = 15 to 30 V
VEE = 0 V
0.2
0
-40 -20
0
20
40
60
80
100
ICC – SUPPLY CURRENT – mA
3.0
2.5
VCC = 30 V
VEE = 0 V
IF = 10 mA for ICCH
IF = 0 mA for ICCL
ICCH
ICCL
3.0
2.5
40
60
80
TA – TEMPERATURE – °C
Figure 7. ICC vs. Temperature.
100
IF = 10 mA for ICCH
IF = 0 mA for ICCL
TA = 25 °C
VEE = 0 V
2.0
1.5
20
IF = 7 to 16 mA
VCC = 15 to 30 V
VEE = 0 V
-5
-6
0
0.2
0.4
0.6
1.0
0.8
IOH – OUTPUT HIGH CURRENT – A
VF(OFF) = -3.0 to 0.8 V
VCC = 15 to 30 V
4 VEE = 0 V
3
2
1
0
15
20
25
VCC – SUPPLY VOLTAGE – V
Figure 8. ICC vs. VCC.
100 °C
25 °C
-40 °C
0
0.2
0.4
0.8
0.6
1.0
Figure 6. VOL vs. I OL.
3.5
ICCH
ICCL
0
-4
IOL – OUTPUT LOW CURRENT – A
Figure 5. IOL vs. Temperature.
3.5
1.5
-40 -20
-3
TA – TEMPERATURE – °C
TA – TEMPERATURE – °C
Figure 4. VOL vs. Temperature.
100 °C
25 °C
-40 °C
-2
5
VOL – OUTPUT LOW VOLTAGE – V
0.4
-1
Figure 3. VOH vs. IOH.
1.0
VF(OFF) = -3.0 to 0.8 V
IOUT = 100 mA
VCC = 15 to 30 V
VEE = 0 V
0.6
2.0
20
Figure 2. IOH vs. Temperature.
IOL – OUTPUT LOW CURRENT – A
0.8
0
TA – TEMPERATURE – °C
1.0
VOL – OUTPUT LOW VOLTAGE – V
0.45
TA – TEMPERATURE – °C
Figure 1. VOH vs. Temperature.
ICC – SUPPLY CURRENT – mA
IF = 7 to 16 mA
VOUT = VCC - 4 V
VCC = 15 to 30 V
VEE = 0 V
30
IFLH – LOW TO HIGH CURRENT THRESHOLD – mA
-1
0.50
IF = 7 to 16 mA
IOUT = -100 mA
VCC = 15 to 30 V
VEE = 0 V
(VOH - VCC ) – OUTPUT HIGH VOLTAGE DROP – V
0
IOH – OUTPUT HIGH CURRENT – A
(VOH - VCC ) – HIGH OUTPUT VOLTAGE DROP – V
10
5
VCC = 15 TO 30 V
VEE = 0 V
OUTPUT = OPEN
4
3
2
1
0
-40 -20
0
20
40
60
80
TA – TEMPERATURE – °C
Figure 9. IFLH vs. Temperature.
100
11
TPLH
TPHL
300
200
15
25
20
400
300
200
TPLH
TPHL
100
30
VCC – SUPPLY VOLTAGE – V
10
12
14
300
200
TPLH
TPHL
0
50
150
100
200
Rg – SERIES LOAD RESISTANCE – Ω
Figure 13. Propagation Delay vs. Rg.
1000
TA = 25°C
100
10
IF
+
VF
–
1.0
0.1
0.01
0.001
1.10
1.20
1.30
1.40
1.50
300
200
TPLH
TPHL
1.60
VF – FORWARD VOLTAGE – V
Figure 16. Input Current vs. Forward
Voltage.
20
40
60
80
100
Figure 12. Propagation Delay vs.
Temperature.
30
VCC = 30 V, VEE = 0 V
TA = 25 °C
IF = 10 mA
Rg = 47 Ω
DUTY CYCLE = 50%
f = 10 kHz
400
300
200
TPLH
TPHL
100
0
TA – TEMPERATURE – °C
VO – OUTPUT VOLTAGE – V
400
400
100
-40 -20
16
500
VCC = 30 V, VEE = 0 V
TA = 25 °C
IF = 10 mA
Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
Tp – PROPAGATION DELAY – ns
Tp – PROPAGATION DELAY – ns
8
Figure 11. Propagation Delay vs. IF.
500
IF – FORWARD CURRENT – mA
6
IF(ON) = 10 mA
IF(OFF) = 0 mA
VCC = 30 V, VEE = 0 V
Rg = 47 Ω, Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
IF – FORWARD LED CURRENT – mA
Figure 10. Propagation Delay vs. VCC.
100
VCC = 30 V, VEE = 0 V
Rg = 47 Ω, Cg = 3 nF
TA = 25 °C
DUTY CYCLE = 50%
f = 10 kHz
Tp – PROPAGATION DELAY – ns
400
100
500
500
IF = 10 mA
TA = 25 °C
Rg = 47 Ω
Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
Tp – PROPAGATION DELAY – ns
Tp – PROPAGATION DELAY – ns
500
0
20
40
60
80
100
Cg – LOAD CAPACITANCE – nF
Figure 14. Propagation Delay vs. Cg.
25
20
15
10
5
0
0
1
2
3
4
5
IF – FORWARD LED CURRENT – mA
Figure 15. Transfer Characteristics.
12
8
1
1
8
2
7
3
6
4
5
0.1 µF
2
0.1 µF
+
–
7
4V
IF = 7 to
16 mA
IOL
+ VCC = 15
– to 30 V
+ VCC = 15
– to 30 V
6
3
IOH
4
5
Figure 17. I OH Test Circuit.
2.5 V +
–
Figure 18. I OL Test Circuit.
8
1
1
8
2
7
0.1 µF
2
7
0.1 µF
VOH
IF = 7 to
16 mA
100 mA
+ VCC = 15
– to 30 V
+ VCC = 15
– to 30 V
6
3
3
6
4
5
VOL
100 mA
4
5
Figure 19. VOH Test Circuit.
1
Figure 20. VOL Test Circuit.
8
1
8
2
7
0.1 µF
2
0.1 µF
7
IF
VO > 5 V
+ VCC = 15
– to 30 V
IF = 10 mA
VO > 5 V
3
6
3
6
4
5
4
5
Figure 21. I FLH Test Circuit.
Figure 22. UVLO Test Circuit.
+
–
VCC
13
8
1
0.1 µF
IF = 7 to 16 mA
+
10 KHz –
500 Ω
2
+
–
7
IF
VCC = 15
to 30 V
tr
tf
VO
50% DUTY
CYCLE
90%
47 Ω
6
3
50%
VOUT
3 nF
4
10%
5
tPLH
tPHL
Figure 23. tPLH, t PHL, t r, and tf Test Circuit and Waveforms.
VCM
δV
8
1
IF
0.1 µF
A
B
5V
δt
2
VO
6
4
5
VCM
∆t
0V
7
+
–
3
=
∆t
+
–
VCC = 30 V
VOH
VO
SWITCH AT A: IF = 10 mA
VO
VOL
+
–
SWITCH AT B: IF = 0 mA
VCM = 1500 V
Figure 24. CMR Test Circuit and Waveforms.
Applications Information
Eliminating Negative IGBT
Gate Drive
To keep the IGBT firmly off, the
HCPL-3150/315J has a very low
maximum VOL specification of
1.0 V. The HCPL-3150/315J
realizes this very low VOL by using
a DMOS transistor with 4 Ω
(typical) on resistance in its pull
down circuit. When the
HCPL-3150/315J is in the low
state, the IGBT gate is shorted to
the emitter by Rg + 4 Ω.
Minimizing Rg and the lead
inductance from the HCPL-3150/
315J to the IGBT gate and
emitter (possibly by mounting the
HCPL-3150/315J on a small PC
board directly above the IGBT)
can eliminate the need for
negative IGBT gate drive in many
applications as shown in Figure
25. Care should be taken with
such a PC board design to avoid
routing the IGBT collector or
emitter traces close to the HCPL3150/315J input as this can result
in unwanted coupling of transient
signals into the HCPL-3150/315J
and degrade performance. (If the
IGBT drain must be routed near
the HCPL-3150/315J input, then
the LED should be reverse-biased
when in the off state, to prevent
the transient signals coupled
from the IGBT drain from turning
on the HCPL-3150/315J.)
HCPL-3150
+5 V
1
270 Ω
8
0.1 µF
2
+
–
VCC = 18 V
+ HVDC
7
Rg
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
3
6
4
5
Figure 25a. Recommended LED Drive and Application Circuit.
Q1
3-PHASE
AC
Q2
- HVDC
14
HCPL-315J
+5 V
CONTROL
INPUT
270 Ω
1
16
2
15
0.1 µF
+
–
FLOATING
SUPPLY
VCC = 18 V
+ HVDC
Rg
74XX
OPEN
COLLECTOR
3
14
GND 1
+5 V
3-PHASE
AC
6
270 Ω
CONTROL
INPUT
11
0.1 µF
7
VCC = 18 V
+
–
10
Rg
74XX
OPEN
COLLECTOR
8
9
GND 1
- HVDC
Figure 25b. Recommended LED Drive and Application Circuit (HCPL-315J).
Selecting the Gate Resistor
(Rg) to Minimize IGBT
Switching Losses.
Step 1: Calculate Rg Minimum
From the IOL Peak Specification. The IGBT and Rg in Figure
26 can be analyzed as a simple
RC circuit with a voltage supplied
by the HCPL-3150/315J.
(VCC – VEE - VOL)
Rg ≥ –––––––––––––––
IOLPEAK
(VCC – VEE - 1.7 V)
= ––––––––––––––––
IOLPEAK
(15 V + 5 V - 1.7 V)
= ––––––––––––––––––
0.6 A
= 30.5 Ω
The VOL value of 2 V in the previous equation is a conservative
value of VOL at the peak current
of 0.6 A (see Figure 6). At lower
Rg values the voltage supplied by
the HCPL-3150/315J is not an
ideal voltage step. This results in
lower peak currents (more
margin) than predicted by this
analysis. When negative gate
drive is not used VEE in the
previous equation is equal to zero
volts.
Step 2: Check the HCPL-3150/
315J Power Dissipation and
Increase Rg if Necessary. The
HCPL-3150/315J total power
dissipation (PT) is equal to the
sum of the emitter power (PE ) and
the output power (PO):
PT = PE + PO
PE = IF • VF • Duty Cycle
PO = PO(BIAS) + PO (SWITCHING)
= ICC• (VCC - VEE)
+ ESW(R G, QG) • f
For the circuit in Figure 26 with IF
(worst case) = 16 mA, Rg =
30.5 Ω, Max Duty Cycle = 80%,
Qg = 500 nC, f = 20 kHz and TA
max = 90°C:
PE = 16 mA • 1.8 V • 0.8 = 23 mW
PO = 4.25 mA • 20 V
+ 4.0 µJ• 20 kHz
= 85 mW + 80 mW
= 165 mW
> 154 mW (PO(MAX) @ 90°C
= 250 mW−20C• 4.8 mW/C)
15
HCPL-3150
+5 V
8
1
270 Ω
0.1 µF
2
+
–
VCC = 15 V
+ HVDC
7
Rg
Q1
CONTROL
INPUT
6
3
–
+
74XXX
OPEN
COLLECTOR
4
VEE = -5 V
3-PHASE
AC
5
Q2
- HVDC
Figure 26a. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive.
HCPL-315J
+5 V
CONTROL
INPUT
1
16
2
15
270 Ω
0.1 µF
+
–
FLOATING
SUPPLY
VCC = 15 V
+ HVDC
Rg
74XX
OPEN
COLLECTOR
3
14
–
+
VEE = -5 V
GND 1
+5 V
6
270 Ω
11
0.1 µF
CONTROL
INPUT
7
3-PHASE
AC
VCC = 15 V
+
–
10
Rg
74XX
OPEN
COLLECTOR
8
9
–
+
VCC = -5 V
GND 1
- HVDC
Figure 26b. HCPL-315J Typical Application Circuit with Negative IGBT Gate Drive.
PE
Parameter
IF
VF
Duty Cycle
Description
LED Current
LED On Voltage
Maximum LED
Duty Cycle
PO Parameter
ICC
VCC
VEE
ESW(Rg,Qg)
f
Description
Supply Current
Positive Supply Voltage
Negative Supply Voltage
Energy Dissipated in the HCPL-3150/315J for
each IGBT Switching Cycle (See Figure 27)
Switching Frequency
16
The value of 4.25 mA for I CC in
the previous equation was
obtained by derating the ICC max
of 5 mA (which occurs at -40°C)
to I CC max at 90°C (see Figure 7).
Since PO for this case is greater
than PO(MAX) , Rg must be
increased to reduce the HCPL3150 power dissipation.
PO(SWITCHING MAX)
= PO(MAX) - PO(BIAS)
= 154 mW - 85 mW
= 69 mW
PO(SWITCHINGMAX)
E SW(MAX) = –––––––––––––––
f
69 mW
= ––––––– = 3.45 µJ
20 kHz
For Qg = 500 nC, from Figure
27, a value of ESW = 3.45 µJ
gives a Rg = 41 Ω.
board design and is, therefore,
determined by the designer. The
value of θCA = 83°C/W was
obtained from thermal measurements using a 2.5 x 2.5 inch PC
board, with small traces (no
ground plane), a single HCPL3150 soldered into the center of
the board and still air. The
absolute maximum power
dissipation derating specifications
assume a θCAvalue of 83°C/W.
From the thermal mode in Figure
28a the LED and detector IC
junction temperatures can be
expressed as:
(
TJD = PE
LC
LC
•
DC
DC
LD
CA
Inserting the values for θLC and
θDC shown in Figure 28 gives:
θLC = 391°C/W
θDC = 119°C/W
TC
θCA = 83°C/W*
TA
Figure 28a. Thermal Model.
TJE and TJD should be limited to
125°C based on the board layout
and part placement (θCA) specific
to the application.
θ
θ
(–––––––––––––––
+θ )
θ +θ +θ
The steady state thermal model
for the HCPL-3150 is shown in
Figure 28a. The thermal
resistance values given in this
model can be used to calculate
the temperatures at each node for
a given operating condition. As
shown by the model, all heat
generated flows through θCA
which raises the case temperature
T C accordingly. The value of θCA
depends on the conditions of the
TJD
TJD = PE• 132°C/W + PD• 187°C/W + TA
= 45 mW• 132C/W + 250 mW
• 187°C/W + 70°C = 123°C
)
+ PD • (θDC||(θLD + θLC) + θCA ) + TA
θLD = 439°C/W
TJE = PE• 313°C/W + PD• 132°C/W + TA
= 45 mW• 313°C/W + 250 mW
• 132°C/W + 70°C = 117°C
TJE = PE • (θLC||(θLD + θDC) + θCA)
θLC • θDC
+ PD • ––––––––––––––––
+ θCA + TA
θLC + θDC + θLD
Thermal Model
(HCPL-3150)
TJE
For example, given PE = 45 mW,
PO = 250 mW, TA = 70°C and θCA
= 83°C/W:
TJE = PE • (230°C/W + θCA)
+ PD • (49°C/W + θCA) + TA
TJD = PE • (49°C/W + θCA)
+ PD • (104°C/W + θCA) + TA
TJE = LED junction temperature
TJD = detector IC junction temperature
TC = case temperature measured at the center of the package bottom
θLC = LED-to-case thermal resistance
θLD = LED-to-detector thermal resistance
θDC = detector-to-case thermal resistance
θCA = case-to-ambient thermal resistance
∗θCA will depend on the board design and the placement of the part.
17
Thermal Model DualChannel (SOIC-16)
HCPL-315J Optoisolator
Definitions
θ1, θ2, θ3, θ4, θ5, θ6, θ7, θ8, θ9,
θ10: Thermal impedances
between nodes as shown in
Figure 28b. Ambient
Temperature: Measured
approximately 1.25 cm above the
optocoupler with no forced air.
Description
This thermal model assumes that
a 16-pin dual-channel (SOIC-16)
optocoupler is soldered into an
8.5 cm x 8.1 cm printed circuit
board (PCB). These optocouplers
are hybrid devices with four die:
two LEDs and two detectors. The
temperature at the LED and the
detector of the optocoupler can
be calculated by using the
equations below.
θ1
LED 1
LED 2
θ3
θ2
θ4
θ5
DETECTOR 1
DETECTOR 2
θ10
θ7
θ8
θ6
θ9
AMBIENT
Figure 28b. Thermal Impedance Model for HCPL-315J.
∆T E1A = A11PE1 + A12PE2+A13 PD1+A 14PD2
PE1
PD1
PE2
PD2
∆T E2A = A21PE1 + A22PE2+A23 PD1+A 24PD2
∆T D1A = A31PE1 + A32PE2+A33 PD1+A 34PD2
∆T D2A = A41PE1 + A42PE2+A43 PD1+A 44PD2
where:
∆T E1A = Temperature difference between ambient and LED 1
∆T E2A = Temperature difference between ambient and LED 2
∆T D1A = Temperature difference between ambient and detector 1
∆T D2A = Temperature difference between ambient and detector 2
PE1 = Power dissipation from LED 1;
PE2 = Power dissipation from LED 2;
PD1 = Power dissipation from detector 1;
PD2 = Power dissipation from detector 2
Axy thermal coefficient (units in °C/W) is a function of thermal
impedances θ1 through θ10.
Thermal Coefficient Data (units in °C/W)
Part Number
A 11, A22
A 12, A21
A 13, A31
A 24, A42
A 14, A41
A 23, A32
A 33, A44
A 34, A43
HCPL-315J
198
64
62
64
83
90
137
69
Note: Maximum junction temperature for above part: 125°C.
LED Drive Circuit
Considerations for Ultra
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
shown in Figure 29. The HCPL3150/315J improves CMR
performance by using a detector
IC with an optically transparent
Faraday shield, which diverts the
capacitively coupled current away
from the sensitive IC circuitry.
How ever, this shield does not
eliminate the capacitive coupling
between the LED and optocoupler pins 5-8 as shown in
Figure 30. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 25), can achieve
15 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
Esw – ENERGY PER SWITCHING CYCLE – µJ
18
logic gate is less than VF(OFF), the
LED will remain off and no
common mode failure will occur.
7
Qg = 100 nC
Qg = 250 nC
Qg = 500 nC
6
5
VCC = 19 V
VEE = -9 V
4
3
2
1
0
0
20
40
60
80
100
Rg – GATE RESISTANCE – Ω
Figure 27. Energy Dissipated in the
HCPL-3150 for Each IGBT Switching
Cycle.
CMR with the LED On
(CMRH)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED current of 10 mA provides adequate
margin over the maximum I FLH of
5 mA to achieve 15 kV/µs CMR.
CMR with the LED Off
(CMRL)
A high CMR LED drive circuit
must keep the LED off
(VF ≤ VF(OFF)) during common
mode transients. For example,
during a -dVCM/dt transient in
Figure 31, the current flowing
through CLEDP also flows through
the RSAT and VSAT of the logic
gate. As long as the low state
voltage developed across the
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dVCM/dt
transient, since all the current
flowing through CLEDN must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMRL
performance. Figure 33 is an
alternative drive circuit which,
like the recommended application
circuit (Figure 25), does achieve
ultra high CMR performance by
shunting the LED in the off state.
Under Voltage Lockout
Feature
The HCPL-3150/315J contains an
under voltage lockout (UVLO)
feature that is designed to protect
the IGBT under fault conditions
which cause the HCPL-3150/315J
supply voltage (equivalent to the
fully-charged IGBT gate voltage)
to drop below a level necessary to
keep the IGBT in a low resistance
state. When the HCPL-3150/315J
output is in the high state and the
supply voltage drops below the
HCPL-3150/315J VUVLO- threshold
(9.5 <VUVLO- <12.0), the
optocoupler output will go into
the low state with a typical delay,
UVLO Turn Off Delay, of 0.6 µs.
When the HCPL-3150/315J
output is in the low state and the
supply voltage rises above the
HCPL-3150/315J VUVLO+
threshold (11.0 < VUVLO+ < 13.5),
the optocoupler will go into the
19
high state (assuming LED is
“ON”) with a typical delay, UVLO
TURN On Delay, of 0.8 µs.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-3150/315J includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices from the highto the low-voltage motor rails.
To minimize dead time in a given
design, the turn on of LED2
should be delayed (relative to the
turn off of LED1) so that under
worst-case conditions, transistor
Q1 has just turned off when
transistor Q2 turns on, as shown
in Figure 34. The amount of delay
necessary to achieve this conditions is equal to the maximum
value of the propagation delay
difference specification, PDDMAX,
which is specified to be 350 ns
over the operating temperature
range of -40°C to 100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal temperatures and test conditions since
the optocouplers under consideration are typically mounted in
close proximity to each other and
are switching identical IGBTs.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
8
1
2
7
2
3
6
3
5
4
1
maximum dead time will be. The
maximum dead time is equivalent
to the difference between the
maximum and minimum propagation delay difference specifications as shown in Figure 35. The
maximum dead time for the
HCPL-3150/315J is 700 ns
(= 350 ns - (-350 ns)) over an
operating temperature range of
-40°C to 100°C.
CLEDP
CLEDO1
8
CLEDP
7
CLEDO2
CLEDN
4
Figure 29. Optocoupler Input to Output
Capacitance Model for Unshielded Optocouplers.
+5 V
5
SHIELD
Figure 30. Optocoupler Input to Output
Capacitance Model for Shielded Optocouplers.
8
1
0.1
µF
CLEDP
+
VSAT
–
6
CLEDN
2
7
+
–
VCC = 18 V
ILEDP
3
4
•••
6
CLEDN
Rg
SHIELD
5
•••
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dVCM/dt.
+ –
VCM
Figure 31. Equivalent Circuit for Figure 25 During Common Mode Transient.
20
8
1
8
1
+5 V
+5 V
CLEDP
2
3
Q1
CLEDN
CLEDP
7
2
6
3
5
4
7
6
CLEDN
ILEDN
4
SHIELD
Figure 32. Not Recommended Open Collector
Drive Circuit.
Figure 33. Recommended LED Drive Circuit
for Ultra-High CMR.
VOUT1
Q1 ON
Q1 ON
Q1 OFF
Q1 OFF
Q2 ON
Q2 ON
VOUT2
ILED2
5
ILED1
ILED1
VOUT1
SHIELD
Q2 OFF
VOUT2
Q2 OFF
ILED2
tPHL MAX
tPHL MIN
tPLH MIN
tPHL MAX
tPLH
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 34. Minimum LED Skew for Zero Dead Time.
MIN
tPLH MAX
(tPHL-tPLH) MAX
= PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 35. Waveforms for Dead Time.
12
(12.3, 10.8)
10
(10.7, 9.2)
8
6
4
2
0
(10.7, 0.1)
0
5
10
(12.3, 0.1)
15
20
(VCC - VEE ) – SUPPLY VOLTAGE – V
Figure 36. Under Voltage Lock Out.
OUTPUT POWER – PS, INPUT CURRENT – IS
VO – OUTPUT VOLTAGE – V
14
800
PS (mW)
IS (mA)
700
600
500
400
300
200
100
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
Figure 37a. HCPL-3150: Thermal Derating
Curve, Dependence of Safety Limiting
Value with Case Temperature per IEC/EN/
DIN EN 60747-5-2.
1400
PSI OUTPUT
PSI – POWER – mW
1200
PSI INPUT
1000
800
600
400
200
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
Figure 37b. HCPL-315J: Thermal Derating Curve,
Dependence of Safety Limiting Value with Case
Temperature per IEC/EN/DIN EN 60747-5-2.
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Obsoletes 5989-0783EN
March 1, 2005
5989-2142EN