ON NOIH2SM1000S-HWC Has2 image sensor Datasheet

NOIH2SM1000A
HAS2 Image Sensor
INTRODUCTION
Scope
This datasheet details the ratings, physical, geometrical,
electrical and electro-optical characteristics, and test- and
inspection-data for the High Accuracy Star Tracker (HAS2)
CMOS active pixel image sensor (CMOS APS).
The device described in this document is protected by US
patent 6,225,670 and others.
www.onsemi.com
• Always store the devices in a shielded environment that
Table 10 on page 9 provides a summary of the type
variants. The complete list of specifications for each type
variant is given in the specifications tables.
All specifications are given at 22 ±3°C, under nominal
clocking and bias conditions. Exceptions are noted in the
‘Remarks’ field.
protects against ESD damage (at least a non-ESD
generating tray and a metal bag).
• Always wear a wrist strap when handling the devices
and use ESD safe gloves.
• The HAS2 is classified as class 1A (JEDEC
classification - [AD02]) device for ESD sensitivity.
For proper handling and storage conditions, refer to the
ON Semiconductor application note AN52561.
Maximum Rating
Return Material Authorization (RMA)
Component Type Values
Figure 4 on page 24 shows the physical dimensions of the
assembled component. The geometrical information in
Figure 3 on page 10 describes the position of the die in the
package.
ON Semiconductor packages its image sensor products in
a clean room environment under strict handling procedures
and ships all image sensor products in ESD-safe,
clean-room-approved shipping containers. Products
returned to ON Semiconductor for failure analysis should be
handled under these same conditions and packed in its
original packing materials, or the customer may be liable for
the product.
Pin Assignment
Storage Information
Table 11 on page 9 specifies the maximum ratings. Do
not exceed these ratings at any times, during use or storage.
Physical Dimension and Geometrical Information
Figure 25 on page 39 contains the pin assignment. The
figure contains a schematic drawing and a pin list. A detailed
functional description of each pin is available in Pin List on
page 35.
The components must be stored in a dust-free and
temperature-, humidity-and ESD-controlled environment.
• Store devices in special ESD-safe trays such that the
glass window is never touched.
• Close the trays with EDS-safe rubber bands.
• Seal the trays in an ESD-safe conductive foil in clean
room conditions.
• For transport and storage outside a clean room, pack the
trays in a second ESD-save bag that is sealed in clean
room.
Soldering Instructions
Soldering is restricted to manual soldering only. No wave
or reflow soldering is allowed. For manual soldering, the
following restrictions are applicable:
• Solder 1 pin on each of the four sides of the sensor.
• Cool down for a minimum period of 1 minute before
soldering another pin on each of the four sides.
• Repeat soldering of 1 pin on each side, including a 1
minute cool down period.
Additional Information
The HAS sensor is subject to the standard European
export regulations for dual use products. A Certificate of
Conformance will be issued upon request at no additional
charge. The CoC refers to this datasheet version.
Handling Precautions
The component is susceptible to damage by electro-static
discharge. Therefore, use suitable precautions for protection
during all phases of manufacture, testing, packaging,
shipment, and any handling. Follow these guidelines:
• Always manipulate devices in an ESD controlled
environment.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 14
ITAR Information
All the HAS2 type variants are ITAR-free components.
1
Publication Order Number:
NOIH2SM1000A/D
NOIH2SM1000A
Table 1. ORDERING INFORMATION
Marketing Part Number
Description
NOIH2SM1000T-HHC
HAS2 Mono, Flight Model, Level 2
NOIH2SM1000A-HHC
HAS2 Mono, Engineering Model
NOIH2SM1000S-HHC
HAS2 Mono, Flight Model, Level 1
NOIH2SM1000A-HWC
HAS2 Mono Windowless, Engineering Model
NOIH2SM1000S-HWC
HAS2 Mono Windowless, Flight Model, Level 1
Package
84-pin JLCC
ORDERING CODE DEFINITION
For information on device numbering and ordering codes, please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
APPLICABLE DOCUMENTS
The following documents form part of this specification:
Table 2. APPLICABLE DOCUMENTS
No.
Reference
Title
AD01
NPD−0064422
Image Sensor Characterization Standard
AD02
JESD22-A114-B
Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)
AD03
12MBE83443F
Process Identification Document for HAS2
AD04
12MON56972E
Visual Inspection for FM devices
1. Lot acceptance and screening are based on ESCC 9020. Please note that Lot Acceptance and Screening on page 6 − is valid for the Flight
Model Level 1 devices. For more information on Flight Model 1 Windowless devices, please contact [email protected]
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NOIH2SM1000A
DETAILED INFORMATION
Deviations from Generic Specification
The optical quality of the glass must have the
specifications in Table 15 on page 11.
The anti reflective coating has a reflection coefficient less
than 1.3% absolute and less than 0.8% on average, over a
bandwidth from 440 nm to 1100 nm.
Lot acceptance and screening are based on ESCC 9020.
See Lot Acceptance and Screening on page 6 and document
NPD−0067186 for more information.
Mechanical Requirements
Level 2 versus Level 1 Differences
Dimension Check
The dimensions of the components specified here is
checked and must comply with the specifications and the
tolerances indicated in Figure 4 on page 24
Geometrical Characteristics
The geometrical characteristics of the components
specified here is checked and must comply with the
specifications and tolerances given in Figure 4 on page 24
and Figure 3 on page 10
Mass
The maximum mass of the components specified here is
specified in Table 14 on page 10
HAS2 Flight Model Level 2 devices differ from Level 1
devices in Lot Acceptance and Screening Tests:
• 100% screening is applied with burn-in limited to 168 h
• Devices will be fully tested at room temperature and
85°C.
• X/Y die placement is relaxed to ±200 mm.
• Mismatching between odd and even columns in
Destructive Readout is allowed but shall stay in the
limit of 127 LSB.
• The defect and particles specification will be the same
as for the Engineering Model - NOIH2SM1000A-HHC
– with the exception of the defective columns which are
not allowed in the Level 2 devices. Refer to Table 10
“Type Variant Summary” on page 9.
• Endurance testing during Wafer LAT is limited to a
1000 h burn in and will be performed on 3 unscreened
parts.
• Prior to endurance testing and total dose testing, a
stabilization bake of 48 hrs, followed by a 168 hrs
burn-in, shall be performed.
• During Wafer LAT, the Electro-optical measurements
are limited on 2 parts (1 from endurance and 1 from
radiation testing).
• For each assembly batch (manufacturing-lot), 2
screened devices will be made available for a DPA test.
An assembly batch is defined as a group of parts which
have been assembled within a time window of less than
one week. The DPA devices can be rejected devices
(glass lid cosmetic defects, electrical defects,…) but
have to be screened through the same thermal steps as
the HAS2 “level2”. The DPA test will be carried out by
ON Semiconductor as a customer courtesy.
Prior to DPA testing, the following tests are performed:
Solderability and Resistance to Solvents (marking
permeability).
Materials and Finishes
The materials and finishes is as specified in this document.
Where a definite material is not specified, a material which
enables the components to meet the performance
requirements of this specification must be used.
Case
The case is hermetically sealed and must have a ceramic
body and a glass window.
Table 3. CASE
Type
JLCC−84
Material
Black Alumina BA−914
Thermal expansion coefficient
7.6 x 10−6/K
Hermeticity
< 5 x 10−7 atms. cm3/s
Thermal resistance
(Junction to case)
3.633°C/W
Lead Material and Finish
Table 4. LEAD MATERIAL AND FINISH
Lead Material
KOVAR
1e Finish
Nickel, min 2 mm
2nd
Gold, min 1.5 mm
Finish
NOTE: As the glass lid removal is a best effort activity,
the DPA test cannot be 100% guaranteed.
• Assembly lot acceptance testing is not performed.
Window
The window material is a BK7G18 glass lid with
anti-reflective coating applied on both sides.
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3
NOIH2SM1000A
Marking
Data Pack
Each set of devices will have a data pack which will be
made available to the customer. The data pack consists of:
• CoC form referring to the applicable specification
• Calibration data
• Screening Report
• Life Test Report and Radiation (Total Dose) Test
Report for each wafer lot
• Electrical Test Report
• Spectral response data
• Visual Inspection Report
• DPA Test Report
12
General
The marking must consist of lead identification and
traceability information.
Lead Identification
An index to pin 1 must be located on the top of the package
in the position defined in Figure 4 on page 24. The pin
numbering is counter clock-wise, when looking at the
top-side of the component.
Traceability Information
Each component must be marked such that complete
traceability is maintained.
The component must have a number as follows:
32
11
33
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
NNNN = Serial Number
1
84
75
53
74
54
Figure 1. Product Marking
Table 5. PACKAGE MARK DECODER
Orderable Part Number
Package Mark: Line 1
Package Mark: Line 2
Package Mark: Line 3
NOIH2SM1000T-HHC
NOIH2SM1000T
-HHC NNNN
AWLYYWW
NOIH2SM1000A-HHC
NOIH2SM1000A
-HHC NNNN
AWLYYWW
NOIH2SM1000S-HHC
NOIH2SM1000S
-HHC NNNN
AWLYYWW
NOIH2SM1000A-HWC
NOIH2SM1000A
-HWC NNNN
AWLYYWW
NOIH2SM1000S-HWC
NOIH2SM1000S
-HWC NNNN
AWLYYWW
where NNNN- serialized number controlled manually by ON Semiconductor, BELGIUM
where DD-MM-YYYY represents the lot assembly date
NOIH2SM1000T-HHC has a Minimum Order Quantity of 10
Electrical and Electro−optical Measurements
timing diagrams in Figure 35 on page 46 and Figure 37 on
page 48.
NOTE: The given bias and power supply settings imply
that the devices are measured in ‘soft-reset’
condition.
Electrical and Electro−optical Measurements at High and
Low Temperature
Table 19 on page 15 and Table 20 on page 16 list the
parameters to be measured to verify electrical and
electro-optical specifications. Unless otherwise specified,
Electrical and Electro−optical Measurements at Reference
Temperature
The parameters to be measured to verify the electrical and
electro-optical specifications are given in Table 18 on
page 14 and Table 27 on page 23. Unless otherwise
specified, the measurements must be performed at a
environmental temperature of 22 ±3°C.
For all measurements, the nominal power supply, bias,
and clocking conditions apply. The nominal power supply
and bias conditions are given in Table 28 on page 23; the
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NOIH2SM1000A
the measurements must be performed at –40 (–5 +0) °C and
at +85 (+5 –0) °C.
Circuits for Electrical and Electro−optical Measurements
Circuits for performing the electro−optical tests in
Table 18 on page 14 and Table 27 on page 23 are shown in
Figure 49 on page 58 to Figure 52 on page 58.
Electrical Circuits for High Temperature Reverse Bias
Burn-in
Not Applicable
Electrical Circuits for Power Burn-in
Circuits to perform the power burn-in test are shown in
Figure 48 on page 57 and Figure 49 on page 58 of this
specification.
Burn−in Test
Environmental and Endurance Tests
Parameter Drift Values
The parameter drift values for power burn-in are specified
in Table 21 on page 17. Unless otherwise specified, the
measurements must be conducted at an environmental
temperature of 22 ±3°C and under nominal power supply,
bias, and timing conditions.
In addition to the drift value requirements, the devices do
not exceed the limit values of any parameter, as indicated in
Table 18 on page 14.
Conditions for High Temperature Reverse Bias Burn-in
Not Applicable
Conditions for Power Burn-in
The conditions for power burn-in is specified in Table 24
on page 19 of this specification.
Electrical and Electro-optical Measurements on
Completion of Environmental Test
The parameters to be measured on completion of
environmental tests are listed in Table 25 on page 20. Unless
otherwise stated, the measurements must be performed at a
environmental temperature of 22 ±3°C. Measurements of
dark current must be performed at 22 ±1°C and the actual
environmental temperature must be reported with the test
results.
Electrical and Electro-optical Measurements At
Intermediate Point During Endurance Test
The parameters to be measured at intermediate points
during endurance test of environmental tests are listed in
Table 25 on page 20. Unless otherwise stated, the
measurements must be performed at an environmental
temperature of 22 ±3°C.
Electrical and electro-optical Measurements on Completion
of Endurance Test
The parameters to be measured on completion of
endurance tests are listed in Table 25 on page 20. Unless
otherwise stated, the measurements must be performed at a
environmental temperature of 22 ±3°C.
Conditions for Operating Life Test
The conditions for operating life tests must be as specified
in Table 24 on page 19 of this specification.
Electrical Circuits for Operating Life Test
Circuits for performing the operating life test are shown
in Figure 49 on page 58 and next ones of this specification.
Conditions for High Temperature Storage Test
The temperature to be applied must be the maximum
storage temperature specified in Table 11 on page 9 of this
specification.
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5
NOIH2SM1000A
Total Dose Radiation Test
Electrical and Electro-optical Measurements
The parameters to be measured, prior to, during and on
completion of the irradiation are listed in Table 27 on
page 23 of this specification. Only devices that meet the
specification in Table 18 on page 14 of this specification
must be included in the test samples.
Application
The total dose radiation test must be performed in
accordance with the requirements of ESCC Basic
Specification 22900.
Parameter Drift Values
The allowable parameter drift values after total dose
irradiation are listed in Table 22 on page 18 . The parameters
shown are valid after a total dose of 50 krad and
168 h / 100°C annealing.
Bias Conditions
Continuous bias must be applied during irradiation testing
as shown in Figure 49 on page 58 and next ones of this
specification.
Lot Acceptance and Screening
This section describes the Lot Acceptance Testing (LAT)
and screening on the HAS2 FM devices. All tests on device
level must be performed on screened devices (see Table 9 on
page 7)
Wafer Lot Acceptance
This is the acceptance of the silicon wafer lot. This must
be done on every wafer lot that is used for the assembly of
flight models.
Table 6.
Test
Test Method
Number of Devices
Test Condition
Wafer processing data review
PID
NA
NA
SEM
ESCC 21400
4 naked dies
NA
Total dose test
ESCC 22900
3 devices
50 krad, not to exceed 3.6 krad/hr
Endurance test
MIL-STD-883 Method 1005
6 devices
2000h at +125°C
Before and after total dose test and endurance test:
Table 15. Three glass lids are chosen randomly from the lot
and measured in detail. The results are compared with
Figure 5 on page 25.
Package Lot Acceptance
• Five packages are chosen randomly from the lot and
measured in detail. The results are compared with
Figure 4 on page 24.
• A solderability test is covered in the assembly lot
acceptance tests (Table 7)
• Electrical measurements before and after at high, low,
•
•
and room temperature. See Table 18 on page 14, Table
19 on page 15 and Table 20 on page 16 of this
specification.
Visual inspection before and after
Detailed electro-optical measurements before and after
Glass Lot Acceptance
Transmission and reflectance curves that are delivered
with each lot must be compared with the specifications in
Table 7. ASSEMBLY LOT ACCEPTANCE
Test
Test Method
Number of Devices
Test Condition
Special assembly house in
process control
Bond strength test
MIL-STD-883 method 2011
2
Assembly house geometrical data
review
Review
All
Solder ability
MIL-STD883, method 2003
3
Terminal strength
MIL-STD 883, method 2004
Marking permanence
ESCC 24800
Geometrical measurements
12MBE83937F
5
Temperature cycling
MIL-STD 883, method 1010
5
Moisture resistance
JEDEC Std. Method A101-B
Temperature cycling around dew
point
ESCC9020 8.15(a) phase 2
D
D
Condition B
50 cycles
–55°C / +125°C
240 h at 85°C / 85%
5
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6
Phase 2
NOIH2SM1000A
Table 7. ASSEMBLY LOT ACCEPTANCE
Test
Test Method
Residual Gas Analysis
Number of Devices
Test Condition
MIL-STD-883, method 1018
2
Procedure 1
Die shear test
MIL-STD-883, method 2019
4
N/A
Bond pull test
MIL-STD-883, method 2011
DPA
All wires
• Fine leak test + gross leak test
NOTES: As the glass lid is removed from the package
prior to DPA, the results of the DPA cannot be
guaranteed.
HAS2 does not comply with the moisture limit
of ESCC9020 − see document NPD−0067186.
• Electrical measurements conform to Table 18 on
Fine- and gross-leak tests must be performed using the
following methods:
Fine Leak test: MIL-STD-883, Test Method 1014,
Condition A, 30 psi for 24 h
Gross Leak test: MIL-STD-883, Test Method 1014,
Condition C, 30 psi for 24 h
•
The required leak rate for fine leak testing is
5 x 10−7 atms.cm3/s
Before and after the following tests are done:
page 14 of this specification
Detailed visual inspection
Table 8. PERIODIC TESTING
Test
Test Method
Number of
Devices
Test Condition
Mechanical shock
MIL-STD 883, method 2002
2
B - 5 shocks, 1500 g – 0.5 ms – ½ sine, 6 axes
Mechanical
vibration
MIL-STD 883, method 2007
2
A - 4 cycles, 20 g 80 to 2000 Hz,
0.06 inch 20 to 80 Hz,
3 axes
Die shear test
MIL-STD-883 method 2019
2
N/A
Bond pull test
MIL-STD-883 method 2011
DPA
All wires
Fine- and gross-leak tests must be performed using the
following methods:
Fine Leak Test: MIL-STD-883, Test Method 1014,
Condition A, 30 psi for 24 h
Gross Leak Test: MIL-STD-883, Test Method 1014,
Condition C, 30 psi for 24 h
NOTE: As the glass lid is removed from the package
prior to DPA, the results of the DPA cannot be
guaranteed.
Periodic testing is required every two years. Before and
after the following tests are done:
• Electrical measurements conform to Table 18 on
page 14
• Detailed visual inspection
• Fine leak test + gross leak test
The required leak rate for fine leak testing is
5 x 107 atms.cm3/s
Table 9. SCREENING
No.
Test
Test Method
Number of Devices
Test Condition
1
Stabilization bake
MIL-STD-883 method 1008
All
48h at 125°C
2
HCRT Electrical measurements
12MBE83443F
All
HT +85°C
LT –40°C
RT +22°C
3
Visual inspection
12MON56972E
All
4
Die placement measurements
12MBE83937F
All
5
XRAY
ESCC 20900
All
6
Fine leak test
MIL-STD-883 method 1014
All
A
7
Gross leak test
MIL-STD-883 method 1014
All
C
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NOIH2SM1000A
Table 9. SCREENING
No.
Test
Test Method
Number of Devices
Test Condition
8
Temperature cycling
MIL-STD-883 method 1010
All
B - 10 cycles
–55°C +125°C
9
Biased Burn-in
MIL-STD-883 method 1015
All
240 h at +125°C
10
Mobile Particle Detection
MIL-STD-883 method 2020
All
A
11
Fine leak test
MIL-STD-883 method 1014
All
A
12
Gross leak test
MIL-STD-883 method 1014
All
C
13
HCRT Electrical measurements
12MBE83443F
All
HT +85°C
LT –40°C
RT +22°C
14
Final Visual Inspection
12MON56972E
All
Figure 2. HAS2 Assembly LAT Flow
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NOIH2SM1000A
TABLES AND FIGURES
Specification Tables
Table 10. TYPE VARIANT SUMMARY
HAS2 Type Variants
Engineering Model
Flight Model
Dead pixels
100
20
Bright pixels in FPN image
50
20
Bad pixels in PRNU image
Optical quality (see Optical Quality − Definitions on page 66)
150
50
Bad columns
5
0
Bad rows
5
0
2 adjacent bright pixels
25
2
4 or more adjacent bright pixels
10
0
DSNU defects at 22 dec BOL
1200
1000
DSNU defects at 22 dec EOL
1500
1250
N/A
N/A
Mobile particles > 20 mm
0
0
Fixed particles on focal plane > 20 mm
0
0
Mobile particles > 10 mm and < 20 mm
20
10
Particles < 10 mm
N/A
N/A
Wafer lot acceptance (see section Wafer Lot Acceptance on page 6)
NO
Yes
Glass lot acceptance (see section Glass Lot Acceptance on page 6)
NO
Yes
Assembly lot acceptance (Table 7 on page 6)
NO
Yes
Periodic testing (Table 8 on page 7)
NO
Yes
Screening (Table 9 on page 7)
NO
Yes
Calibration data
NO
Yes
Visual Inspection + particle mapping
NO
Yes
Bright pixel clusters
Particle contamination
Fixed particles outside focal plane
Fixed particles on focal plane > 10 mm and < 20 mm
Table 11. MAXIMUM RATINGS
No.
Characteristic
Min
Typ
Max
Unit
1
Any supply voltage except VDD_RES
–0.5
3.3
+7.0
V
2
Supply voltage at VDD_RES
–0.5
3.3
+5.0
V
3
Voltage on any input terminal
–0.5
3.3
Vdd + 0.5
V
4
Soldering temperature
NA
NA
260
°C
5
Operating temperature
–40
NA
+85
°C
6
Storage temperature
–55
NA
+125
°C
Remarks
3.3 V for normal operation; up to
5 V for increased full well capacity.
Hand soldering only; See Soldering Instructions on page 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NOIH2SM1000A
Detailed Specifications − All Type Variants
Table 12. GENERAL SPECIFICATIONS
No.
Characteristic
Min
Typ
Max
Unit
Remarks
1
Image sensor format
N/A
1024 x 1024
N/A
pixels
2
Pixel size
N/A
18
N/A
mm
3
ADC resolution
N/A
12
N/A
bit
10-bit accuracy at 5 Msamples/sec
Remarks
Table 13. SILICON PARTICLE CONTAMINATION SPECIFICATIONS
No.
1
Characteristic
Optical quality: Particle max size
Min
Typ
Max
Unit
N/A
N/A
20
mm
See Type Variant Summary on
page 9
Table 14. MECHANICAL SPECIFICATIONS
Parameter
Die
(Refer to Figure 3
“Die Placement”
on page 10)
Description
Min
Typ
Max
Units
Flatness of image area (Note 1)
NA
Flatness of glass lid (Note 2)
NA
7.4
NA
mm
90
150
mm
Mass
7.7
7.85
8.0
g
Die thickness
(−10)
740
(10)
mm
Die center, X offset to the center of package (A)
(−50)
0
(+50)
mm
Die center, Y offset to the center of the package (A)
(−50)
0
(+50)
mm
Die position, X tilt
−0.3
0
0.3
deg
Die position, Y tilt
−0.3
0
0.3
deg
Die placement accuracy in package
(−50)
(+50)
mm
Die rotation accuracy
−0.4
0.4
deg
Optical center referenced from package center (X-dir) (B)
(−50)
+571
(+50)
mm
Optical center referenced from package center (Y-dir) (B)
(−50)
+109.5
(+50)
mm
Distance from top of the die surface to top of the glass lid
(−0.31)
1.78
(0.31)
mm
Total Thickness
Refer to Package Diagram
(Figure 4 on page 24)
1. Peak-to-peak at 22 ±3°C. Specified by the foundry over an entire 8-inch wafer.
2. Towards ceramic package.
y
x
A: Package center/Die center
Pin 1
B: Optical center
Figure 3. Die Placement
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NOIH2SM1000A
Table 15. GLASS LID SPECIFICATIONS
No.
Characteristic
Min
Typ
Max
Unit
26.7 x 26.7
26.8 x 26.8
26.9 x 26.9
mm
Thickness
1.4
1.5
1.6
mm
2a
Spectral range for optical coating of
window
440
NA
1100
nm
2b
Reflection coefficient for window
NA
<0.8
<1.3
%
3
Optical quality:
Scratch max width
Scratch max number
Dig max size
Dig max number
N/A
N/A
1a
XY size
1b
Remarks
Over bandwidth indicated in 2a
mm
10
5
60
25
Table 16. ENVIRONMENTAL SPECIFICATIONS
No.
Min
Typ
Max
Unit
1
Operating temperature
Characteristic
–40
NA
+85
°C
Remarks
2
Storage temperature
–55
NA
+125
°C
3
Sensor total dose radiation tolerance
N/A
42
N/A
krad (Si)
Tested for functionality up to
300 krad, 42 krad is guaranteed
4
Sensor SEL threshold with ADC enabled
NA
NA
>110
MeV cm3
mg-1
Equivalent LET value
Lower storage temperatures (up to
–80°C) have been tested and the
device survives, but this is not a
fully qualified temperature.
Table 17. ELECTRICAL SPECIFICATIONS
No
Min
Typ
Max
Unit
1
Total power supply current stand-by
Characteristic
15
19
23
mA
2
Total power supply current, operational
24
28.5
33.5
mA
ADC at 5 MHz sampling rate
measured
3
Power supply current to ADC,
operational: analog + digital
17
19
21
mA
ADC at 5 MHz sampling rate
measured
4
Power supply current to image core,
operational
14
15.5
17
mA
5
Input impedance digital input
3
NA
NA
MW
6
Input impedance ADC input
3
NA
NA
MW
7
Output amplifier voltage range
2.2
2.45
2.6
V
8
Output amplifier gain setting 0
NA
1
NA
–
Nominal 1
measured reference
9
Output amplifier gain setting 1
1.9
2.1
2.3
–
Nominal 2
relative to setting 0
10
Output amplifier gain setting 2
3.8
4.1
4.4
–
Nominal 4
relative to setting 0
11
Output amplifier gain setting 3
7.2
7.7
8.2
–
Nominal 8
relative to setting 0
12
Output amplifier offset setting 0
0.9
0.95
1.0
V
0 decodes to middle value
13
Output amplifier offset setting 31
1.31
1.36
1.41
V
14
Output amplifier offset setting 32
0.5
0.56
0.62
V
15
Output amplifier offset setting 63
0.88
0.93
0.98
V
16
ADC ladder network resistance
NA
1.8
NA
kW
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11
Remarks
Typical value
NOIH2SM1000A
Table 17. ELECTRICAL SPECIFICATIONS
No
Characteristic
Min
Typ
Max
Unit
17
ADC differential nonlinearity
NA
7
11
lsb
18
ADC integral nonlinearity
NA
8
18
lsb
19
ADC setup time
5
NA
NA
ns
Analog_in stable to CLK_ADC rising
20
ADC hold time
10
NA
NA
ns
Analog_in stable after CLK_ADC
rising edge
21
ADC delay time
NA
NA
20
ns
22
ADC latency
NA
6.5
NA
-
Cycles of CLK_ADC
23
ADC ideal input range
0.85
NA
2.0
V
VLOW_ADC to VHIGH_ADC
24
Saturation voltage output swing
1.20
1.49
NA
V
VDD_RES = 3.3 V
25
Output range
0.8
NA
2.1
V
Measured with PGA in unity gain,
offset = 0.8 V, low is dark, high is
bright.
26
Linear range of pixel signal swing
40
50
0.75
NA
keV
Measured within ±1%
27
Linear range
60
82
NA
ke-
Measured within ±5%
28
Full well charge
90
100
NA
ke-
Measured with VDD_RES = 3.3 V
29
Quantum efficiency x fillfactor
NA
45
NA
%
Measured between 500 nm and
650 nm. Refer to section Spectral
Response on page 26 for complete
curve.
30
Spectral response
NA
33.3
NA
%
Measured average over
400 nm – 900 nm.
31
Charge to voltage conversion factor
NA
16.9
NA
mV/e-
At pixel
32
Charge to voltage conversion factor
13
14.8
15.6
mV/e-
Measured at output SIGNAL_OUT,
unity gain
33a
Temporal noise (soft reset)
NA
55
95
e-
Dark noise, with DR/DS, internal
ADC
33b
Temporal noise (hard reset)
N/A
75
125
e-
Dark noise, with DR/DS, internal
ADC
33c
Temporal noise (HTS reset)
NA
65
110
e-
Dark noise, with DR/DS, internal
ADC
34a
Temporal noise (NDR soft reset)
NA
75
100
e-
34b
Temporal noise (NDR hard reset)
NA
75
100
e-
34c
Temporal noise (NDR HTS reset)
NA
70
100
e-
35
ADC quantization noise
NA
7
NA
e-
36a
Local fixed pattern noise standard
deviation (hard reset)
NA
110
160
e-
With DR/DS
36b
Local fixed pattern noise standard
deviation (soft reset)
NA
70
140
e-
With DR/DS
36c
Local fixed pattern noise standard
deviation (HTS reset)
NA
95
140
e-
With DR/DS
37a
Global fixed pattern noise standard
deviation (hard reset)
NA
115
180
e-
With DR/DS
37b
Global fixed pattern noise standard
deviation (soft reset)
NA
90
140
e-
With DR/DS
37c
Global fixed pattern noise standard
deviation (HTS reset)
NA
110
180
e-
With DR/DS
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12
Remarks
NOIH2SM1000A
Table 17. ELECTRICAL SPECIFICATIONS
No
Characteristic
Min
Typ
Max
Unit
Remarks
37d
Global fixed pattern noise standard
deviation (NDR, soft reset)
14
15
18
e-
With NDR/CDS and external ADC
37e
Local Column fixed pattern noise
standard deviation (NDR, soft reset)
14
15
18
e-
With NDR/CDS and external ADC
38
Average dark signal
NA
190
400
e-/s
At 22 ±2°C die temp, BOL
see “Dark Current vs Temperature
Model” on page 30
39
Average dark signal
NA
5550
8730
e-/s
At 22 ±2°C die temp, EOL (25 krad)
40
Dark signal temperature dependency
5
5.8
8
°C
Sensor temperature increase for
doubled average dark current.
41
Local dark signal non-uniformity standard
deviation
NA
260
400
e-/s
At 22 ±2°C die temp, BOL
96% of BOL average
42
Global dark signal non-uniformity
standard deviation
N/A
275
500
e-/s
At 22 ±2°C die temp, BOL
96% of BOL average
43
Local photo response non-uniformity,
standard deviation
NA
0.8
1.0
%
Of average response
44
Global photo response non-uniformity,
standard deviation
NA
1.8
5
%
Of average response
45
MTF X direction
NA
0.35
NA
NA
At Nyquist
measured
46
MTF Y direction
NA
0.35
NA
-
At Nyquist
measured
47
Pixel to pixel crosstalk X direction
NA
9.8
NA
%
Of total source signal – see
“Pixel−to−Pixel Cross Talk”
on page 34 for 2−D plot
48
Pixel to pixel crosstalk Y direction
NA
9.8
NA
%
Of total Source signal – see
“Pixel−to−Pixel Cross Talk”
on page 34 for 2−D plot
49
Anti-blooming capability
200
1000
NA
50
Pixel rate
NA
5
10
MHz
51
Temperature sensor transfer curve
NA
–4.64
NA
mV/_C
BOL
52
Temperature sensor output signal range,
Min to Max (typical)
800
NA
1700
mV
BOL
53
Temperature sensor linearity
NA
3
NA
mV
BOL
54
Temperature sensor transfer curve
NA
–4.64
NA
mV/_C
EOL
55
Temperature sensor output signal range,
Min to Max (typical)
800
NA
1700
NA
EOL
The following formulas are applicable to convert % Vsat
and mV/s into e- and e-/s:
Typical
Other Definitions
• Conversion gain for HAS: 14.8 mV/e• Definition for local measurements: 32 x 32 pixels
• Definition for global measurements: Full pixel array
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13
NOIH2SM1000A
Table 18. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS AT ROOM TEMPERATURE 225C
No.
Characteristic
Min
Typ
Max
Unit
Remarks
1
Total power supply current stand-by
15
19
23
mA
2
Total power supply current, operational
24
28.5
33.5
mA
ADC at 5 MHz sampling rate
3
Power supply current to ADC,
operational
17
19
21
mA
ADC at 5 MHz sampling rate
4
Power supply current to image core,
operational
14
15.5
17
mA
5
Input impedance digital input
3
NA
NA
MW
6
Input impedance ADC input
3
NA
NA
MW
7
Output impedance digital outputs
NA
NA
400
W
8
Output impedance analog output
NA
NA
1
kW
9
Output amplifier voltage range
2.2
2.45
2.6
V
10
Output amplifier gain setting 0
NA
1
NA
-
Nominal 1
measured reference
11
Output amplifier gain setting 1
1.9
2.1
2.3
-
Nominal 2
relative to setting 0
12
Output amplifier gain setting 2
3.8
4.1
4.4
-
Nominal 4
relative to setting 0
13
Output amplifier gain setting 3
7.2
7.7
8.2
-
Nominal 8
relative to setting 0
14
Output amplifier offset setting 0
0.9
0.95
1.0
V
0 decodes to middle value
15
Output amplifier offset setting 31
1.31
1.36
1.41
V
16
Output amplifier offset setting 32
0.5
0.56
0.62
V
17
Output amplifier offset setting 63
0.88
0.93
0.98
V
18
ADC Differential nonlinearity
N/A
7
11
lsb
19
ADC Integral nonlinearity
N/A
8
18
lsb
20
Saturation voltage output swing
1.20
1.49
NA
V
VDD_RES = 3.3 V
21
Output range
0.8
NA
2.1
V
PGA in unity gain, offset = 0.8 V, low
is dark, high is bright.
22a
Temporal noise (soft reset)
NA
55
95
e-
Dark noise, with DR/DS, internal
ADC
22b
Temporal noise (hard reset)
NA
75
125
e-
Dark noise, with DR/DS, internal
ADC
22c
Temporal noise (HTS reset)
NA
65
110
e-
Dark noise, with DR/DS, internal
ADC
23a
Temporal noise (NDR soft reset)
NA
75
100
e-
23b
Temporal noise (NDR hard reset)
NA
75
100
e-
23c
Temporal noise (NDR HTS reset)
NA
70
100
e-
24
ADC quantization noise
NA
7
NA
e-
25a
Local fixed pattern noise standard
deviation (soft reset)
N/A
70
140
e-
With DR/DS
25b
Local fixed pattern noise standard
deviation (hard reset)
NA
110
160
e-
With DR/DS
25c
Local fixed pattern noise standard
deviation (HTS reset)
NA
95
140
e-
With DR/DS
26a
Global fixed pattern noise standard
deviation (soft reset)
NA
90
140
e-
With DR/DS
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14
NOIH2SM1000A
Table 18. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS AT ROOM TEMPERATURE 225C
No.
Characteristic
Min
Typ
Max
Unit
Remarks
26b
Global fixed pattern noise standard
deviation (hard reset)
NA
115
180
e-
With DR/DS
26c
Global fixed pattern noise standard
deviation (HTS reset)
NA
110
180
e-
With DR/DS
27
Average dark signal
NA
190
400
e-/s
At 22 ±2°C die temp
28
Local dark signal non-uniformity standard
deviation
NA
260
400
e-/s
At 22 ±2°C
29
Global dark signal non-uniformity
standard deviation
NA
275
500
e-/s
At 22 ±2°C
30
Local photo response non-uniformity,
standard deviation
NA
0.8
1.0
%
Of average response
31
Global photo response non-uniformity,
standard deviation
NA
1.8
5
%
Of average response
Table 19. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS AT HIGH TEMPERATURE +855C
No.
Characteristic
Min
Typ
Max
Unit
Remarks
1
Total power supply current stand-by
15
19
23
mA
2
Total power supply current, operational
24
28.5
33.5
mA
ADC at 5 MHz sampling rate
3
Power supply current to ADC, operational
17
19
21
mA
ADC at 5 MHz sampling rate
4
Power supply current to image core,
operational
14
15.5
17
mA
5
Input impedance digital input
3
NA
NA
MW
6
Input impedance ADC input
3
NA
NA
MW
7
Output impedance digital outputs
NA
NA
400
W
8
Output impedance analog output
NA
NA
1
kW
9
Output amplifier voltage range
2.2
2.45
2.6
V
10
Output amplifier gain setting 0
NA
1
NA
-
Nominal 1
measured reference
11
Output amplifier gain setting 1
1.9
2.1
2.3
-
Nominal 2
relative to setting 0
12
Output amplifier gain setting 2
3.7
4.0
4.3
-
Nominal 4
relative to setting 0
13
Output amplifier gain setting 3
7.0
7.5
8.0
-
Nominal 8
relative to setting 0
14
Output amplifier offset setting 0
0.91
0.97
1.03
V
0 decodes to middle value
15
Output amplifier offset setting 31
1.33
1.38
1.43
V
16
Output amplifier offset setting 32
0.52
0.59
0.66
V
17
Output amplifier offset setting 63
0.91
0.96
1.01
V
18
ADC Differential nonlinearity
NA
8
11
lsb
19
ADC Integral nonlinearity
NA
10
18
lsb
20
Saturation voltage output swing
1.20
1.52
NA
V
VDD_RES = 3.3 V
21
Output range
0.8
NA
2.1
V
PGA in unity gain, offset = 0.8 V,
low is dark, high is bright.
22a
Temporal noise (soft reset)
NA
66
110
e-
DR/DS
22b
Temporal noise (hard reset)
NA
85
125
e-
DR/DS
22c
Temporal noise (HTS reset)
NA
73
110
e-
DR/DS
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15
NOIH2SM1000A
Table 19. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS AT HIGH TEMPERATURE +855C
No.
Characteristic
Min
Typ
Max
Unit
Remarks
23a
Temporal noise (NDR soft reset)
NA
200
400
e-
23b
Temporal noise (NDR hard reset)
NA
170
300
e-
23c
Temporal noise (NDR HTS reset)
NA
65
125
e-
24
ADC quantization noise
NA
7
NA
e-
25a
Local fixed pattern noise standard deviation
(soft reset)
NA
82
160
e-
With DR/DS
25b
Local fixed pattern noise standard deviation
(hard reset)
NA
95
160
e-
With DR/DS
25c
Local fixed pattern noise standard deviation
(HTS reset)
NA
100
160
e-
With DR/DS
26a
Global fixed pattern noise standard deviation (soft reset)
NA
80
140
e-
With DR/DS
26b
Global fixed pattern noise standard deviation (hard reset)
NA
97
160
e-
With DR/DS
26c
Global fixed pattern noise standard deviation (HTS reset)
NA
115
300
e-
With DR/DS
27
Local photo response non-uniformity, standard deviation
NA
0.74
1.0
%
Of average response
28
Global photo response non-uniformity,
standard deviation
NA
1.7
5
%
Of average response
Table 20. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS AT LOW TEMPERATURE –405C
No.
Characteristic
Min
Typ
Max
Unit
Remarks
1
Total power supply current stand-by
15
19
23
mA
2
Total power supply current, operational
24
28.5
33.5
mA
ADC at 5 MHz sampling rate
3
Power supply current to ADC, operational
17
19
21
mA
ADC at 5 MHz sampling rate
4
Power supply current to image core,
operational
14
15.5
17
mA
5
Input impedance digital input
3
NA
NA
MW
6
Input impedance ADC input
3
NA
NA
MW
7
Output impedance digital outputs
NA
NA
400
W
8
Output impedance analog output
NA
NA
1
kW
9
Output amplifier voltage range
2.2
2.45
2.6
V
10
Output amplifier gain setting 0
NA
1
NA
-
Nominal 1
measured reference
11
Output amplifier gain setting 1
1.9
2.1
2.3
-
Nominal 2
relative to setting 0
12
Output amplifier gain setting 2
3.8
4.1
4.4
-
Nominal 4
relative to setting 0
13
Output amplifier gain setting 3
7.2
7.7
8.2
-
Nominal 8
relative to setting 0
14
Output amplifier offset setting 0
0.89
0.94
0.99
V
0 decodes to middle value
15
Output amplifier offset setting 31
1.30
1.35
1.40
V
16
Output amplifier offset setting 32
0.46
0.53
0.6
V
17
Output amplifier offset setting 63
0.86
0.92
0.98
V
18
ADC differential nonlinearity
N/A
7
11
lsb
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16
NOIH2SM1000A
Table 20. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS AT LOW TEMPERATURE –405C
No.
Characteristic
Min
Typ
Max
Unit
Remarks
19
ADC integral nonlinearity
N/A
11
18
lsb
20
Saturation voltage output swing
1.20
1.49
NA
V
VDD_RES = 3.3 V
21
Output range
0.8
NA
2.1
V
PGA in unity gain, offset = 0.8 V,
low is dark, high is bright.
22a
Temporal noise (soft reset)
NA
59
100
e-
DR/DS
22b
Temporal noise (hard reset)
NA
77
125
e-
DR/DS
22c
Temporal noise (HTS reset)
NA
70
125
e-
DR/DS
23a
Temporal noise (NDR soft reset)
NA
80
125
e-
23b
Temporal noise (NDR hard reset)
NA
80
125
e-
23c
Temporal noise (NDR HTS reset)
NA
75
125
e-
24
ADC quantization noise
NA
7
NA
e-
25a
Local fixed pattern noise standard
deviation (soft reset)
NA
70
140
e-
With DR/DS
25b
Local fixed pattern noise standard
deviation (hard reset)
NA
90
140
e-
With DR/DS
25c
Local fixed pattern noise standard
deviation (HTS reset)
NA
100
160
e-
With DR/DS
26a
Global fixed pattern noise standard
deviation (soft reset)
NA
70
140
e-
With DR/DS
26b
Global fixed pattern noise standard
deviation (hard reset)
NA
95
140
e-
With DR/DS
26c
Global fixed pattern noise standard
deviation (HTS reset)
NA
120
180
e-
With DR/DS
27
Local photo response non-uniformity, standard deviation
NA
0.8
1.0
%
Of average response
measured
28
Global photo response non-uniformity,
standard deviation
NA
1.8
5
%
Of average response
measured
Table 21. DRIFT LIMITS
Electrical and Electro-optical Measurements at Room Temperature +22°C
Characteristic
Min
Target
Max
Units
−7
0
7
mA
Total power supply current stand-by
−6.4
0
6.4
mA
ADC Differential nonlinearity
−1.1
0
1.1
lsb
Average dark signal
−200
−10
180
e-/s
Global dark signal non-uniformity standard deviation
−230
3
230
e-/s
Output amplifier offset setting 0
−100
2.2
100
mV
Total power supply current, operational
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17
NOIH2SM1000A
Table 22. PARAMETER DRIFT VALUES FOR RADIATION TESTING
Electrical and Electro-optical Measurements at Room Temperature +22°C
No.
Characteristic
Typical Value
Max Drift
Unit
18.5
2
mA
Remarks
1
Total power supply current stand-by
2
Total power supply current, operational
29
3
mA
ADC at 5 MHz sampling rate
3
Power supply current to ADC, operational
19
2
mA
ADC at 5 MHz sampling rate
4
Power supply current to image core, operational
15.5
2
mA
5
Output impedance digital outputs
N/A
20
W
6
Output impedance analog output
N/A
20
W
7
Output amplifier voltage range
2.45
0.2
V
8
Output amplifier gain setting 0
1
N/A
-
Nominal 1
measured reference
9
Output amplifier gain setting 1
2.1
0.2
-
Nominal 2
relative to setting 0
10
Output amplifier gain setting 2
4.1
0.3
-
Nominal 4
relative to setting 0
11
Output amplifier gain setting 3
7.7
0.5
-
Nominal 8
relative to setting 0
12
Output amplifier offset setting 0
0.95
0.1
V
0 decodes to middle value
13
Output amplifier offset setting 31
1.36
0.1
V
14
Output amplifier offset setting 32
0.56
0.1
V
15
Output amplifier offset setting 63
0.93
0.1
V
16
ADC differential nonlinearity
7
1
lsb
17
ADC integral nonlinearity
8
1
lsb
18
Saturation voltage output swing
1.49
0.2
V
VDD_RES = 3.3 V
19
Output range
N/A
0.2
V
PGA in unity gain, offset = 0.8 V, low is
dark, high is bright.
20a
Temporal noise (soft reset)
55
+30
e-
Dark noise, with DR/DS, internal ADC
20b
Temporal noise (hard reset)
75
+30
e-
Dark noise, with DR/DS, internal ADC
20c
Temporal noise (HTS reset)
65
+30
e-
Dark noise, with DR/DS, internal ADC
21a
Temporal noise (NDR soft reset)
75
+40
e-
21b
Temporal noise (NDR hard reset)
75
+40
e-
21c
Temporal noise (NDR HTS reset)
70
+40
e-
22
ADC quantization noise
7
NA
e-
23a
Local fixed pattern noise standard deviation
(soft reset)
70
+200
e-
With DR/DS
23b
Local fixed pattern noise standard deviation
(hard reset)
110
+100
e-
With DR/DS
23c
Local fixed pattern noise standard deviation
(HTS reset)
95
+100
e-
With DR/DS
24a
Global fixed pattern noise standard deviation
(soft reset)
90
+200
e-
With DR/DS
24b
Global fixed pattern noise standard deviation
(hard reset)
115
+100
e-
With DR/DS
24c
Global fixed pattern noise standard deviation
(HTS reset)
110
+100
e-
With DR/DS
25
Average dark signal
190
+6000
e-/s
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18
At 22 ±2°C die temp
NOIH2SM1000A
Table 22. PARAMETER DRIFT VALUES FOR RADIATION TESTING
Electrical and Electro-optical Measurements at Room Temperature +22°C
No.
Characteristic
Typical Value
Max Drift
Unit
Remarks
26
Local dark signal non-uniformity standard
deviation
260
+1500
e-/s
At 22 ±2°C
27
Global dark signal non-uniformity standard
deviation
275
+1500
e-/s
At 22 ±2°C
28
Local photo response non-uniformity, standard deviation
0.8
+0.1
%
Of average response
29
Global photo response non-uniformity, standard deviation
1.8
+0.3
%
Of average response
Table 23. CONDITIONS FOR HIGH TEMPERATURE REVERSE BIAS BURN−IN
No.
Characteristics
Symbol
Test Condition
Unit
Not applicable
Table 24. CONDITIONS FOR POWER BURN−IN AND OPERATING LIFE TESTS
No.
Characteristics
Symbol
Test Condition
Unit
Tamb
125
°C
Vdd
3.3
V
1
Ambient temperature
2
All power supplies
3
Bias conditions
See Figures 49, 50, 51, 52 on page 58
4
Clock frequency
10
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19
MHz
NOIH2SM1000A
Table 25. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS ON COMPLETION OF ENVIRONMENTAL
TESTS AND AT INTERMEDIATE POINTS AND ON COMPLETION OF ENDURANCE TESTING
Electrical and Electro-optical Measurements at Room Temperature +22°C
No.
Characteristic
Min
Typ
Max
Unit
Remarks
1
Total power supply current stand-by
15
19
23
mA
2
Total power supply current, operational
24
28.5
33.5
mA
ADC at 5 MHz sampling rate
measured
3
Power supply current to ADC, operational
17
19
21
mA
at 5 MHz
4
Power supply current to image core,
operational
14
15.5
17
mA
5
Input impedance digital input
3
NA
NA
MW
6
Input impedance ADC input
3
NA
NA
MW
7
Output impedance digital outputs
NA
NA
400
W
8
Output impedance analog output
NA
NA
1
kW
9
Output amplifier voltage range
2.2
2.45
2.6
V
10
Output amplifier gain setting 0
NA
1
NA
-
Nominal 1
measured reference
11
Output amplifier gain setting 1
1.9
2.1
2.3
-
Nominal 2
relative to setting 0
12
Output amplifier gain setting 2
3.8
4.1
4.4
-
Nominal 4
relative to setting 0
13
Output amplifier gain setting 3
7.2
7.7
8.2
-
Nominal 8
relative to setting 0
14
Output amplifier offset setting 0
0.90
0.95
1.0
V
0 decodes to middle value
15
Output amplifier offset setting 31
1.31
1.36
1.41
V
16
Output amplifier offset setting 32
0.50
0.56
0.62
V
17
Output amplifier offset setting 63
0.88
0.93
0.98
V
18
ADC Differential nonlinearity
NA
7
11
lsb
19
ADC Integral nonlinearity
NA
8
18
lsb
20
Saturation voltage output swing
1.20
1.49
N/A
V
VDD_RES = 3.3 V
21
Output range
0.8
NA
2.1
V
PGA in unity gain, offset = 0.8 V,
low is dark, high is bright.
22a
Temporal noise (soft reset)
NA
55
95
e-
DARK noise, with DR/DS, internal
ADC
22b
Temporal noise (hard reset)
NA
75
125
e-
Dark noise, with DR/DS, internal
ADC
22c
Temporal noise (HTS reset)
NA
65
110
e-
Dark noise, with DR/DS, internal
ADC
23a
Temporal noise (NDR soft reset)
NA
75
100
e-
23b
Temporal noise (NDR hard reset)
NA
75
100
e-
23c
Temporal noise (NDR HTS reset)
NA
70
100
e-
24
ADC quantization noise
NA
7
NA
e-
25a
Local fixed pattern noise standard deviation
(soft reset)
NA
70
140
e-
With DR/DS
25b
Local fixed pattern noise standard deviation
(hard reset)
NA
110
160
e-
With DR/DS
25c
Local fixed pattern noise standard deviation
(HTS reset)
NA
95
140
e-
With DR/DS
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NOIH2SM1000A
Table 25. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS ON COMPLETION OF ENVIRONMENTAL
TESTS AND AT INTERMEDIATE POINTS AND ON COMPLETION OF ENDURANCE TESTING
Electrical and Electro-optical Measurements at Room Temperature +22°C
No.
Characteristic
Min
Typ
Max
Unit
Remarks
26a
Global fixed pattern noise standard
deviation (soft reset)
NA
90
140
e-
With DR/DS
26b
Global fixed pattern noise standard
deviation (hard reset)
NA
115
180
e-
With DR/DS
26c
Global fixed pattern noise standard
deviation (HTS reset)
NA
110
180
e-
With DR/DS
27
Average dark signal
NA
190
400
e-/s
At 22 ±2°C die temp
28
Local dark signal non-uniformity standard
deviation
NA
260
400
e-/s
At 22 ±2°C
29
Global dark signal non-uniformity standard
deviation
NA
275
500
e-/s
At 22 ±2°C
30
Local photo response non-uniformity, standard deviation
NA
0.8
1.0
%
Of average response
31
Global photo response non-uniformity, standard deviation
NA
1.8
5
%
Of average response
Table 26. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS DURING AND ON COMPLETION OF
TOTAL-DOSE IRRADIATION TESTING (50krad)
Electrical and Electro-optical Measurements at Room Temperature +22°C
No.
Characteristic Symbol
Min
Typ
Max
Unit
Remarks
1
Total power supply current stand-by
15
19
23
mA
2
Total power supply current, operational
24
28.5
33.5
mA
3
Power supply current to ADC, operational
17
19
21
mA
4
Power supply current to image core, operational
14
15.5
17
mA
5
Output impedance digital outputs
NA
NA
400
W
6
Output impedance analog output
NA
NA
1
kW
7
Output amplifier voltage range
2.2
2.45
2.6
V
8
Output amplifier gain setting 0
NA
1
NA
-
Nominal 1
measured reference
9
Output amplifier gain setting 1
1.9
2.1
2.3
-
Nominal 2
relative to setting 0
10
Output amplifier gain setting 2
3.8
4.1
4.4
-
Nominal 4
relative to setting 0
11
Output amplifier gain setting 3
7.2
7.7
8.2
-
Nominal 8
relative to setting 0
12
Output amplifier offset setting 0
0.90
0.95
1.0
V
0 decodes to middle value
13
Output amplifier offset setting 31
1.31
1.36
1.41
V
14
Output amplifier offset setting 32
0.50
0.56
0.62
V
15
Output amplifier offset setting 63
0.88
0.93
0.98
V
16
ADC Differential nonlinearity
N/A
8
11
lsb
17
ADC Integral nonlinearity
N/A
9
18
lsb
18
Saturation voltage output swing
1.20
1.49
N/A
V
VDD_RES = 3.3 V
19
Output range
0.8
N/A
2.1
V
PGA in unity gain, offset = 0.8 V, low
is dark, high is bright.
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21
ADC at 5 MHz sampling rate
NOIH2SM1000A
Table 26. ELECTRICAL AND ELECTRO-OPTICAL MEASUREMENTS DURING AND ON COMPLETION OF
TOTAL-DOSE IRRADIATION TESTING (50krad)
Electrical and Electro-optical Measurements at Room Temperature +22°C
No.
Characteristic Symbol
Min
Typ
Max
Unit
Remarks
20
Temporal noise (soft reset)
NA
55
95
e-
Dark noise, with DR/DS, internal
ADC
21
Temporal noise (hard reset)
NA
75
125
e-
Dark noise, with DR/DS, internal
ADC
22a
Temporal noise (HTS reset)
NA
65
110
e-
Dark noise, with DR/DS, internal
ADC
22b
Temporal noise (NDR soft reset)
NA
75
100
e-
22c
Temporal noise (NDR hard reset)
NA
75
100
e-
23a
Temporal noise (NDR HTS reset)
NA
70
100
e-
23b
ADC quantization noise
NA
7
NA
e-
23c
Local fixed pattern noise standard deviation (soft reset)
NA
70
350
e-
With DR/DS
24
Local fixed pattern noise standard deviation (hard reset)
NA
110
160
e-
With DR/DS
25a
Local fixed pattern noise standard deviation (HTS reset)
NA
95
200
e-
With DR/DS
25b
Global fixed pattern noise standard deviation (soft reset)
NA
90
350
e-
With DR/DS
25c
Global fixed pattern noise standard deviation (hard reset)
NA
115
180
e-
With DR/DS
26a
Global fixed pattern noise standard deviation (HTS reset)
NA
110
200
e-
With DR/DS
26b
Average dark signal
NA
5550
8730
e-/s
At 22 ±2°C die temp
26c
Local dark signal non-uniformity standard
deviation
NA
260
2000
e-/s
At 22 ±2°C
27
Global dark signal non-uniformity standard
deviation
NA
275
2000
e-/s
At 22 ±2°C
28
Local photo response non-uniformity, standard deviation
NA
0.8
1.0
%
Of average response
29
Global photo response non-uniformity,
standard deviation
NA
1.8
5
%
Of average response
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NOIH2SM1000A
Table 27. ELECTRO−OPTICAL MEASUREMENTS ON THE OPTICAL BENCH
No.
Min
Typ
Max
Unit
1
Linear range of pixel signal swing
Characteristic Symbol
40
50
0.75
NA
keV
Measured within ±1%
Remarks
2
Linear range
60
82
NA
ke-
Measured within ±5%
3
Full well charge
90
100
NA
ke-
Measured
VDD_RES = 3.3 V
4
Quantum efficiency x Fillfactor
NA
45
NA
%
Measured between 500 nm and
650 nm. See Specification Figures
on page 24 for complete curve
5
Spectral Response
NA
33.3
-
%
Measured average over
400 nm – 900 nm.
6
Charge to voltage conversion factor
NA
16.9
-
mV/e-
at pixel
7
Charge to voltage conversion factor
13
14.8
15.6
mV/e-
Measured at output SIGNAL_OUT,
unity gain
8
MTF X direction
NA
0.35
NA
-
at Nyquist measured
9
MTF Y direction
NA
0.35
NA
-
at Nyquist measured
10
Pixel to pixel crosstalk X direction
NA
9.8
NA
%
of total source signal – see Specification Figures on page 24 for
2−D plot
11
Pixel to pixel crosstalk Y direction
NA
9.8
NA
%
of total source signal – see Specification Figures on page 24 for
2−D plot
12
Anti-blooming capability
NA
1000
NA
Ke-
predicted value
Table 28. TYPICAL POWER SUPPLY SETTINGS AND SENSOR SETTINGS
Power Supply Settings
ADC_VLOW
0.85 V
ADC_VHIGH
2.0 V
V_ADC_DIGITAL
3.3 V
V_ADC_ANALOG
3.3 V
VDDD
3.3 V
VDDA
3.3 V
VRES
3.3 V for SR / 4.2 V for HR
VPIX
3.3 V (for HTS switched to 0.75 V)
Sensor Settings
Read Out Modes
Destructive – Nondestructive
Integration Time
195 ms
Gain Setting
Unity
Offset Setting
0
X Clock Period
100 ns
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23
NOIH2SM1000A
Specification Figures
JLDCC84
CASE 114AK
ISSUE A
Figure 4. 84−Pin JLCC Package Diagram
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24
NOIH2SM1000A
Figure 5. Glass Lid Dimensions
Figure 6. HAS2 Package Photo
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25
NOIH2SM1000A
Response Curves
Spectral Response
0.3
60 %
50 %
40 %
0.25
Spectral response [A/W]
30 %
0.2
20 %
0.15
0.1
10 %
0.05
0
400
500
600
700
800
900
1000
Wavelength [nm]
Figure 7. Measured Spectral Response of HAS Rad−hard Pixel (Black Curve Indicates Average Spectral Response
50
45
measured average curve
smoothed trend
40
QE x FF [%]
35
30
25
20
15
10
5
0
400
500
600
700
800
900
1000
Wavelength [nm]
Figure 8. Average Measured Spectral Response of HAS Rad−hard Pixel Recalculated to QExFF
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26
NOIH2SM1000A
Photo−response Curve
1.6
pix 1
pix 2
pix 3
pix 4
1.4
Output voltage [V]
1.2
1
0.8
0.6
0.4
0.2
0
0
20000
40000
60000
80000
100000
120000
140000
Number of electrons
Figure 9. Pixel Response Curve: Photo−electrons versus Signal Voltage
Fit to the linear response curve with the same conversion
gain (solid black line). The dashed lines indicate linear
response curves with –5% and +5% conversion gain.
A detailed analysis is performed in the range < 4000 e-.
The dashed lines corresponds to soft reset. The others to hard
reset.
Figure 10. Pixel Response Curve < 4000 e−
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27
NOIH2SM1000A
gain 4 (4.54)
2
gain 2 (2.27)
gain 8 (8.55)
Output voltage [V]
1.5
gain 1 (1)
1
0.5
0
0
20000
40000
60000
80000
100000
120000
Number of electrons [e−]
Figure 11. Measured Response Curves of Two Pixels on Two Devices at Different Gain Setting
Table 29. OVERVIEW OF THE OFFSET AT DIFFERENT GAIN SETTINGS
Device
1
6
Average
Average
Gain Setting
Offset
[V]
[V]
[V]
Offset drift [mV]
1
offset_g1
0.86
0.85
0.86
0
2
offset_g2
0.93
0.91
0.92
65
4
offset_g4
1.02
0.99
1.00
149
8
offset_g8
1.18
1.14
1.16
303
Fixed Pattern Noise
Figure 12 shows a log linear plot of the fixed pattern noise in destructive readout before and after radiation.
FPN DR Histogram TID
100000
BOL
4KRad TID
13KRad TID
20KRad TID
41KRad TID
# Pixels
10000
1000
100
10
1
100
150
200
250
300
350
2^12 [DN]
Figure 12. Typical FPN Histogram in DR Before and After TID
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28
400
NOIH2SM1000A
Figure 13 shows a log linear plot of the fixed pattern noise in destructive readout before and after a 2000 h life test, which
can be considered as EOL 41 behavior.
DR Histogram BOL - EOL
100000
BOL
EOL
10000
# Pixels
1000
100
10
1
200
220
240
260
280
300
320
340
2^12 [DN]
Figure 13. FPN Histogram in DR Before and After 2000 h Life Test
Figure 14 shows a log linear plot of the fixed pattern noise in nondestructive readout before and after a 2000 h life test, which
can be considered as EOL 42 behavior.
NDR Reset Level Histogram BOL − EOL
100000
BOL
EOL
# Pixels
10000
1000
100
10
1
0
100
200
300
400
500
600
700
800
900
1000
2^12 [DN]
Figure 14. FPN Histogram in NDR Before and After 2000 h Life Test
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NOIH2SM1000A
Dark Current vs. Temperature Model
1000000
100000
Aver ag e D ark Current [e−/s]
10000
0.1082x
y = 16.336e
2
R = 0.9995
1000
100
10
Theoretical Curve
1
-60 -40 -20020 406080 100
0.1
T emp er atu r e [d eg C]
Figure 15. Temperature Dependence of the Dark Current (in e/s) Measured on a Sample
Following model is consistent with what has been
measured for typical values:
Following model is consistent with what has been
measured for worst case values:
with
DC the dark current in e/s
DC0 the dark current at 30°C and 0 krad = 300 e/s
TID the total ionizing dose (in krad(Si))
T the temperature (in °C)
aDC the slope of the curve at 30°C = 325 e/s/krad(Si)
DTDC,d1 = 5.8°C and DTDC,d2 = 7.1°C
DCNU0 the dark current non-uniformity at 30°C and
0 krad = 230 e/s
aDCNU the slope of the curve at 30°C = 33.6 e/s/krad(Si)
DTDCNU,d1 = 9.5°C and DTDCNU,d2 = 9.5°C
T0 = 30°C
with
DC the dark current in e/s
DC0 the dark current at 30°C and 0 krad = 550 e/s
TID the total ionizing dose (in krad(Si))
T the temperature (in °C)
aDC the slope of the curve at 30°C = 480 e/s/krad(Si)
DTDC,d1,L = 6.6°C and DTDC,d2,L = 8°C for T < T0
DTDC,d1,H = 5°C and DTDC,d2,H = 6.5°C for T > T0
DCNU0 the dark current non-uniformity at 30°C and
0 krad = 400 e/s
aDCNU the slope of the curve at 30°C = 45 e/s/krad(Si)
DTDCNU,d1,L = 10.5°C and DTDCNU,d2,L = 10.5°C
for T < T0
DTDCNU,d1,H = 8.5°C and DTDCNU,d2,H = 8.5°C for
T > T0
T0 = 30°C
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NOIH2SM1000A
DCNU Distributions
Figure 16 and Figure 17 show the distributions of the dark current in mV/s and e/s respectively for a number of devices and
the average distribution.
10000
ext dev 1
ext dev 6
ext dev 10
1000
int dev 1
int dev 6
int dev 10
100
Relative frequency
average
10
1
0.1
0.01
0.001
020 40 60 80100120140160180200
Dark current [mV/s]
Figure 16. Dark Current Distribution (in mV/s) at 255C Ambient Temperature
10000
ext dev 1
ext dev 6
1000
ext dev 10
int dev 1
int dev 6
int dev 10
100
Relative frequency
average
10
1
0.1
0.01
0.001
0200040006000800010000 12000
Dark cu rren t [e/s]
Figure 17. Dark Current Distribution (in e/s) at 255C Ambient Temperature
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31
NOIH2SM1000A
Figure 18 and Figure 19 show the cumulative distributions of the dark current in mV/s and e/s respectively for a number of
devices and the average cumulative distribution.
100
ext dev 1
ext dev 6
ext dev 10
int dev 1
10
C umu la ti ve fr e que ncy
int dev 6
int dev 10
average
1
0.1
0.01
0.001
0.0001
0 20406080100 120 140 160 180 200
Dark current [mV/s]
Figure 18. Cumulative Dark Current Distribution (in mV/s) at 255C Ambient Temperature
100
ext dev 1
ext dev 6
ext dev 10
10
int dev 1
Cumulative frequency
int dev 6
int dev 10
average
1
0.1
0.01
0.001
0.0001
0200040006000800010000 12000
Dark current [e/s]
Figure 19. Cumulative Dark Current Distribution (in e/s) at 255C Ambient Temperature
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32
NOIH2SM1000A
Figure 20 shows the percentage of pixels versus their
normalized dark current for the measurement and for a
Gaussian distribution with the same average value and
standard deviation. In the measured distribution, about
1.1–1.2% of the pixels exhibit a dark current that exceeds the
3s limit that is typically used to exclude pixels from the
measurements (about 10 times larger than for Gaussian
distribution)
100
measurement
Gaussian distribution
Per centage of pixels [%]
10
1
0.1
0.01
0.001
0.0001
0
1
2
3
4
5
6
7
8
9
10
(dark current − average dark current) / (st. dev. dark current)
Figure 20. Comparison between Measured Distribution and Gaussian Distribution
Figure 21 shows the DSNU distributions during TID irradiation
DSNU distribution during Total Dose Irra diation
an d after annealing
10000
Pre Rad
4 Krad
14 Krad
20 Krad
41 Krad
168 h HT Annealing
3 mnth RT Annealing
Number of pixels
1000
Biased
Conditions
100
10
1
0
500
1000
1500
2000
2500
3000
3500
ADU value [0 − 2^12]
Figure 21. DSNU Distributions during TID Irradiation
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4000
4500
NOIH2SM1000A
Temperature Sensor
1.4
5
measurement points
fitted curve
deviation
4
1.36
3
1.34
2
1.32
1
1.3
0
1.28
-1
1.26
-2
1.24
-3
1.22
-4
1.2
D eviati o n fro m fi tted cu rve [mV]
Output volta ge [V]
1.38
-5
35
30
40
45
50
55
60
65
70
75
Tempe rature [C]
Figure 22. Temperature Sensor Voltage Sensitivity
(The solid line indicates a linear fit with 1.38 V as output voltage at 305C and a slope of −4.64 mV/5C)
Pixel−to−Pixel Crosstalk
0.0
0.2
1.3
0.2
0.0
0.2
1.3
9.8
1.3
0.2
1.3
9.8
49.0
9.8
1.3
0.2
1.3
9.8
1.3
0.2
0.0
0.2
1.3
0.2
0.0
Figure 23. Cross Talk with Central Pixel Uniformity Illuminated with 100%.
Estimation from Knife−edge Measurements
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NOIH2SM1000A
PACKAGE INFORMATION
Pin Type Information
Power Supply Considerations
The following conventions are used in the pin list.
It is recommended to use one regulator for all digital
supply pins together, one regulator for the sensor core analog
supplies together, and one regulator for the ADC analog
supply (if used). Analog ground returns must be of very low
impedance, as short-term peaks of 200 mA can be
encountered.
The ADC can be disabled by connecting all of its power
and ground pins to system ground, leaving all other pins
open.
Table 30. PIN TYPES
AI
Analog Input
AO
Analog Output
AB
Analog Bias
DI
Digital Input
DO
Digital Output
VDD
Supply Voltage
Pin List
GND
Supply Ground
Doubled-up pins have the same pin name, but are
indicated with (*). These pins are at the same potential on the
chip.
Table 31. PIN LIST
Pin No.
Name
Type
Purpose
Power Supply and Ground Connections
10
VDD_DIG (1)
VDD
33
VDD_DIG (2)
VDD
11
GND_DIG (1)
GND
32
GND_DIG (2)
GND
8
VDD_ANA (1)
VDD
35
VDD_ANA (2)
VDD
9
GND_ANA (1)
GND
34
GND_ANA (2)
GND
55
GND_ANA (3)
GND
73
GND_ANA (4)
GND
58
VDD_PIX (1)
VDD
70
VDD_PIX (2)
VDD
74
VDD_RES
VDD
Logic power, 3.3 V
Logic ground
Analog power, 3.3 V
Analog ground
Pixel array power, 3.3 V
Reset power, 3.3 V, optionally up to 5 V for increased full well
Sensor Biasing
75
GND_AB
AB
Anti-blooming ground, connect to system ground or to a low-impedance 1 V
source for enhanced anti-blooming
52
NBIAS_DEC
AB
Connect with 200kW to VDD_ANA, decouple with 100 nF to GND_ANA
51
NBIAS_PGA
AB
Connect with 200kW to VDD_ANA, decouple with 100 nF to GND_ANA
50
NBIAS_UNI40
AB
Connect with 75kW to VDD_ANA, decouple with 100 nF to GND_ANA
49
NBIAS_LOAD
AB
Connect to GND_ANA
48
NBIAS_PRECHARGE
AB
Connect with 110kW to VDD_ANA, decouple with 100 nF to GND_ANA
47
NBIAS_PREBUF
AB
Connect with 200kW to VDD_ANA, decouple with 100 nF to GND_ANA
46
NBIAS_COLUMN
AB
Connect with 110kW to VDD_ANA, decouple with 100 nF to GND_ANA
Analog Signal Input and Outputs
31
SIGNAL_OUT
AO
Output of PGA, range ##.. ## V, straight polarity i.e. a low output voltage corresponds to a dark pixel reading.
60
A_IN1
AI
Input to PGA input multiplexer.
59
A_IN2
AI
Input to PGA input multiplexer.
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NOIH2SM1000A
Table 31. PIN LIST
Pin No.
Name
Type
Purpose
57
A_IN3
AI
Input to PGA input multiplexer.
56
A_IN4
AI
Input to PGA input multiplexer.
54
PHOTODIODE
AO
Reference photodiode
Logic Control Inputs and Status Outputs
71
A9
DI
Parallel sensor programming interface shared address/data bus, MSB
69
A8
DI
68
A7
DI
67
A6
DI
66
A5
DI
65
A4
DI
64
A3
DI
63
A2
DI
62
A1
DI
61
A0
DI
Parallel sensor programming interface shared address/data bus, LSB
72
LD_Y
DI
Load strobe: copy A[9..0] into Y1 start register
76
LD_X
DI
Load strobe: copy A[9..0] into X1 start register
77
LD_REG
DI
Load strobe: copy A[7..0] into parameter register indicated by A[9..8]
78
RES_REGn
DI
Asynchronous reset for internal registers
82
SYNC_YRD
DI
Initialize Y read shift register (YRD) to position indicated by Y1 start register
84
SYNC_YRST
DI
Initialize Y reset shift register (YRST) to position indicated by Y1 start register
36
SYNC_XRD
DI
Initialize X read shift register (XRD) to position indicated by X1 start register
83
CLK_YRD
DI
Advance shift register YRD one position
1
CLK_YRST
DI
Advance shift register YRST one position
25
CLK_X
DI
Advance shift register XRD; note: two clock cycles needed for one pixel output
53
EOS
DO
End Of Scan monitor output for YRD,YRST,XRD shift registers, selected through
an internal register
2
YRST_YRDn
DI
Enable YRD to address the pixel array when ‘0’;
Enable YRST to address the pixel array when ‘1’
4
RESET
DI
Reset the line pointed to by YRST (YRST_YRDn = ‘1’) or pointed to by YRD
(YRST_YRDn = ‘0’)
37
BLANK
DI
Assert when in line blanking / non-readout phase
3
SEL
DI
Select for readout the line pointed to by YRST (YRST_YRDn = ‘1’) or YRD
(YRST_YRDn = ‘0’)
5
PRECHARGE
DI
Pre-charge column bus
6
R
DI
Sample the selected line’s levels onto the column amplifier reset level bus
7
S
DI
Sample the selected line’s levels onto the column amplifier signal level bus
38
CAL
DI
Calibrate PGA
ADC
30
IN_ADC
AI
Analog input to ADC
27
23
CLK_ADC
DI
ADC conversion clock, pixel rate, latency is 6.5 cycles
DATA_11
DO
ADC data output, MSB
22
DATA_10
DO
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NOIH2SM1000A
Table 31. PIN LIST
Pin No.
Name
Type
Purpose
21
DATA_9
DO
20
DATA_8
DO
19
DATA_7
DO
18
DATA_6
DO
17
DATA_5
DO
16
DATA_4
DO
15
DATA_3
DO
14
DATA_2
DO
13
DATA_1
DO
12
DATA_0
DO
ADC data output, LSB
43
SPI_DIN
DI
Serial calibration interface data in
42
SPI_LD
DI
Serial calibration interface load strobe
41
SPI_CLK
DI
Serial calibration interface bit clock
44
ADC_NBIAS
AB
Connect with 60 kW resistor to ADC_PBIAS, decouple with 100 nF to ground
45
ADC_PBIAS
AB
Connect with 60 kW resistor to ADC_NBIAS, decouple with 100 nF to
VDD_ADC_ANA
39
VLOW_ADC
AI
ADC low threshold reference voltage, connect with 90 W to GND and 130 W to
VHIGH_ADC, decouple with 100 nF to ground
40
VHIGH_ADC
AI
ADC high threshold reference voltage, connect with 130 W to VDD_ANA_ADC,
decouple with 100 nF to ground
81
REF_COMP_LOW
AO
Decouple with 100 nF to ground
80
REF_MID
AO
Decouple with 100 nF to ground
79
REF_COMP_HIGH
AO
Decouple with 100 nF to ground
29
VDD_ADC_ANA
VDD
Analog supply, 3.3 V
28
GND_ADC_ANA
GND
Analog ground
24
VDD_ADC_DIG
VDD
Digital supply, 3.3 V
26
GND_ADC_DIG
GND
Digital ground
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NOIH2SM1000A
Electrical Characteristics
Multiplexer Inputs
Table 32. MULTIPLEXER INPUTS
Pin No.
Name
Input Impedance
Settling Time
60
A_IN1
Capacitive 10 pF
100 ns
59
A_IN2
Capacitive 10 pF
100 ns
57
A_IN3
Capacitive 10 pF
100 ns
56
A_IN4
Capacitive 10 pF
100 ns
Digital I/O
D C si mulation of differ ent input buffers of HAS 2
incertain if input is seen as a high or low signal
3.50E+00
3.00E+00
Output of buffert
2.50E+00
Low signal
Low signal, but
leackage current
through buffer
2.00E+00
1.50E+00
High signal, but
leackage current
through buffer
1.00E+00
5.00E-01
High signal
0.00E+00
0.00E+00 5.00E-011.00E+00 1.50E+00 2.00E+00 2.50E+00 3.00E+00 3.50E+00
Digit al input
Figure 24. Simulation Results Digital ‘0’ and Digital ‘1’
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NOIH2SM1000A
Package Pin Assignment
The HAS sensor is packaged in an 84-pin JLCC84 package with large cavity. The following figure shows the pin
configuration.
Figure 25. Pin Configuration
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NOIH2SM1000A
USER MANUAL
Image Sensor Architecture
Figure 26. Sensor Block Diagram
Pixel Architecture
A square array contains 1024 x 1024 three-transistor
linearly-integrating pixels of each 18 x 18 mm. Each pixel
has a connection for a reset line, for power, an output select
line, and eventually the pixel’s output signal.
VDD
V DD
RESET
SELECT
SELECT
RESET
OUT
OUT
Figure 27. Three−transistor Pixel: Transistor−level Diagram (left), and Functional Equivalent (right)
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NOIH2SM1000A
photodiode by impinging photons. During this integration
the voltage on the photodiode cathode decreases.
When the select line is asserted the voltage on the
capacitor is connected to the pixel output through the source
follower buffer transistor.
All pixels in a line have their select lines tied together:
upon selection a whole line of pixel output signals is driven
onto the 1024 column buses that lead into the column
amplifiers for further processing and complete or partial
sequential readout to the ADC.
All pixels on a line have their reset lines tied together: the
reset mechanism works on all pixels in a line
simultaneously, no individual or addressed pixel reset (IPR)
is possible.
There are three transistors in a pixel. The first one acts as
a switch between the power supply and the photodiode. The
photodiode is equivalent to a capacitor with a
light-controlled current source. The second transistor is a
source follower amplifier, buffering the voltage at the
photodiode/capacitor cathode for connection to the outside
world. The third transistor again is a switch, connecting the
output of the buffer amplifier to an output signal bus.
Activating the reset line drains the charges present on the
pixel’s embedded photodiode capacitor, corresponding to a
black, dark, pre-exposure state, or high voltage. As all pixels
on a row (line) share their reset control lines, the pixels in a
row can only be reset together.
With both reset and select lines disabled the pixel amasses
photo charges on its capacitor, charges generated in the
pixel
output
level
exposure time
empty well
post-integration output level
full well
reset
exposure
readout
time
Figure 28. Signal Lifetime in a Three−transistor Pixel: Reset to Black Level (high voltage),
Photo Charge Integration (dropping voltage), Voltage Readout
Y
X
(0,0)
Figure 29. Front View of Sensor Die: Package Pin 1 is on the Left Side. The Focal Plane Origin is
in the Bottom−left Corner. Lines (Y) are Scanned Down to Top, Pixels (X) Left to Right
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NOIH2SM1000A
Line Addressing
The sensor operates line wise: a line of pixels can be
selected and reset, and a line of pixels can be selected for
readout into the column amplifier structures. There is no
frame reset operation, there is no frame transfer.
Image acquisition is done by sequencing over all lines of
interest and applying the required reset and/or readout
control to each line selected.
YRD
CLK_YRD
YRST
0
0
CLK_YRST
0
0
0
0
0
0
1
0
line selected by YRST when YRST_YR Dn=‘1’
0
SYNC_YRST
line selected by YRD when YRST_YR Dn=‘0’
0
0
SYNC_YRD
The sensor array contains two vertical shift registers for
line addressing. These registers are one-hot; they contain a
pattern such as ‘00001000000’, at each time pointing to one
line of pixels.
0
0
0
0
0
Y1
YRST_YRDb
register upload
Figure 30. Line Addressing Structures: YRD and YRST One−hot Shift Register Pointers
and Y1 Programmable Start−of−scan Register
one-hot; it contains a pattern such as ‘00001000000’, at a
time pointing to exactly one pixel and one column amplifier.
Line acquisition is done by sequencing over all pixels of
interest and applying each time the required pixel readout
and ADC control signals.
The X shift register can be initialized to a position
indicated by an on-chip address register. This address
register is written by the user through the parallel sensor
programming interface. With this programmable initial
position windowed readout (region-of-interest) is possible.
The X register can be advanced one position under user
control. This requires a pixel clock signal at twice the
frequency of the desired pixel rate.
In double sampling and destructive readout, one of these
registers is typically dedicated to addressing the lines to
read, and the other is used for addressing the lines to reset as
part of the electronic shutter operation.
In correlated double sampling and nondestructive
readout, you can choose if one or both shift registers will be
used.
Both Y shift registers can be initialized to a position
indicated by an on-chip address register. This address
register is written by the user through the parallel sensor
programming interface. With this programmable initial
position windowed readout (region-of-interest) is possible.
Both registers can be advanced one position at a time
under user control.
Column Amplifiers
At the bottom of each column of pixels sits one column
amplifier, for sampling the addressed pixel’s signal and reset
levels. These signals are then locally hold until that
particular pixel is sent to the output channel, in this case
PGA, multiplexer, buffer, and ADC.
Pixel Addressing
Pixels are read from left to right, generating a
pixel-sequential output signal for each line. The pixel
addressing is similar to the line addressing.
Close to the column amplifiers resides a horizontal shift
register for pixel/column addressing. This register is
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NOIH2SM1000A
a rising clock edge, and outputs the converted signal 6 pixel
clock periods afterwards on the falling edge.
The ADC contains its own SPI serial interface for the
optional upload of calibration settings, enhancing its
performance.
The ADC is electrically isolated from the actual sensor
core: when unused it can be left non-powered for lower
dissipation, and without risk for latch-up.
When used, the input voltage range of the ADC is set with
a two-node voltage divider connected to pins VLOW_ADC
and VHIGH_ADC.
The ADC has an accuracy of 10 bit at 5 MHz operation
speed.
The combination of column amplifiers and PGA can
perform Double Sampling: in this case a pixel’s signal level
is read into the structures, then the pixel is reset, then the
reset level is read into the structures and subtracted from the
previously-stored signal level, cancelling fixed pattern
noise.
In Correlated Double Sampling mode the column
amplifiers are used in bypass mode, and the raw signal level
(which can be either a dark reset level or a post-illumination
signal level) is sent to the output amplifier, and then to the
output for storage and correlated subtraction off-chip. This
cancels fixed pattern noise as well as temporal KTC noise.
Input Signal Multiplexer
An analog signal multiplexer with six inputs connects a
number of sources to the output buffer.
One input always is connected to the pixel-serial output of
the pixel array.
Four inputs are connected to analog input pins and are
intended for monitoring voltages in the neighborhood of the
sensor.
The last multiplexer input is connected to the on-chip
temperature sensor.
The multiplexer is controlled by an internal register,
written through the parallel sensor programming interface.
Temperature Sensor
A PN-junction type temperature sensor is integrated on
the chip. The temperature-proportional voltage at its output
can be routed to the ADC through one of the six analog
inputs of the multiplexer.
The temperature sensor must be calibrated on a
device-to-device base. Its nominal response is
–4.64 mV/°C.
Image Sensor Operation
The following section describes the HAS2 readout
mechanisms and gives the detailed timing and control
diagrams to implement these mechanisms.
Programmable Gain Amplifier (PGA)
A voltage amplifier conditions the output signal of the
multiplexer for conversion by the ADC. Signal gain and
offset can be controlled by a register written through the
parallel sensor programming interface.
When connected to the pixel array, the PGA also subtracts
pixel black level from pixel signal level when in DS/DR
mode.
Double Sampling − Destructive Readout
In double sampling or destructive readout (DS/DR) mode
the YRST pointer runs over the frame, top to bottom, each
time resetting the line it addresses. Lagging behind this runs
the YRD pointer, each time reading out the line it addresses.
The distance between the YRD pointer and the YRD pointer
is then proportional to the exposure time, hence the
electronic shutter operation.
At line readout the signal levels of the pixels in the
addressed line are copied onto the column amplifiers’ signal
sample nodes. Immediately after this the line of pixels is
reset, and the pixels’ black levels are copied onto the column
amplifiers’ reset sample nodes. This is destructive readout.
The column amplifiers/PGA then subtract the black levels
from the signal levels during sequential pixel out. This is
un-correlated double sampling, eliminating any static
pixel-to-pixel offsets of the sensor array.
Parallel Sensor Programming Interface
The sensor is controlled via a number of on-chip settings
registers for X and Y addressing, PGA gain and offset,
one-off calibration of the column amplifiers.
These registers are written by the user through a parallel
bus.
12−bit Analog to Digital Convertor (ADC)
The on-chip ADC is a 12 bit pipelined convertor. It has a
latency of 6.5 pixel clock cycles, i.e. it samples the input on
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NOIH2SM1000A
pixel
output
level
r: non−correlated reset level
empty well
pixel output = (s−r)
s: pixel signal level
full well
tEXP
time
Figure 31. Double Sampling: Pixel Signal is Read (s), then Pixel is Reset, then Reset Level is Read (r)
Correlated Double Sampling − Nondestructive Readout
In correlated double sampling or nondestructive readout
(CDS/NDR) mode the YRST or YRD pointer quickly runs
over the frame, top to bottom, resetting each line it
addresses. This leaves the pixel array drained of charges, in
black or dark state.
Then the YRD or YRST pointer is run over the region of
interest of the frame, and of each line addressed the pixels’
black levels are read out and passed on to the ADC. The user
stores these black levels in an off-chip frame-sized memory.
pixel
output
level
empty well
Then the system is held idling during the exposure time.
After the exposure time has elapsed, the frame is scanned
once more with the YRD or YRST pointer, and each line
addressed is read out again. These signal levels are passed
on to the ADC and then to the end user. At the same time, the
user retrieves the corresponding black levels from the
memory and subtracts them from the signal levels. This is
correlated double sampling, eliminating static offsets as
well as kTC noise
frame time
r: correlated reset level, store in
SRAM
s: pixel signal level, output (s−r) difference
full well
tEXP
time
Figure 32. Correlated Double Sampling: Pixel is Reset, Reset Level is Read and Stored (r),
Pixel is Exposed, Signal Level is Read (s), Difference is Output
In Nondestructive readout/correlated double sampling it
is not even possible to pinpoint a typical case, as all depends
on the exact reset (R), reset-read (r) and signal-read (s)
scheme the user employs. In the specific case of 10 MHz
pixel rate rate operation, 10 windowed frames per second,
and 40 windows of 20 x 20, each receiving the same
exposure time, and the whole FPA reset (R) at the start of the
frame, the minimal exposure time is 7.3 ms, the maximal
exposure time 90.2 ms. Depending on window
configuration, shorter and longer times are possible, though.
Possible Exposure Times
The range of exposure times attainable by the HAS is
entirely dependent on the user control strategy, although two
obvious scenarios can be envisaged:
In destructive readout/double sampling, a typical case is
a minimal exposure time equal to the line readout time, and
a maximal exposure time equal to the frame time. With
1024 x 1024 pixels in a frame, 10 frames per second, this
amounts to 98 ms and 100 ms.
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NOIH2SM1000A
Timing and Control Sequences
Definitions
The HAS is a line-scan imager with 1024 horizontal lines
(Y) each of 1024 pixels (X). Pixel coordinates are defined
relative to an origin (X=0,Y=0), and projected onto the
user’s display view: the origin (0,0) is in the top-left corner
of the displayed image, lines are scanned top-down, and the
pixels in a line are scanned left to right.
Windows or regions-of-interest are defined by their
top-left and bottom-right coordinates (X1,Y1)-(X2,Y2).
The full frame then corresponds to (0,0)-(1023,1023). Note
that (X1,Y1) is to be programmed into the sensor, while
(X2,Y2) is not: windowed readout is obtained by pointing
the sensor to (X1,Y1), followed by reading out (Y2-Y1+1)
lines of (X2-X1+1) pixels.
A frame readout sequence consists of a number of line
readout sequences.
A line readout sequence consists of
• A line select sequence for the YRD and YRST pointer
shift registers, during which a line may be selected for
readout and another line may be selected for reset
• A line blanking sequence during which the line selected
•
for readout copies its pixel signals into the column
amplifiers, the column amplifiers are operated, and
both lines selected are optionally reset (the line selected
for read can be reset as part of the destructive
readout/double sampling operation; the other line can
be reset as part of the electronic shutter operation).
A pixel readout sequence
A pixel readout sequence consists of
• Initialization of the pixel pointer XRD to position X1
• A sequencing through the region-of-interest,
• While the output amplifier and the ADC are activated
and pixel values are sequentially selected, connected to
the PGA, and converted by the ADC.
t5
BLANK
t1
t2
t3
t4
CLK_Y*
SYNC_Y*
XXX
Y*
Y1
Y1+1
Y1+2
Y1+3
Y1+4
Figure 33. Line Selection Timing Diagram
This timing diagram is valid for CLK_YRD/SYNC_YRD and for CLK_YRST/SYNC_YRST.
Description
Min
Typ
t1
SYNC_Y* setup
50 ns
t2
CLK_Y* high width
100 ns
t3
CLK_Y* period
200 ns
t4
Address delay
t5
Setup to next blanking
Max
Remarks
No constraint on duty cycle
30 ns
100 ns
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NOIH2SM1000A
Destructive Readout Timing Diagram
In this mode the unit of timing is conveniently chosen to
equal the time needed to read out a line of pixels. Hence, the
exposure time tEXP can be expressed as an equivalent
number of lines.
Table 33. THREADS OF OPERATION FOR DESTRUCTIVE READOUT WITH DOUBLE SAMPLING
Comment
init
YRD - Read Side
YRST - Reset Side
Load registers Y1 and X1 with the window start coordinates
Initialize YRD with Y1
expose
read
Initialize YRST with Y1
For YRST = Y1 to Y1+tEXP loop
.select line YRST
.reset line YRST
.wait for one line time
.advance YRST one position
end loop
.do nothing
For YRD = Y1 to Y2 loop
.select line YRD
.operate column amplifiers for DS/DR
.read pixels X1 to X2
.advance YRD
end loop
.select line YRST
.reset line YRST
.advance YRST
Figure 34. DS/DR Sequence: Exposure is Initiated with Running YRST over the Array, Resetting Lines.
After tEXP YRD starts running over the array too, reading and then resetting lines
t15
BLANK
t2
t3
t2
t3
PRECHARGE
t4
t6
t8
t4
t11
SEL
t7
t13
t7
RESET
t12
t13
t14
YRST_YRDn
t1
t5
S
t9
t10
R
t16
t16
CAL
Double Sampling of line indicated by YRD
Optional reset of YRST
for electronic shutter
Figure 35. Destructive Readout Timing Diagram
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Pixel readout
NOIH2SM1000A
Description
Min
Typ
t1
BLANK setup
13 ns
25 ns
t2
S setup
10 ns
25 ns
t3
PRECHARGE width
400 ns
t4
30 ns
t5
S active when SEL
t6
RESET width
2 ms
25 ns
400 ns
t8
100 ns
t9
100 ns
t10
Remarks
50 ns
11 ns
t7
Max
R active when SEL
t11
2 ms
10 ns
25 ns
t12
YRST_YRDn setup
100 ns
Second RESET is optional
t13
YRST_YRDn hold
100 ns
t14
BLANK hold
22 ns
t15
BLANK hold
100 ns
When no second RESET
t16
CAL delay ref. BLANK
25 ns
Once per frame or per line
25 ns
The CAL signal initiates the programmable gain amplifier to a known ‘black’ state. This initialization should be done at the
start of each frame.
Nondestructive Readout Timing Diagram
In describing this mode, the unit of timing is conveniently
chosen to equal the time needed to read out a line of pixels.
Hence, the exposure time tEXP can be expressed as an
equivalent number of lines. (Note that the user is under no
obligation to link tEXP to the line read time: tEXP can be
chosen arbitrarily as its timing and nature are only
dependent on the external system controlling the HAS).
Table 34. THREADS OF OPERATION FOR NONDESTRUCTIVE READOUT WITH OFF−CHIP CDS
Comment
init
YRD - read side
YRST - reset side
Load registers Y1 and X1 with the window start coordinates
initialize YRD with Y1
clear frame
Initialize YRST with Y1
for YRST = 1 to 1023 loop
.select line YRST
.reset line YRST
.advance YRST one position
end loop
.do nothing
read black levels
for YRD = Y1 to Y2 loop
.select line YRD
.operate column amplifiers for CDS/NDR, black levels
.read pixels X1 to X2
.advance YRD
end loop
exposure
wait for time tEXP
read signal levels
for YRD = Y1 to Y2 loop
.select line YRD
.operate column amplifiers for CDS/NDR, signal levels
.read pixels X1 to X2
.advance YRD
end loop
Proper operation can be attained by using just one Y
pointer register, YRD or YRST, for all of the frame’s phases.
The above operation scheme is just an example, using YRST
for the frame reset phase.
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NOIH2SM1000A
Figure 36. CDS/NDR Sequence: First Array is Reset Completely with YRST. Then Black Levels are Read with YRD.
Then, after a Time tEXP, All Signal Levels are Read, again with YRD.
t 11
BLANK
t5
t6
PRECHARGE
t7
t10
SEL
t2
t3
RESET
t1
t2
t1
YRST_YRDn
t4
t8
S
t9
R
t12
t 12
CAL
Reset of line YRD
Readout of line YRD black or signal levels
Pixel readout
Figure 37. Non−destructive Readout Timing Diagram
Description
Min
Typ
25 ns
t1
BLANK setup
13 ns
t2
YRST_YRDn s/h
100 ns
t3
RESET width
400 ns
t4
BLANK setup
13 ns
25 ns
t5
S/R setup
10 ns
25 ns
t6
PRECHARGE width
400 ns
t7
t8
30 ns
S/R active when SEL
t9
Max
Remarks
Optional, only when YRST is used instead of YRD
50 ns
2.4 ms
11 ns
25 ns
11 ns
25 ns
t10
SEL hold
t11
BLANK hold
100 ns
t12
CAL delay ref. BLANK
25 ns
once per frame or per line/window
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NOIH2SM1000A
t4
t1
CAL
CLK_X
SYNC_X
XRD
XXX
X1
X1+1
X1+2
X1+3
X1+4
X1
X1+1
output signal
t2
X1+2
t3
CLK_ADC
Figure 38. Pixel Readout Timing Diagram
The externally applied clock CLK_X runs at twice the
pixel rate. From address pointer XRD shift to output signal
available exists a latency of 6 CLK_X cycles. The above
Description
t1
CLK_X period
t2
output settle time
t3
output hold time
t4
CAL off setup
Min
Typ
50 ns
100 ns
timing diagram supposes an ADC sampling at the rising
edge of CLK_ADC.
Max
Remarks
50% duty cycle required, ±2.5 ns
15 ns
2 ns
50 ns
BLANK off setup when no CAL
PGA and Signal Multiplexer Control
temp
CAL
SIGNAL_OUT
pixels
PGA
mux
buffer
A_IN1
A_IN2
A_IN3
A_IN4
AMP.Offset[5..0]
MODE.PGA[2..0]
AMP.Gain[1..0]
Figure 39. Programmable Gain Amplifier and Signal Multiplexer Diagram
t2
CLK_X
t1
CAL
Figure 40. Amplifier Calibration Timing Diagram
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NOIH2SM1000A
of the gain settings, the PGA have to be calibrated to set the
correct offset on the PGA. It is suggested to make this CAL
signal equal to the BLANK signal.
NOTE: The BLANK signal resets the X shift register.
So after each active BLANK period, there has to
be a SYNCING of the x shift register before
reading out any pixel.
For gain and offset control, see section “Sensor
Programming” on page 51.
The column amplifier output is a stream of raw or
FPN-corrected pixels. These pixels then pass the
programmable gain amplifier, where gain and DC-offset can
be adjusted. Then follows a signal multiplexer that selects
between the pixel signal or the temperature sensor and four
externally-accessible analog inputs. The output of the
multiplexer is buffered and then made available at output
pad SIGNAL_OUT.
The PGA must be calibrated periodically with a black
reference input signal, triggered by CAL. After each change
Description
Min
t1
CAL width
200 ns
t2
CAL-to-pixel-readout
50 ns
Typ
Multiplexer Operation
MODE.PGA[2..0]
Selected Input
000
pixel array
001
TEMP
010
-
011
-
100
AIN1
101
AIN2
110
AIN3
111
AIN4
Max
Remarks
• When pixel 56 comes out, stop the x clock after the
falling edge.
• The output stays at the same level of this pixel (see
•
•
•
•
•
Changing gain during read out
It is possible to change the gain settings during the read out
of one line. The following procedure is suggested. For
example, gain changing between pixel 56 and 57.
Figure 38 on page 49)
Change the gain settings by setting the internal registers
as described in Sensor Programming on page 51
Assert the CAL signal for 200 ns but leave the BLANK
signal inactive
After the CAL signal has felled down, wait 50 ns.
Reactivate the X clock starting with the rising edge
The first pixel that comes out is pixel 57
The total time needed to change the gain settings is about
450 ns.
Hard Reset − Soft Reset − Hard−to−Soft Reset
See Reset Modes Timing Controls on page 56.
t1
t2
analogue in
t3
CLK_ADC
XXX
DATA[11..0]
1
t4
2
3
t5
Figure 41. ADC Timing Diagram
The ADC is a pipelined device that samples on each rising
edge of its clock CLK_ADC. The output DATA is updated
Description
Min
on each falling edge of CLK_ADC. There is an
input-to-output latency of 6.5 clock cycles.
Typ
t1
input setup
5 ns
t2
input hold
20 ns
t3
sample clock
100 ns
t4
Latency
6.5 t3
t5
output delay
10 ns
Max
Remarks
50% duty cycle required, ±5%
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NOIH2SM1000A
Sensor Programming
Parallel Sensor Programming Interface
The operational modes and start-of-window addresses of
the HAS are kept in seven on-chip registers. These internal
registers are programmable through a parallel interface
similar to the one on the STAR250.
This interface comprises of a 10-bit wide A bus, and 3 load
strobes: LD_X, LD_Y, and LD_REG.
With LD_Y or LD_X asserted (rising edge), the full 10
bits of A are loaded into respectively the line start address
(Y1) and the column start address (X1) (as similar to the
STAR250).
With a rising edge on LD_REG, the upper two bits of A
are decoded as an internal register address, and the 8 lower
bits of A are loaded into the corresponding register. These 4
registers are reset to their default values by asserting
RES_REGn.
Address Register Load Timing Diagram
t1
t4
A
X1/Y1
t2
LD_X/LD_Y
t3
X1/Y1
XXX
X1/Y1
Figure 42. Line / Column Address Upload Timing Diagram
The YRD/YRST and XRD pointer start address registers
Y1 and X1 are latches that pass the input value when
Description
Min
t1
A setup
100 ns
t2
LD_* width
100 ns
t3
delay
75 ns
t4
A hold
100 ns
LD_Y/LD_X is asserted, and freeze their output values
when LD_Y/LD_X is deasserted.
Typ
Max
t1
Remarks
t4
value
A
t2
LD_REG
t3
value
XXX
register
Figure 43. Mode Registers Upload Timing Diagram
The mode setting registers are edge-triggered flip flops
that freeze their outputs at the rising edge of LD_REG.
Description
Min
t1
A setup
100 ns
t2
LD_REG width
100 ns
t3
delay
75 ns
t4
A hold
100 ns
Typ
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Max
Remarks
NOIH2SM1000A
Internal Registers Global Description
Are registers are programmed using the parallel upload
interface. Two styles of register access methods are used.
Address registers loaded with LD_Y or LD_X:
Register Name
Value A[9..0]
Default
Description
Y1
9:0
0
start position of the YRD and YRST one-hot addressing shift registers, range
0..1023
X1
9:0
0
start position of the XRD one-hot pixel address register, range 0..1023
Mode registers loaded with LD_REG and reset to default with RES_REGn:
Register Name
Address A[9..8]
Value A[7..0]
Default
MODE
00
6:5
0
End of scan multiplexer
4:2
0
PGA input multiplexer
1
0
1 = nondestructive readout
0 = destructive readout, dual sampling
0
0
1 = standby
0 = APS in active mode
7:2
0
Amplifier raw offset
1:0
0
Amplifier gain.
AMP
01
Description
BLACK
10
7:0
0
NDR mode black level
OFFSET
11
7:0
0
DR mode column bus offset correction
Internal Registers Detailed Description
X1 Register:
X1
strobe: LD_X
A[9..0] = X1[9..0]
X1[9..0]
start coordinate of XRD shift register for pixel scan
Y1 Register:
Y1
strobe :LD_Y
A[9..0] = Y1[9..0]
Y1[9..0]
start coordinate of YRD and YRST shift registers for line scan
Legal (decimal) values are 0 (first line of the array) to 1023 (last line of the array)
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MODE Register:
MODE
A[9..8] = “00”
LD_REG
A[7..0] = “X”&EOS[2..0]&PGA[2..0]&NDR&StandBy
EOS[1..0]
End-Of-Scan indicator selector
00
output of YRD shift pointer register to pin EOS
01
output of YRST shift pointer register to pin EOS
10
output of XRD shift pointer register to pin EOS
11
output of XRD shift pointer register to pin EOS
PGA[2..0]
PGA input multiplexer
000
pixel array
001
TEMP temperature sensor
010
-
011
-
100
AIN1 analog telesense input
101
AIN2
110
AIN3
111
AIN4
NDR
Non-destructive Readout selector
0
NDR off, DS/DR enabled
1
NDR on, CDS/NDR enabled
StandBy
power switch
0
sensor operational
1
sensor in standby / low power
NDR selects DR or NDR mode.
Standby puts the sensor in a low-power mode, in which
the current mirror bias network drivers of the column
structures, PGA, output buffer, and internal offset DACs are
disabled.
EOS[1..0] connects the output of the last stage of either
one of the internal array = addressing shift register pointers
YRD, YRST or XRD to the outside world at pin EOS.
PGA[2..0] selects one of 6 possible analog signals to be
connected to the analog output pin.
AMP
A[9..8] = “01”
LD_REG
A[7..0] = Offset[5..0]&Gain[1..0]
Offset[5..0]
PGA offset
Gain[1..0]
PGA gain
00
1
01
2
10
4
11
8
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NOIH2SM1000A
The reset value of AMP.Offset is 0, decoding to the middle
offset value of 0.8 V. AMP.Offset range 0 to 31 corresponds
to levels of 0.8 to 1.3 V, while AMP.Offset range 32 to 63
corresponds to levels of 0.3 to 0.8 V.
Gain is controlled in 4 steps for nominal values of 1,2,4,
and 8. Real gain values are expected to be somewhat lower
and will be characterized.
This register sets the PGA output offset and gain. The
PGA output signal offset is controlled in 64 steps of 16 mV
each, from 0.3 V to 1.3 V. Output offset control is used to
adapt the PGAs output to the ADC used (internal or external
ADC). See Other Definitions on page 13.
For unity gain and internal ADC use, the recommended
default setting is:
AMP_OFFSET = 60
BLACK Register:
BLACK
A[9..8] = “10”
LD_REG
A[7..0] = BLACK[7..0]
BLACK[7..0]
NDR mode black level
The BLACK register sets the black level of the column
amplifier structures and column pre-chargers when used in
NDR mode.
The reset value of BLACK is 0, setting the internal black
level to half-way full scale: BLACK range 0..127
corresponds to 1.65 V to 2.9 V in steps of 10 mV. BLACK
range 128 to 255 corresponds to 0.4 V to 1.65 V in steps of
10 mV.
The recommended default setting is: BLACK = 10
OFFSET Register:
OFFSET
A[9..8] = “11”
LD_REG
A[7..0] = OFFSET[7..0]
OFFSET[7..0]
Column bus offset correction.
The column signal path and later parts of the signal path
is split in an odd bus with amplifiers and an even bus with
amplifiers.
Using the OFFSET register, the offsets for these two
signal paths can be calibrated to obtain a balanced
performance.
The reset value of OFFSET is 0, driving the offset
generator to half-scale (0 mV). OFFSET range 0 to 127
corresponds to 0 to +17.5 mV in steps of 140 mV. OFFSET
range 128 to 255 corresponds to –17.5 mV to 0 mV in steps
of 137 mV.
Expressed in electrons, this gives the following numbers:
Total offset correction range: 2365 electrons
Step of correction: 9.3 electrons
The recommended default setting is:
OFFSET = 0 (sample depended).
It’s recommended to calibrate the device while taking a
dark image.
Sensor Calibration
NDR Mode Black Level
BLACK=10.
ADC Corrections
Concept
The ADC is a pipelined device with 11 identical
conversion stages in series. Each conversion stage is built
around an amplifier with gain that can be calibrated. Each
amplifier’s gain can be tuned individually with an 8 bit code,
totaling 11 words of 8 bits to be loaded into the ADC through
a separate serial interface.
Column Amplifier Offset Correction
The column amplifier structures comprise of two
independent signal buses, one handling pixels from odd
columns, one handling pixels from even columns.
As these structures are inherently imperfectly matched in
offset, user calibration of this parameter is required when the
sensor is operated in destructive readout / double sampling
mode.
The default (reset) values for this parameter puts the
internal calibration signal generators in their neutral,
middle-value mode.
ADC Tuning Codes
Tuning codes each span the range 0 to 255, with value 127
denoting the amplifier’s central gain setting (default after
power-on, i.e. without user calibration, and allowing
nominal operation of the device). Code 0 reduces the gain
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NOIH2SM1000A
ADC Linearity Tuning Method
The ideal calibration code is 75 for each stage.
It is expected that a complete set of calibration values will
be provided in the sensor data sheet, or when necessary, with
each device individually.
with 5%, tuning code 255 increases gain with 5%. The
code-gain relation is guaranteed monotonous.
t1
t2
SPI_CLK
XXX
SPI_DATA
N
N‐ 1
1
XXX
t3
SPI_LD
Figure 44. ADC Serial Interface
Description
Min
t1
SPI_CLK width
1000 ns
t2
SPI_LD setup
0 ns
t3
SPI_LD width
1000 ns
Typ
All 11 8-bit correction words are uploaded in one burst of
88 bits. The word for stage 11 first, then stage 10, and so
down to stage 1. Within each word the MSB comes first. Bits
are sampled on the rising edge of SPI_CLK, and thus should
change on the falling edge of SPI_CLK. The complete set of
words is registered in the ADC on the rising edge of SPI_LD.
Max
Remarks
Temperature Sensor
An internal temperature sensor presents a
temperature-dependent voltage which can be made
available at pin SIGNAL_OUT through the multiplexer.
The voltage-temperature dependency is approximately
–4.64 mV/°C, but the absolute level is to be characterized on
a device-by-device basis for demanding applications.
With the on-chip ADC biased for an input window of 0.7
to 1.9 V, the temperature sensor/ADC combination can be
used from –40 to +125°C.
Sensor Biasing
The operating points of the sensor and ADCs analog
circuitry are set with external passive components (resistors
and capacitors). These components have their
recommended values listed in Detailed Information on
page 3.
ADC Input Range Setting
The input voltage range of the ADC (pin ADC_IN) is to
be matched to the signal at hand, in this case the output
voltage range at pin SIGNAL_OUT.
The lower threshold is set to the voltage injected at pin
VLOW_ADC. The upper threshold is set to the voltage
injected at pin VHIGH_ADC. For both settings it is
recommended to use a resistive voltage divider: 90 W from
GND_ADC_ANA to VLOW_ADC, 130 W from
VLOW_ADC to VHIGH_ADC, 130 W from VHIGH_ADC
to VDD_ADC_ANA.
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NOIH2SM1000A
Reset Modes Timing Controls
4.2 V
400 ns
Reset
0 V
3.3 V
VDD_PIX
0V
Figure 45. Hard Reset
3.3 V
Reset
400 ns
0 V
3.3 V
VDD_PIX
0 V
Figure 46. Soft Reset
3.3 V
400 ns
Reset
0 V
400 ns
VDD_PIX
3.3 V
0.75 V
Figure 47. Hard to Soft Reset
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NOIH2SM1000A
Application and Test Circuits
Figure 48. Sensor Pinning
All ground pins may be connected to 1 point except the
anti blooming ground (GNDAB).
The reference voltages can be either injected by a power
supply voltage or can be generated from a resistance divider.
See ADC Input Range Setting on page 55.
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NOIH2SM1000A
Figure 49. Sensor Biasing Circuits
Figure 50. Sensor Power Supply Decoupling Circuits
Figure 51. Reference Voltage End Circuits
Figure 52. Sensor ADC Circuitry
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NOIH2SM1000A
ACRONYMS
For the purpose of this specification, the terms,
definitions, abbreviations, symbols, and units specified in
ESCC Basic Specification 21300 apply. In addition, the
following table contains terms that are specific to CMOS
image sensors and are not listed in ESCC21300
Abbreviation
Description
ADC
analog to digital convertor
APS
active pixel sensor
CDS
correlated double sampling
DNL
differential nonlinearity
DR
destructive readout
DSNU
dark signal non-uniformity
EPPL
European preferred parts list
ESD
electro-static discharge
FPN
fixed pattern noise
HAS
high accuracy star tracker
INL
integral nonlinearity
MTF
modulated transfer function
NDR
nondestructive readout
PRNU
pixel response non-uniformity
TBC
to be confirmed
TBD
to be defined
RGA
residual gas analysis
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NOIH2SM1000A
GLOSSARY
conversion gain
A constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel.
Conversion gain = q/C where q is the charge of an electron (1.602E 19 Coulomb) and C is the capacitance
of the photodiode or sense node.
CDS
Correlated double sampling. This is a method for sampling a pixel where the pixel voltage after reset is
sampled and subtracted from the voltage after exposure to light.
CFA
Color filter array. The materials deposited on top of pixels that selectively transmit color.
DNL
Differential nonlinearity (for ADCs)
DSNU
Dark signal non-uniformity. This parameter characterizes the degree of non-uniformity in dark leakage
currents, which can be a major source of fixed pattern noise.
fill-factor
A parameter that characterizes the optically active percentage of a pixel. In theory, it is the ratio of the
actual QE of a pixel divided by the QE of a photodiode of equal area. In practice, it is never measured.
INL
Integral nonlinearity (for ADCs)
IR
Infrared. IR light has wavelengths in the approximate range 750 nm to 1 mm.
Lux
Photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m2 = 1/683 W/m2)
pixel noise
Variation of pixel signals within a region of interest (ROI). The ROI typically is a rectangular portion of the
pixel array and may be limited to a single color plane.
photometric units
Units for light measurement that take into account human physiology.
PLS
Parasitic light sensitivity. Parasitic discharge of sampled information in pixels that have storage nodes.
PRNU
Photo-response non-uniformity. This parameter characterizes the spread in response of pixels, which is a
source of FPN under illumination.
QE
Quantum efficiency. This parameter characterizes the effectiveness of a pixel in capturing photons and
converting them into electrons. It is photon wavelength and pixel color dependent.
read noise
Noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode
into an output signal.
reset
The process by which a pixel photodiode or sense node is cleared of electrons. ”Soft” reset occurs when
the reset transistor is operated below the threshold. ”Hard” reset occurs when the reset transistor is operated above threshold.
reset noise
Noise due to variation in the reset level of a pixel. In 3T pixel designs, this noise has a component (in units
of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). In 4T pixel
designs, reset noise can be removed with CDS.
responsivity
The standard measure of photodiode performance (regardless of whether it is in an imager or not). Units
are typically A/W and are dependent on the incident light wavelength. Note that responsivity and sensitivity
are used interchangeably in image sensor characterization literature so it is best to check the units.
ROI
Region of interest. The area within a pixel array chosen to characterize noise, signal, crosstalk, and so on.
The ROI can be the entire array or a small subsection; it can be confined to a single color plane.
sense node
In 4T pixel designs, a capacitor used to convert charge into voltage. In 3T pixel designs it is the photodiode itself.
sensitivity
A measure of pixel performance that characterizes the rise of the photodiode or sense node signal in Volts
upon illumination with light. Units are typically V/(W/m2)/sec and are dependent on the incident light wavelength. Sensitivity measurements are often taken with 550 nm incident light. At this wavelength, 1 683 lux
is equal to 1 W/m2; the units of sensitivity are quoted in V/lux/sec. Note that responsivity and sensitivity are
used interchangeably in image sensor characterization literature so it is best to check the units.
spectral response
The photon wavelength dependence of sensitivity or responsivity.
SNR
Signal-to-noise ratio. This number characterizes the ratio of the fundamental signal to the noise spectrum
up to half the Nyquist frequency.
temporal noise
Noise that varies from frame to frame. In a video stream, temporal noise is visible as twinkling pixels.
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NOIH2SM1000A
FREQUENTLY ASKED QUESTIONS
Question:
In the HAS2 data sheet, the pixel readout timing diagram
lacks information. It appears SYNC_X should change on the
rising edge of CLK_X. While SYNC_X is high, a rising
edge of CLK_X should sync XRD to X1 register. But the
diagram shows SYNC_X high for two CLK_X periods. Due
to timing variations, SYNC_X can be high for as many as
three different rising edges of CLK_X! The timing diagram
does not show any setup or hold timing for SYNC_X and
CLK_X.
Answer:
SPI_CLK has a period of 1000 ns, so the SPI_DATA is
present for 500 ns prior to the rising edge of SPI_CLK. But
what is the SPI_DATA setup time for the *first* rising edge
of SPI_CLK (first bit of data)?
Answer:
The best way to operate the device is to change your SPI
data during the falling edge of the SPI clock. This gives you
plenty of time before the data is being sampled on the rising
edge of the SPI clock.
Consider a 100 ns hold and setup time of the SPI data
around the rising edge of the SPI clock. For the first rising
edge, consider a 500 ns setup time for the SPI data.
Question:
I noticed that BLANK remains high for the destructive
readout timing diagram even during the reset of YRST row.
However, in the nondestructive readout timing diagram,
BLANK is shown going low between a reset and line
selection, with no timing information.
What should the timing be? Or should it be left BLANK
constantly high during a line reset and subsequent line
selection during nondestructive readout?
Answer:
For the nondestructive read out, extend T1 and reduce T4.
This means that you can leave the BLANK signal high.
CLK_X is divided internally in the sensor. SYNC_X is
based upon this divided clock. When SYNC_X is high for
an even pair of this divided clock cycles, the XRD is pushed
the length of this even pair of clock cycles. Though, when
SYNC_X drops during an uneven pair of divided clock
cycles, it is unclear what XRD will do. But this behavior is
most unlikely.
Question:
RES_REGn does not have any timing information. It is
the asynchronous reset for internal registers. How long must
it be held low?
Answer:
To be on the safe side, keep it low for at least 1 s. You
can apply the following sequence when powering up the
sensor:
• Power on device with known register settings
• During power on, keep RES_REGn low for at least 1 ms
• Apply line/column address upload timing diagram
Question:
The ADC serial interface timing diagram is incomplete. It
appears the SPI_DATA is supposed to change on the falling
edge of SPI_CLK. If so, then what is the setup and hold times
of the SPI_DATA around the rising edge of SPI_CLK? The
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NOIH2SM1000A
t11
BLANK
t5
t6
PRECHARGE
t7
SEL
t2
t10
t3
RESET
t1
t2
t1
YRST_YRDn
t4
t8
S
t9
R
t12
t12
CAL
Reset of line YRD
Readout of line YRD black or signal levels
Question:
What is your recommendation to do with the unused
analog inputs to the multiplexor (A_IN1-4)? Grounding
them will place them at 0 volts, which is outside the
VLOW_ADC range. Should they be left floating? Or should
they be tied to some constant voltage source between
VHIGH_ADC and VLOW_ADC?
Answer:
If you do not use the analog inputs, then ground them. But
most customers use these inputs to monitor some supply
voltages. For example, monitor your 3.3 V input voltage.
Divide it with a resistance divider to have the voltage inside
the ADC range. You can also use it to monitor some external
voltages that are used on your board and which are important
to be stable.
Question:
What are the implications of turning off the analog power
supplies (VDDA), but keeping the digital power supply
(VDD) active? I am trying to improve the standby low power
mode.
Answer:
No this is not bad. In fact, the total power supply current
will reduce a little more.
Question:
Specification sheet describes the ADC input range
setting: 90 W from GND_ADC_ANA to VLOW_ADC,
130 W from VLOW_ADC to VHIGH_ADC, 130 W from
VHIGH_ADC
to
VDD_ADC_ANA.
The
VDD_ADC_ANA is 3.3 V so this puts VLOW_ADC = 0.85
V and VHIGH_ADC = 2.07 V. Table 28 on page 23 specifies
ADC_VLOW = 0.8 V and ADC_VHIGH = 2.5 V. Which
way do you recommend? Can you describe the discrepancy?
Answer:
The correct ADC range is with the resistance divider. An
alternative without resistance divider is to directly inject this
voltage by a power supply circuitry. This is how it is done in
our characterization system. This way, you can tune ADC
Pixel readout
settings as required. However, to retain the resistances, use
the values described above.
Table 28 on page 23 is a typo. It should be 0.85 V and
2.0 V.
Question:
In the data sheet, ADC High/Low bias voltages are
recommended to be set with a resistive divider. But the data
sheet does not mention anything about temperature stability.
For the STAR-1000, there is an internal resistor between
ADC_HIGH and ADC_LOW that had temperature
dependence. Because of this, for STAR-1000 designs, I set
my ADC bias voltages with buffers that keep the bias levels
constant over temperature. Do I need to repeat the same
principle for the HAS2? Or does the HAS2 remove any
temperature dependence for the ADC bias voltages?
Answer:
For good temperature stability, it is better to use the same
principle as the STAR-1000. So use external buffers to keep
ADC_HIGH and ADC_LOW to a fixed voltage level.
Question:
For Figure 41 on page 50 , the table lists t5, output delay,
as typically 10 ns. The STAR-1000 had a troublesome
output delay variability of 20 ns to 60 ns, some parts even
had 70 ns! Have the digital output drivers been significantly
improved for the HAS2 ADC? What are typical rise/fall
times for the outputs?
Answer:
The output delay and stability has been improved
compared to STAR-1000.
Question:
What are the differences between BLANK, CAL, and
PRECHARGE? The STAR-1000 only had a CAL signal.
Answer:
The extra BLANK signal is used to reset the internal
CLKX divider. PRECHARGE is used to pre-charge the
column lines and column caps to ground
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• What is the role of the anti-blooming ground pin
Question:
The HAS2 appears more restrictive compared to the
flexibility of STAR-1000. For example, the application note
says, “repeated use of pixel re-addressing (register X1)
potentially injects offset-noise into any windows that
overlap in Y-coordinates.” Does this mean I cannot address
each pixel along a line individually? I cannot read out every
other pixel, or every second, fifth, or tenth and all pixels
must be read out in a line. Are there any options?
Answer:
You can start reading at any X or Y position. Remember
that there is an analog pipeline on the pixel data. When
reading two pixels of the same line closer than the analog
pipe, the second pixel is addressed only after the first pixel.
Therefore, the second pixel is read by a new SyncX, when
yo address it the second time.
As a result, there is a risk of a deviated value. Probably
some deviated offset on the pixel value.
Question:
For NDR/CDS mode, there is parasitic exposure in the
suggested algorithm. Can I do this algorithm instead?
1. Reset Row X
2. Start integration timer
3. Readout Row X
4. Reset Row X+1
5. Readout Row X+1
6. Reset Row X+2
7. Readout Row X+2
8. (repeat to region of interest)
9. (wait for integration timer completion)
10. Readout Row X
11. (wait for time to reset a row)
12. Readout Row X+1
13. (wait for time to reset a row)
14. Readout Row X+2
15. (wait for time to reset a row)
16. (repeat to region of interest)
Answer:
This algorithm can be used.
Question:
Our target application requires that we operate with the
sun in our field of view. From initial calculations, this means
that we can have a sun spot on the sensor around 50 pixels
in diameter, over-exposed by a factor of ~1000 against other
target spots.
•
•
(GND_AB) and how does it impact the sensor
behavior?
Is the anti-blooming capability sufficient to prevent any
additional “recovery” time of the sensor?
What pixel to pixel crosstalk behavior can be expected
around the sun spot? 9.8% of the full well (Table 27 on
page 23)?
Answer:
When a pixel is saturated and even goes to negative
voltage levels, it is not suitable for lower electro potential
level to attract new photon-electrons. So the extra
photo-electrons can now go to nearby pixels more easily
than to the pixel where the electrons are generated. This is
visible in the image as blooming. The anti-blooming method
involves keeping the photo-diode at an attractive
electro-potential that still attract new electrons. This is done
by holding the gate of the reset transistor higher then ground
level.
The ‘row_select’ line that selects a specific row of the
pixel array is a digital signal that swaps between
‘GND_DIG’ and ‘VDD_DIG’. The ‘row_reset’ line that
resets a specific row of pixels uses the same drivers as the
‘row_select’ line but the lower voltage level is not
‘GND_DIG’ but ‘GND_AB’. So the lower level of gate of
the pixel reset transistor can be set by adapting the voltage
level of ‘GND_AB’.
It is recommended not to go higher than 1 V with the
voltage level of ‘GND_AB’ than 1 V. The digital circuits of
the sensor should still see it as a digital ‘0’. Some second
order effect of keeping GND_AB higher than ground:
• The swing of row_reset is now lower. This means less
cross-talk to the photo-diode and higher dark-level.
Probably you don’t see much changes if you read the
sensor in dual sampling. Both the signal and the dark
reference changes in level, so the subtraction is still the
same. But you use the photo-diode on a slightly higher
voltage level. Therefore, the pixel cap can be a little
lower. (nonlinear behavior of the cap of a diode).
• The swing of the diode is also lowered, but probably
only the part of the swing that was not read-out anyway.
It is very difficult to get any quantification of the
anti-blooming effect. The best way of figuring is just trying
it. The anti-blooming function is not part of the
characterization of the sensor.
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Question:
I am trying to estimate the pulse height distribution (PHD)
from electrons and protons traversing the focal plane array.
The PHD is the probability of seeing a pulse of a given size
in a single pixel from an electron or proton coming from a
random direction and striking in a random location. When
an electron traverses a unit cell it excites electrons. The total
amount of charge is proportional to the length of the path (the
chord length) through the unit cell. Charge that is created
outside the collection region of the detector has little effect.
The charge in the photodiode is collected and looks similar
to a signal. To calculate the chord length distribution through
the photodiode I need its dimensions. I have been assuming
that it is 7.5 microns on a side, living within the 15 micron
unit cell. What is the thickness of the collection region. It can
be quite thick, but I have been assuming a fairly thin
geometry. The production of streaks by protons is sensitive
to the thickness of the photodiode as well (thicker means
longer streaks). So I think the answer to your question is that
I need all three dimensions of the photodiodes in the array.
Are the unit cells repeated across the array or are they
arranged with mirror images next to each other, which
makes the light sensitive regions cluster in groups of two or
four.
Answer:
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Question:
What is the penetration depth of photons in the HAS2
pixel versus the spectral range? Doe we have such graphs
available?
Answer:
This is theory. We have penetration versus spectral range
but this depends on the actual doping levels of the substrate.
So it is never actual measured.
Question:
How does the MTF behave with increasing wavelength?
Is there an MTF graph available versus spectral range?
Answer:
You can expect a large decrease in MTF when using
higher wavelengths. To known how it behaves on the HAS2,
new MTF measurements are needed.
Question:
In chapter 6.2 of the actual data sheet it is suggested to use
one regulator for all digital supply pins together, one
regulator for the sensor core analog supplies together, and
one regulator for the ADC analog supply. Against it the test
circuit in chapter 7.3 uses 5 different supply voltages
(VDDD, VDDA, VPIX, VadcA, VadcD).
With the first information I decided to use 3 regulators:
One for VDD_ANA + VDD_PIX, one for VDD_DIG +
VDD_ADC_DIG and one only for VDD_ADC_ANA.
Moreover I use two grounds (analog and digital). Sadly with
this configuration I have some problems in Window-Mode.
Every 2nd line of the first lines of a window overshoot there.
The more lines are sampled the lower is that effect. After
may be 20 to 30 lines the effect exists no longer. In an other
PCB I use a separate regulator for VDD_PIX instead for
VDD_ADC_ANA (VDD_ADC_ANA is connected to
VDD_ANA) and everything works fine. Is that the
problem?
Answer:
I expect that the peak currents of VPIX make the power
regulator that you use unstable. This is no problem as long
the VPIX isn’t use by other parts of the sensor.
So it is normal that when VPIX has its own regulator,
nothing strange becomes visible in the image. But probably,
VPIX is still not stable. However, the double sampling (both
the signal and the black level are affected by the voltage level
of VPIX) hide the problem for you.
Question:
Will pixel-to-pixel crosstalk only appear if a pixel is fully
saturated? Or will it also appear if for instance the pixel is
only as half it’s full well capacity. If it does happen even if
the pixel is not fully saturated do you know to what extent
it will happen - will it also be the same extent as shown in
Pixel−to−Pixel Cross Talk on page 34 of your data sheet?
Will pixel-to-pixel crosstalk only lead to charge leaking
from a pixel with higher signal to a pixel with low signal or
vice versa?
Answer:
The pixel-to-pixel crosstalk shown in Pixel−to−Pixel
Cross Talk on page 34 is cross-talk caused by floating
generated electrons that are not yet captured by any
photo-diode. So it has nothing to do with the actual level on
the accumulated photo-diodes. Only when the photo-diode
is really totally saturated, the floating electrons can behave
differently. The saturated photo-diode cannot capture more
electrons, so incoming electrons are not kept. The generated
electrons will be captured by neighboring photo-diodes that
are not yet completely saturated (or recombined).
So cross-talk as measured in Pixel−to−Pixel Cross Talk on
page 34 goes both from pixel with higher to lower signal
levels and vice versa. It doesn’t matter as long they are not
fully saturated. Note that the anti-blooming ground can keep
the pixel out of a completely saturation state.
Question:
The test results after proton beam are not as expected. To
interpret the results we want to know what the thickness is
of the epitaxial layer. Or more in detail the thickness of the
active area of the photo diode.
Answer:
EPI thickness: 5 mm, the nwell is about 1 mm deep.
Question:
How large is the active area compared to the overall pixel?
Almost the whole photo-sensitive area is active area.
Answer:
96% of the whole pixel is active area. Everything expect
the transistors and nwell, is p-doped
Question:
Is there a spice model available for the radiation hard pixel
used in the HAS device?
Answer:
No. The models that are used are just non-radiation hard
models.
ADDENDUM
AN-APS-FF-WO-06-001 (v1.): Application note on HAS readout methods
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65
NOIH2SM1000A
OPTICAL QUALITY − DEFINITIONS
Bad Pixel in PRNU Image
A PRNU image is an image where all pixels have a 50%
response of the full range of the entire pixel array. A bad
pixel in this image is a pixel with an ADC value that differs
more than 10% of the average response. This average
response can be calculated on the total pixel array for a
global measurement or on 32 x 32 pixels for a local
measurement.
Bad Row/Column
A bad row/column is detected in the PRNU image. A
row/column is defective when it differs more than 5% from
the average of a moving window of 32 rows/columns. A
row/column is also defined as defective when it has 100 or
more adjacent bad, bright, or dead pixels.
The following definitions and limits are used to define the
optical quality of the HAS2 type variants as outlined in
Table 10 on page 9.
Dead Pixel
A dead pixel is a pixel that has no electrical response. In
the image, this results in a pixel with fixed ADC value. The
number of pixels with ADC value 0 are count and
accumulated.
Bright Pixel in FPN Image
A FPN image is a dark image with the shortest possible
integration time. A bright pixel in this image is a pixel with
an ADC value higher than 20% of the full range of the entire
pixel array.
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