Cypress CY7C64713-128AXC Ez-usb fx1 usb microcontroller full speed usb peripheral controller Datasheet

CY7C64713
EZ-USB FX1™ USB Microcontroller
Full Speed USB Peripheral Controller
EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller
Features
■
■
■
Integrated, industry standard 8051 with enhanced features:
Single chip integrated USB transceiver, SIE, and enhanced
8051 microprocessor
❐
Up to 48 MHz clock rate
❐
Four clocks for each instruction cycle
Fit, form, and function upgradable to the FX2LP (CY7C68013A)
❐
Two USARTS
❐
Pin compatible
❐
Three counters or timers
❐
Object code compatible
❐
Expanded interrupt system
Functionally compatible (FX1 functionality is a subset of the
FX2LP)
❐
Two data pointers
❐
■
Draws no more than 65 mA in any mode, making the FX1
suitable for bus powered applications
■
Software: 8051 runs from internal RAM, which is:
❐
Downloaded using USB
❐
Loaded from EEPROM
❐
External memory device (128 pin configuration only)
■
16 KB of on-chip code/data RAM
■
Four programmable
endpoints
❐
BULK/INTERRUPT/ISOCHRONOUS
3.3 V operation with 5 V tolerant inputs
■
Smart SIE
■
Vectored USB interrupts
■
Separate data buffers for the setup and DATA portions of a
CONTROL transfer
■
Integrated I2C controller, running at 100 or 400 KHz
■
48 MHz, 24 MHz, or 12 MHz 8051 operation
■
Four integrated FIFOs
Buffering options: double, triple, and quad
■
Additional
endpoint
■
8- or 16-bit external data interface
■
Smart media standard ECC generation
■
GPIF
programmable
(BULK/INTERRUPT)
64-byte
❐
Allows direct connection to most parallel interfaces; 8- and
16-bit
❐
Programmable waveform descriptors and configuration
registers to define waveforms
❐
■
•
Brings glue and FIFOs inside for lower system cost
❐
Automatic conversion to and from 16-bit buses
❐
Master or slave operation
❐
FIFOs can use externally supplied clock or asynchronous
strobes
❐
Easy interface to ASIC and DSP ICs
■
Vectored for FIFO and GPIF Interrupts
■
Up to 40 general purpose IOs (GPIO)
■
Four package options:
Supports multiple ready (RDY) inputs and Control (CTL)
outputs
Cypress Semiconductor Corporation
Document Number: 38-08039 Rev. *J
❐
198 Champion Court
❐
128-pin TQFP
❐
100-pin TQFP
❐
56-pin SSOP
❐
56-pin QFN Pb-free
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 17, 2011
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CY7C64713
Logic Block Diagram
High performance micro
using standard tools
with lower-power options
VCC
x20
PLL
/0.5
/1.0
/2.0
Data (8)
Address (16)
FX1
8051 Core
12/24/48 MHz,
four clocks/cycle
1.5k
connected for
enumeration
D+
USB
D–
XCVR
CY
Smart
16 KB
RAM
Address (16) / Data Bus (8)
24 MHz
Ext. XTAL
I2C
Master
Abundant I/O
including two USARTS
Additional IOs (24)
ADDR (9)
GPIF
RDY (6)
CTL (6)
ECC
USB
Engine
Integrated
full speed XCVR
4 kB
FIFO
Enhanced USB core
Simplifies 8051 code
Document Number: 38-08039 Rev. *J
‘Soft Configuration’
Easy firmware changes
8/16
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Up to 96 MBytes
burst rate
FIFO and endpoint memory
(master or slave operation)
Page 2 of 72
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CY7C64713
Contents
Functional Description ..................................................... 4
Applications ...................................................................... 4
Functional Overview ........................................................ 4
USB Signaling Speed .................................................. 4
8051 Microprocessor ................................................... 4
I2C Bus ........................................................................ 5
Buses .......................................................................... 5
USB Boot Methods ...................................................... 5
ReNumeration™ .......................................................... 6
Bus-powered Applications ........................................... 6
Interrupt System .......................................................... 6
Reset and Wakeup ...................................................... 8
Program/Data RAM ..................................................... 9
Endpoint RAM ........................................................... 11
External FIFO Interface ............................................. 11
GPIF .......................................................................... 12
ECC Generation ........................................................ 13
USB Uploads and Downloads ................................... 13
Autopointer Access ................................................... 13
I2C Controller ............................................................. 13
Compatible with Previous Generation EZ-USB FX2 . 14
Pin Assignments ............................................................ 14
CY7C64713 Pin Definitions ............................................ 20
Register Summary .......................................................... 28
Absolute Maximum Ratings .......................................... 47
Operating Conditions ..................................................... 47
DC Characteristics ......................................................... 47
USB Transceiver ....................................................... 47
Document Number: 38-08039 Rev. *J
AC Electrical Characteristics ........................................ 48
USB Transceiver ....................................................... 48
PORTC Strobe Feature Timings ............................... 51
GPIF Synchronous Signals ....................................... 52
Slave FIFO Synchronous Read ................................. 53
Slave FIFO Asynchronous Read ............................... 54
Slave FIFO Synchronous Write ................................. 55
Slave FIFO Asynchronous Write ............................... 56
Slave FIFO Synchronous Packet End Strobe ........... 56
Slave FIFO Asynchronous Packet End Strobe ......... 58
Slave FIFO Output Enable ........................................ 58
Slave FIFO Address to Flags/Data ............................ 58
Slave FIFO Synchronous Address ............................ 59
Slave FIFO Asynchronous Address .......................... 59
Sequence Diagram .................................................... 60
Ordering Information ...................................................... 64
Ordering Code Definitions ......................................... 64
Package Diagrams .......................................................... 65
Quad Flat Package No Leads (QFN) Package
Design Notes ................................................................... 68
Acronyms ........................................................................ 70
Document Conventions ................................................. 70
Units of Measure ....................................................... 70
Document History Page ................................................. 71
Sales, Solutions, and Legal Information ...................... 72
Worldwide Sales and Design Support ....................... 72
Products .................................................................... 72
PSoC Solutions ......................................................... 72
Page 3 of 72
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CY7C64713
Functional Description
EZ-USB FX1 (CY7C64713) is a full speed, highly integrated,
USB microcontroller. By integrating the USB transceiver, Serial
Interface Engine (SIE), enhanced 8051 microcontroller, and a
programmable peripheral interface in a single chip, Cypress has
created a very cost effective solution that provides superior
time-to-market advantages.
FX1 does not support the low speed signaling mode of 1.5 Mbps
or the high speed mode of 480 Mbps.
8051 Microprocessor
The 8051 microprocessor embedded in the FX1 family has
256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
The EZ-USB FX1 is more economical, because it incorporates
the USB transceiver and provides a smaller footprint solution
than the USB SIE or external transceiver implementations. With
EZ-USB FX1, the Cypress Smart SIE handles most of the USB
protocol in hardware, freeing the embedded microcontroller for
application specific functions and decreasing the development
time to ensure USB compatibility.
8051 Clock Frequency
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8 or 16-bit data bus) provide an easy and
glueless interface to popular interfaces such as ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
Four Pb-free packages are defined for the family: 56-pin SSOP,
56-pin QFN, 100-pin TQFP, and 128-pin TQFP.
Applications
■
DSL modems
■
ATA interface
■
Memory card readers
■
Legacy conversion devices
■
Home PNA
■
Wireless LAN
■
MP3 players
■
Networking
The Reference Designs section of the cypress website provides
additional tools for typical USB applications. Each reference
design comes complete with firmware source and object code,
schematics,
and
documentation.
Please
visit
http://www.cypress.com for more information.
Functional Overview
USB Signaling Speed
FX1 operates at one of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
Full speed, with a signaling bit rate of 12 Mbps.
FX1 has an on-chip oscillator circuit that uses an external
24 MHz (±100 ppm) crystal with the following characteristics:
■
Parallel resonant
■
Fundamental mode
■
500 W drive level
■
12 pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY, and the internal counters
divide it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 is
dynamically changed by the 8051 through the CPUCS register.
The CLKOUT pin, which is three-stated and inverted using the
internal control bits, outputs the 50% duty cycle 8051 clock at the
selected 8051 clock frequency which is 48, 24, or 12 MHz.
USARTS
FX1 contains two standard 8051 USARTs, addressed by Special
Function Register (SFR) bits. The USART interface pins are
available on separate I/O pins, and are not multiplexed with port
pins.
UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48, 24, 12 MHz) such that
it always presents the correct frequency for 230-KBaud
operation.[1]
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX1 functions. These SFR additions are shown
in Table 1 on page 5. Bold type indicates non-standard,
enhanced 8051 registers. The two SFR rows that end with ‘0’ and
‘8’ contain bit addressable registers. The four I/O ports A–D use
the SFR addresses used in the standard 8051 for ports 0–3,
which are not implemented in the FX1. Because of the faster and
more efficient SFR addressing, the FX1 I/O ports are not
addressable in the external RAM space (using the MOVX
instruction).
Note
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a ‘1’ for UART0 and UART1, respectively.
Document Number: 38-08039 Rev. *J
Page 4 of 72
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CY7C64713
Figure 1. Crystal Configuration
C1
24 MHz
12 pF
C2
12 pF
12-pF capacitor values assumes
a trace capacitance of 3 pF per
side on a four layer FR4 PCA
20 × PLL
Table 1. Special Function Registers
x
8x
9x
Ax
Bx
Cx
Dx
Ex
Fx
0
IOA
IOB
IOC
IOD
SCON1
PSW
ACC
B
SBUF1
EICON
EIE
EIP
1
SP
EXIF
INT2CLR
IOE
2
DPL0
MPAGE
INT4CLR
OEA
3
DPH0
OEB
4
DPL1
OEC
5
DPH1
OED
6
DPS
OEE
7
PCON
8
TCON
9
TMOD
SBUF0
A
TL0
AUTOPTRH1
B
TL1
C
TH0
D
TH1
AUTOPTRH2
GPIFSGLDATH
E
CKCON
AUTOPTRL2
GPIFSGLDATLX
F
SCON0
IE
IP
T2CON
EP2468STAT
EP01STAT
RCAP2L
AUTOPTRL1
EP24FIFOFLGS
GPIFTRIG
RCAP2H
reserved
EP68FIFOFLGS
reserved
AUTOPTRSETUP
I2C Bus
TL2
TH2
GPIFSGLDATLNOX
FX1 supports the I2C bus as a master only at 100/400 KHz. SCL
and SDA pins have open drain outputs and hysteresis inputs.
These signals must be pulled up to 3.3 V, even if no I2C device
is connected.
in place of the internally stored values (0xC0). Alternatively, it
boot-loads the EEPROM contents into an internal RAM (0xC2).
If no EEPROM is detected, FX1 enumerates using internally
stored descriptors. The default ID values for FX1 are
VID/PID/DID (0x04B4, 0x6473, 0xAxxx where xxx=Chip
revision).[2]
Buses
Table 2. Default ID Values for FX1
All packages: 8 or 16-bit ‘FIFO’ bidirectional data bus,
multiplexed on I/O ports B and D. 128-pin package: adds 16-bit
output only 8051 address bus, 8-bit bidirectional data bus.
Vendor ID 0x04B4 Cypress Semiconductor
USB Boot Methods
Product ID 0x6473 EZ-USB FX1
During the power up sequence, internal logic checks the I2C port
for the connection of an EEPROM whose first byte is either 0xC0
or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
Device
release
Default VID/PID/DID
0xAnnn Depends on chip revision (nnn = chip
revision where first silicon = 001)
Notes
2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Document Number: 38-08039 Rev. *J
Page 5 of 72
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CY7C64713
ReNumeration™
USB-Interrupt Autovectors
Because the FX1’s configuration is soft, one chip can take on the
identities of multiple distinct USB devices.
The main USB interrupt is shared by 27 interrupt sources. The
FX1 provides a second level of interrupt vectoring, called
Autovectoring, to save code and processing time that is normally
required to identify the individual USB interrupt source. When a
USB interrupt is asserted, the FX1 pushes the program counter
on to its stack and then jumps to address 0x0043, where it
expects to find a “jump” instruction to the USB Interrupt service
routine.
When first plugged into the USB, the FX1 enumerates
automatically and downloads firmware and the USB descriptor
tables over the USB cable. Next, the FX1 enumerates again, this
time as a device defined by the downloaded information. This
patented two step process, called ReNumeration, happens
instantly when the device is plugged in, with no indication that
the initial download step has occurred.
Two control bits in the USBCS (USB Control and Status) register
control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate if the firmware or the Default USB Device handles
device requests over endpoint zero:
■
RENUM = 0, the Default USB Device handles device requests
■
RENUM = 1, the firmware handles device requests
Bus-powered Applications
The FX1 fully supports bus powered designs by enumerating
with less than 100 mA as required by the USB specification.
Interrupt System
INT2 Interrupt Request and Enable Registers
FX1 implements an autovector feature for INT2 and INT4. There
are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors.
See EZ-USB Technical Reference Manual (TRM) for more
details.
The FX1 jump instruction is encoded as shown in Table 3.
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP
register), the FX1 substitutes its INT2VEC byte. Therefore, if the
high byte (“page”) of a jump table address is preloaded at
location 0x0044, the automatically inserted INT2VEC byte at
0x0045 directs the jump to the correct address out of the 27
addresses within the page.
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual
USB-interrupt sources, the FIFO/GPIF interrupt is shared among
14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, such
as the USB Interrupt, can employ autovectoring. Table 4 on page
7 shows the priority and INT4VEC values for the 14 FIFO/GPIF
interrupt sources.
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual
USB-interrupt sources, the FIFO/GPIF interrupt is shared among
14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, such
as the USB Interrupt, can employ autovectoring.
Table 4 on page 7 shows the priority and INT4VEC values for the
14 FIFO/GPIF interrupt sources.
Table 3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority
INT2VEC Value
1
00
SUDAV
Source
Notes
2
04
SOF
Start of Frame
3
08
SUTOK
Setup Token Received
4
0C
SUSPEND
USB Suspend request
5
10
USB RESET
Bus reset
6
14
7
18
8
1C
9
Setup Data Available
Reserved
EP0ACK
FX1 ACK’d the CONTROL Handshake
20
EP0-IN
EP0-IN ready to be loaded with data
10
24
EP0-OUT
EP0-OUT has USB data
11
28
EP1-IN
EP1-IN ready to be loaded with data
12
2C
EP1-OUT
EP1-OUT has USB data
13
30
EP2
IN: buffer available. OUT: buffer has data
14
34
EP4
IN: buffer available. OUT: buffer has data
15
38
EP6
IN: buffer available. OUT: buffer has data
16
3C
EP8
IN: buffer available. OUT: buffer has data
17
40
IBN
IN-Bulk-NAK (any IN endpoint)
Reserved
Document Number: 38-08039 Rev. *J
Page 6 of 72
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CY7C64713
Table 3. INT2 USB Interrupts (continued)
USB INTERRUPT TABLE FOR INT2
Priority
INT2VEC Value
18
44
Source
Notes
Reserved
19
48
EP0PING
EP0 OUT was Pinged and it NAK’d
20
4C
EP1PING
EP1 OUT was Pinged and it NAK’d
21
50
EP2PING
EP2 OUT was Pinged and it NAK’d
22
54
EP4PING
EP4 OUT was Pinged and it NAK’d
23
58
EP6PING
EP6 OUT was Pinged and it NAK’d
24
5C
EP8PING
EP8 OUT was Pinged and it NAK’d
25
60
ERRLIMIT
Bus errors exceeded the programmed limit
26
64
27
68
Reserved
28
6C
Reserved
29
70
EP2ISOERR
ISO EP2 OUT PID sequence error
30
74
EP4ISOERR
ISO EP4 OUT PID sequence error
31
78
EP6ISOERR
ISO EP6 OUT PID sequence error
32
7C
EP8ISOERR
ISO EP8 OUT PID sequence error
Table 4. Individual FIFO/GPIF Interrupt Sources
Priority
INT4VEC Value
1
80
Source
EP2PF
Notes
Endpoint 2 Programmable Flag
2
84
EP4PF
Endpoint 4 Programmable Flag
3
88
EP6PF
Endpoint 6 Programmable Flag
4
8C
EP8PF
Endpoint 8 Programmable Flag
5
90
EP2EF
Endpoint 2 Empty Flag
6
94
EP4EF
Endpoint 4 Empty Flag
7
98
EP6EF
Endpoint 6 Empty Flag
8
9C
EP8EF
Endpoint 8 Empty Flag
9
A0
EP2FF
Endpoint 2 Full Flag
10
A4
EP4FF
Endpoint 4 Full Flag
11
A8
EP6FF
Endpoint 6 Full Flag
12
AC
EP8FF
Endpoint 8 Full Flag
13
B0
GPIFDONE
GPIF Operation Complete
14
B4
GPIFWF
GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSETUP
register), the FX1 substitutes its INT4VEC byte. Therefore, if the
high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically inserted INT4VEC byte at
0x0055 directs the jump to the correct address out of the 14
Document Number: 38-08039 Rev. *J
addresses within the page. When the ISR occurs, the FX1
pushes the program counter onto its stack and then jumps to
address 0x0053, where it expects to find a “jump” instruction to
the ISR Interrupt service routine.
Page 7 of 72
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CY7C64713
Reset and Wakeup
Reset Pin
The input pin, RESET#, resets the FX1 when asserted. This pin
has hysteresis and is active LOW. When a crystal is used with
the CY7C64713, the reset period must allow for the stabilization
of the crystal and the PLL. This reset period must be
approximately 5 ms after VCC has reached 3.0 Volts. If the
crystal input pin is driven by a clock signal the internal PLL
stabilizes in 200 s after VCC has reached 3.0 V[3]. Figure 2 on
page 8 shows a power on reset condition and a reset applied
during operation. A power on reset is defined as the time a reset
is asserted when power is being applied to the circuit. A powered
reset is defined to be when the FX1 has been previously
powered on and operating and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation and is found on the
Cypress web site. While the application note discusses the FX2,
the information provided applies also to the FX1. For more
information on reset implementation for the FX2 family of
products visit http://www.cypress.com.
Figure 2. Reset Timing Plots
RESET#
VIL
RESET#
VIL
3.3 V
3.0 V
3.3 V
VCC
VCC
0V
0V
TRESET
TRESET
Power on Reset
Powered Reset
wakeup interrupt. This applies irrespective of whether the FX1 is
connected to the USB or not.
Table 5. Reset Timing Values
Condition
TRESET
Power On Reset with crystal
5 ms
Power On Reset with external
clock
200 s + Clock stability time
Powered Reset
200 s
Wakeup Pins
The 8051 puts itself and the rest of the chip into a power down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts, after the PLL stabilizes, and then the 8051 receives a
The FX1 exits the power down (USB suspend) state using one
of the following methods:
■
USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX1 and initiate a wakeup).
■
External logic asserts the WAKEUP pin.
■
External logic asserts the PA3/WU2 pin.
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is by default active LOW.
Note
3. If the external clock is powered at the same time as the CY7C64713 and has a stabilization wait period. It must be added to the 200 s.
Document Number: 38-08039 Rev. *J
Page 8 of 72
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CY7C64713
Program/Data RAM
Size
The FX1 has 16 KBytes of internal program/data RAM, where
PSEN#/RD# signals are internally ORed to allow the 8051 to
access it as both program and data memory. No USB control
registers appear in this space.
Two memory maps are shown in the following diagrams:
■
Figure 3 on page 9 Internal Code Memory, EA = 0
■
Figure 4 on page 10 External Code Memory, EA = 1.
Internal Code Memory, EA = 0
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside the
chip. This allows the user to connect a 64 KByte memory without
requiring the address decodes to keep clear of internal memory
spaces.
Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
spaces have the following access:
■
USB download
■
USB upload
■
Setup data pointer
■
I2C interface boot load
This mode implements the internal 16 KByte block of RAM
(starting at 0) as combined code and data memory. When the
Figure 3. Internal Code Memory, EA = 0.
Inside FX1
Outside FX1
FFFF
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
E200
E1FF 0.5 KBytes RAM
E000 Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
48 KBytes
External
Code
Memory
(PSEN#)
3FFF
16 KBytes RAM
Code and Data
(PSEN#,RD#,WR#)*
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
0000
Data
Code
*SUDPTR, USB upload/download, I2C interface boot access
Document Number: 38-08039 Rev. *J
Page 9 of 72
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CY7C64713
External Code Memory, EA = 1
The bottom 16 KBytes of program memory is external, and therefore the bottom 16 KBytes of internal RAM is accessible only as data
memory.
Figure 4. External Code Memory, EA = 1
Inside FX1
Outside FX1
FFFF
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
E200
E1FF
0.5 KBytes RAM
E000 Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
64 KBytes
External
Code
Memory
(PSEN#)
3FFF
16 KBytes
RAM
Data
(RD#,WR#)*
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
0000
Data
Code
2
*SUDPTR, USB upload/download, I C interface boot access
Document Number: 38-08039 Rev. *J
Page 10 of 72
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CY7C64713
Figure 5. Register Addresses
FFFF
4 KBytes EP2-EP8
buffers
(8 x 512)
Not all Space is available
for all transfer types
F000
EFFF
2 KBytes RESERVED
E800
E7FF
E7C0
E7BF
E780
E77F
E740
E73F
E700
E6FF
E500
E4FF
E480
E47F
E400
E3FF
E200
E1FF
64 Bytes EP1IN
64 Bytes EP1OUT
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
(512)
Reserved (128)
128 bytes GPIF Waveforms
Reserved (512)
512 bytes
E000
8051 xdata RAM
Endpoint RAM
Table 6. Default Alternate Settings
Size
■
3 × 64 bytes
(Endpoints 0 and 1)
■
8 × 512 bytes
(Endpoints 2, 4, 6, 8)
Organization
Alternate
Setting
ep0
0
1
64 64
2
64
3
64
ep1out
0
64 bulk
64 int
64 int
ep1in
0
64 bulk
64 int
64 int
■
EP0—Bidirectional endpoint zero, 64 byte buffer
ep2
0
64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
■
EP1IN, EP1OUT—64 byte buffers, bulk or interrupt
ep4
0
64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
■
EP2, 4, 6, 8—Eight 512-byte buffers, bulk, interrupt, or
isochronous, of which only the transfer size is available. EP4
and EP8 are double buffered, while EP2 and 6 are either
double, triple, or quad buffered. Regardless of the physical size
of the buffer, each endpoint buffer accommodates only one full
speed packet. For bulk endpoints, the maximum number of
bytes it can accommodate is 64, even though the physical
buffer size is 512 or 1024. For an ISOCHRONOUS endpoint
the maximum number of bytes it can accommodate is 1023.
For endpoint configuration options, see Figure 6 on page 12.
ep6
0
64 bulk in (2×) 64 int in (2×)
ep8
0
64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
Setup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
data from a CONTROL transfer.
Default Alternate Settings
In the following table, ‘0’ means “not implemented”, and ‘2×’
means “double buffered”.
Document Number: 38-08039 Rev. *J
64 iso in (2×)
External FIFO Interface
Architecture
The FX1 slave FIFO architecture has eight 512-byte blocks in the
endpoint RAM that directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
these buffers depend on the USB transfer mode as described in
the section Organization.
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the I/O transfer logic. The
transfer logic takes two forms: the GPIF for internally generated
control signals or the slave FIFO interface for externally
controlled transfers.
Page 11 of 72
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CY7C64713
Figure 6. Endpoint Configuration
EP0 IN&OUT
64
64
64
EP1 IN
64
64
64
EP1 OUT
64
64
64
EP2
EP2
EP2
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
EP2
EP2
EP2
EP2
EP2
EP2
EP2
64
64
64
64
64
64
64
64
64
64
64
64
EP4
EP4
64
64
64
64
64
64
64
64
64
64
64
64
EP6
64
64
64
64
EP6
1023
EP8
64
EP6
EP6
64
64
64
64
1023
64
64
1
2
1023
3
64
1023
1023
EP6
1023
EP6
EP6
64
64
64
64
64
64
4
5
The FX1 endpoint FIFOS are implemented as eight physically
distinct 256 × 16 RAM blocks. The 8051/SIE can switch any of
the RAM blocks between two domains: the USB (SIE) domain
and the 8051-I/O Unit domain. This switching is done
instantaneously, giving essentially zero transfer time between
“USB FIFOS” and “Slave FIFOS”. While they are physically the
same memory, no bytes are actually transferred between
buffers.
At any time, some RAM blocks fill or empty with USB data under
SIE control, while other RAM blocks are available to the 8051
and the I/O control unit. The RAM blocks operate as a single-port
in the USB domain, and dual port in the 8051-I/O domain. The
blocks are configured as single, double, triple, or quad buffered.
The I/O control unit implements either an internal master (M for
master) or external master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0]
to select a FIFO. The RDY pins (two in the 56-pin package, six
in the 100-pin and 128-pin packages) are used as flag inputs
from an external FIFO or other logic if desired. The GPIF is run
from either an internally derived clock or an externally supplied
clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s
(48 MHz IFCLK with 16-bit interface).
In Slave (S) mode, the FX1 accepts either an internally derived
clock or an externally supplied clock (IFCLK with a maximum
frequency of 48 MHz) and SLCS#, SLRD, SLWR, SLOE,
PKTEND signals from external logic. When using an external
IFCLK, the external clock must be present before switching to
the external clock with the IFCLKSRC bit. Each endpoint can
individually be selected for byte or word operation by an internal
configuration bit, and a Slave FIFO Output Enable signal SLOE
enables data of the selected width. External logic must ensure
that the output enable signal is inactive when writing data to a
slave FIFO. The slave interface can also operate
asynchronously, where the SLRD and SLWR signals act directly
EP6
64
64
EP6
64
1023
64
EP8
EP8
Master/Slave Control Signals
Document Number: 38-08039 Rev. *J
1023
1023
1023
64
EP8
64
1023
1023
64
EP4
EP6
1023
EP2 EP2
64
1023
6
64
64
64
64
7
8
1023
9
1023
1023
1023
EP8
64
64
64
64
10
1023
11
1023
12
as strobes, rather than a clock qualifier as in the synchronous
mode. The signals SLRD, SLWR, SLOE, and PKTEND are gated
by the signal SLCS#.
GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz.
Alternatively, an externally supplied clock of 5 to 48 MHz feeding
the IFCLK pin is used as the interface clock. IFCLK is configured
to function as an output clock when the GPIF and FIFOs are
internally clocked. An output enable bit in the IFCONFIG register
turns this clock output off, if desired. Another bit within the
IFCONFIG register inverts the IFCLK signal whether internally or
externally sourced.
GPIF
The GPIF is a flexible 8 or 16-bit parallel interface driven by a
user programmable finite state machine. It allows the
CY7C64713 to perform local bus mastering, and can implement
a wide variety of protocols such as ATA interface, printer parallel
port, and Utopia.
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general purpose Ready
inputs (RDY). The data bus width is 8 or 16 bits. Each GPIF
vector defines the state of the control outputs, and determines
what state a Ready input (or multiple inputs) must be before
proceeding. The GPIF vector is programmed to advance a FIFO
to the next data value, advance an address, and so on. A
sequence of the GPIF vectors create a single waveform that
executes to perform the data move between the FX1 and the
external device.
Six Control OUT Signals
The 100-pin and 128-pin packages bring out all six Control
Output pins (CTL0–CTL5). The 8051 programs the GPIF unit to
define the CTL waveforms. The 56-pin package brings out three
Page 12 of 72
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CY7C64713
of these signals: CTL0–CTL2. CTLx waveform edges are
programmed to make transitions as fast as once per clock
(20.8 ns using a 48 MHz clock).
Six Ready IN Signals
The 100-pin and 128-pin packages bring out all six Ready inputs
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56 pin package brings out two
of these signals, RDY0–1.
Nine GPIF Address OUT Signals
Nine GPIF address lines are available in the 100-pin and 128-pin
packages: GPIFADR[8..0]. The GPIF address lines allow
indexing through up to a 512 byte block of RAM. If more address
lines are needed, I/O port pins are used.
Long Transfer Mode
In Master mode, the 8051 appropriately sets the GPIF
transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1,
or GPIFTCB0) for unattended transfers of up to 232 transactions.
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions are
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
ECC Generation
The EZ-USB FX1 can calculate ECCs (Error Correcting Codes)
on data that pass across its GPIF or Slave FIFO interfaces.
There are two ECC configurations: Two ECCs, each calculated
over 256 bytes (SmartMedia™ Standard); and one ECC
calculated over 512 bytes.
The ECC can correct any one-bit error or detect any two-bit error.
Note To use the ECC logic, the GPIF or Slave FIFO interface
must be configured for byte-wide operation.
ECC Implementation
The two ECC configurations are selected by the ECCM bit:
0.0.0.1 ECCM = 0
Two 3-byte ECCs, each calculated over a 256-byte block of data.
This configuration conforms to the SmartMedia Standard.
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 256 bytes of data
is calculated and stored in ECC1. The ECC for the next 256 bytes
is stored in ECC2. After the second ECC is calculated, the values
in the ECCx registers do not change until the ECCRESET is
written again, even if more data is subsequently passed across
the interface.
0.0.0.2 ECCM = 1
One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 512 bytes of data
is calculated and stored in ECC1; ECC2 is not used. After the
ECC is calculated, the value in ECC1 does not change until the
ECCRESET is written again, even if more data is subsequently
passed across the interface
USB Uploads and Downloads
The core has the ability to directly edit the data contents of the
internal 16 KByte RAM and of the internal 512 byte scratch pad
RAM via a vendor specific command. This capability is normally
used when ‘soft’ downloading user code and is available only to
and from the internal RAM, only when the 8051 is held in reset.
The available RAM spaces are 16 KBytes from 0x0000–0x3FFF
(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad
data RAM).[4]
Autopointer Access
FX1 provides two identical autopointers. They are similar to the
internal 8051 data pointers, but with an additional feature: they
can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. The autopointers are available in external FX1 registers,
under the control of a mode bit (AUTOPTRSETUP.0). Using the
external FX1 autopointer access (at 0xE67B–0xE67C) allows
the autopointer to access all RAM, internal and external, to the
part. Also, the autopointers can point to any FX1 register or
endpoint buffer space. When autopointer access to external
memory is enabled, the location 0xE67B and 0xE67C in XDATA
and the code space cannot be used.
I2C Controller
FX1 has one I2C port that is driven by two internal controllers:
one that automatically operates at boot time to load VID/PID/DID
and configuration information; and another that the 8051, once
running, uses to control external I2C devices. The I2C port
operates in master mode only.
I2C Port Pins
The I2C pins SCL and SDA must have external 2.2 k pull up
resistors even if no EEPROM is connected to the FX1. External
EEPROM device address pins must be configured properly. See
Table 7 for configuring the device address pins.
Table 7. Strap Boot EEPROM Address Lines to These Values
Bytes
Example EEPROM
A2
A1
A0
16
24LC00[5]
N/A
N/A
N/A
128
24LC01
0
0
0
256
24LC02
0
0
0
4K
24LC32
0
0
1
8K
24LC64
0
0
1
16K
24LC128
0
0
1
Notes
4. After the data is downloaded from the host, a ‘loader’ executes from the internal RAM to transfer downloaded data to the external memory.
5. This EEPROM has no address pins.
Document Number: 38-08039 Rev. *J
Page 13 of 72
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CY7C64713
I2C Interface Boot Load Access
I2
At power on reset the C interface boot loader loads the
VID/PID/DID configuration bytes and up to 16 KBytes of
program/data. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
is in reset. I2C interface boot loads only occur after power on
reset.
I2C Interface General Purpose Access
The 8051 can control peripherals connected to the I2C bus using
the I2CTL and I2DAT registers. FX1 provides I2C master control
only, because it is never an I2C slave.
Compatible with Previous Generation EZ-USB FX2
The EZ-USB FX1 is fit, form, and function upgradable to the
EZ-USB FX2LP. This makes for an easy transition for designers
wanting to upgrade their systems from full speed to high speed
designs. The pinout and package selection are identical, and all
firmware developed for the FX1 function in the FX2LP with
proper addition of high speed descriptors and speed switching
code.
Pin Assignments
Figure 7 on page 15 identifies all signals for the three package
types. The following pages illustrate the individual pin diagrams,
Document Number: 38-08039 Rev. *J
plus a combination diagram showing which of the full set of
signals are available in the 128, 100, and 56-pin packages.
The signals on the left edge of the 56-pin package in Figure 7 on
page 15 are common to all versions in the FX1 family. Three
modes are available in all package versions: Port, GPIF master,
and Slave FIFO. These modes define the signals on the right
edge of the diagram. The 8051 selects the interface mode using
the IFCONFIG[1:0] register bits. Port mode is the power on
default configuration.
The 100-pin package adds functionality to the 56-pin package by
adding these pins:
■
PORTC or alternate GPIFADR[7:0] address signals
■
PORTE or alternate GPIFADR[8] address signal and seven
additional 8051 signals
■
Three GPIF Control signals
■
Four GPIF Ready signals
■
Nine 8051 signals (two USARTs, three timer inputs, INT4,and
INT5#)
■
BKPT, RD#, WR#.
The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version. In the 100-pin and
128-pin versions, an 8051 control bit is set to pulse the RD# and
WR# pins when the 8051 reads from and writes to the PORTC.
Page 14 of 72
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CY7C64713
Figure 7. Signals
Port
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
56
GPIF Master
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
IFCLK
CLKOUT
DPLUS
DMINUS
100
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
128
Document Number: 38-08039 Rev. *J
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
RDY0
RDY1
SLRD
SLWR
CTL0
CTL1
CTL2
FLAGA
FLAGB
FLAGC
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2
T1
T0
RD#
WR#
CS#
OE#
PSEN#
D7
D6
D5
D4
D3
D2
D1
D0
EA
Slave FIFO
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Page 15 of 72
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CY7C64713
Figure 8. CY7C64713 128-pin TQFP Pin Assignment
27
28
29
30
31
32
33
34
35
36
37
38
103
26
104
25
105
24
106
23
107
22
108
21
109
20
110
19
111
18
112
17
113
16
114
15
115
14
116
13
117
12
118
11
119
10
120
9
121
8
122
7
123
6
124
5
125
4
126
3
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
A4
A5
A6
A7
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
A8
A9
A10
2
127
128
1
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
EA
SCL
SDA
OE#
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
A3
A2
A1
A0
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
D6
D5
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
GND
CY7C64713
128-pin TQFP
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
D4
D3
D2
D1
D0
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
CS#
WR#
RD#
PSEN#
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
* indicates programmable polarity
Document Number: 38-08039 Rev. *J
Page 16 of 72
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CY7C64713
Figure 9. CY7C64713 100-pin TQFP Pin Assignment
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
SCL
SDA
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
CY7C64713
100-pin TQFP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
WR#
RD#
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Document Number: 38-08039 Rev. *J
* indicates programmable polarity
Page 17 of 72
[+] Feedback
CY7C64713
Figure 10. CY7C64713 56-pin SSOP Pin Assignment
CY7C64713
56-pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK
RESERVED
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
* indicates programmable polarity
Document Number: 38-08039 Rev. *J
Page 18 of 72
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CY7C64713
Figure 11. CY7C64713 56-pin QFN Pin Assignment
GND
VCC
CLKOUT
GND
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RDY0/*SLRD
1
42
RESET#
RDY1/*SLWR
2
41
GND
AVCC
3
40
PA7/*FLAGD/SLCS#
XTALOUT
4
39
PA6/*PKTEND
XTALIN
5
38
PA5/FIFOADR1
AGND
6
37
PA4/FIFOADR0
AVCC
7
36
PA3/*WU2
DPLUS
8
35
PA2/*SLOE
DMINUS
9
34
PA1/INT1#
AGND
10
33
PA0/INT0#
VCC
11
32
VCC
GND
12
31
CTL2/*FLAGC
*IFCLK
13
30
CTL1/*FLAGB
RESERVED
14
29
CTL0/*FLAGA
CY7C64713
56-pin QFN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
GND
VCC
GND
* indicates programmable polarity
Document Number: 38-08039 Rev. *J
Page 19 of 72
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CY7C64713
CY7C64713 Pin Definitions
The FX1 Pin Definitions for CY7C64713 follow.[6]
Table 8. FX1 Pin Definitions
128-pin 100-pin 56-pin
TQFP TQFP SSOP
56-pin
QFN
Name
Type
Default
Description
10
9
10
3
AVCC
Power
N/A
Analog VCC. Connect this pin to 3.3 V power source. This
signal provides power to the analog section of the chip.
17
16
14
7
AVCC
Power
N/A
Analog VCC. Connect this pin to 3.3 V power source. This
signal provides power to the analog section of the chip.
13
12
13
6
AGND
Ground
N/A
Analog Ground. Connect to ground with as short a path as
possible.
20
19
17
10
AGND
Ground
N/A
Analog Ground. Connect to ground with as short a path as
possible.
19
18
16
9
DMINUS
I/O/Z
Z
18
17
15
8
USB D– Signal. Connect to the USB D– signal.
DPLUS
I/O/Z
Z
USB D+ Signal. Connect to the USB D+ signal.
94
A0
Output
L
95
A1
Output
L
96
A2
Output
L
8051 Address Bus. This bus is driven at all times. When the
8051 is addressing the internal RAM it reflects the internal
address.
97
A3
Output
L
117
A4
Output
L
118
A5
Output
L
119
A6
Output
L
120
A7
Output
L
126
A8
Output
L
127
A9
Output
L
128
A10
Output
L
21
A11
Output
L
22
A12
Output
L
23
A13
Output
L
24
A14
Output
L
25
A15
Output
L
59
D0
I/O/Z
Z
60
D1
I/O/Z
Z
61
D2
I/O/Z
Z
62
D3
I/O/Z
Z
63
D4
I/O/Z
Z
86
D5
I/O/Z
Z
87
D6
I/O/Z
Z
88
D7
I/O/Z
Z
39
PSEN#
Output
H
8051 Data Bus. This bidirectional bus is high impedance when
inactive, input for bus reads, and output for bus writes. The data
bus is used for external 8051 program and data memory. The
data bus is active only for external bus accesses, and is driven
LOW in suspend.
Program Store Enable. This active LOW signal indicates an
8051 code fetch from external memory. It is active for program
memory fetches from 0x4000–0xFFFF when the EA pin is
LOW, or from 0x0000–0xFFFF when the EA pin is HIGH.
Note
6. Do not leave unused inputs floating. Tie either HIGH or LOW as appropriate. Pull outputs up or down to ensure signals at power up and in standby. Note that no
pins must be driven when the device is powered down.
Document Number: 38-08039 Rev. *J
Page 20 of 72
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CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin
TQFP TQFP SSOP
34
28
99
77
49
56-pin
QFN
42
35
Name
Type
Default
Description
BKPT
Output
L
Breakpoint. This pin goes active (HIGH) when the 8051
address bus matches the BPADDRH/L registers and
breakpoints are enabled in the BREAKPT register (BPEN = 1).
If the BPPULSE bit in the BREAKPT register is HIGH, this
signal pulses HIGH for eight 12-/24-/48 MHz clocks. If the
BPPULSE bit is LOW, the signal remains HIGH until the 8051
clears the BREAK bit (by writing ‘1’ to it) in the BREAKPT
register.
RESET#
Input
N/A
Active LOW Reset. Resets the entire chip. See the section
Reset and Wakeup on page 8 for more details.
EA
Input
N/A
External Access. This pin determines where the 8051 fetches
code between addresses 0x0000 and 0x3FFF. If EA = 0 the
8051 fetches this code from its internal RAM. IF EA = 1 the 8051
fetches this code from external memory.
XTALIN
Input
N/A
Crystal Input. Connect this signal to a 24 MHz
parallel-resonant, fundamental mode crystal and load capacitor
to GND.
It is also correct to drive the XTALIN with an external 24 MHz
square wave derived from another clock source. When driving
from an external source, the driving signal must be a 3.3 V
square wave.
N/A
Crystal Output. Connect this signal to a 24 MHz
parallel-resonant, fundamental mode crystal and load capacitor
to GND.
If an external clock is used to drive XTALIN, leave this pin open.
12
11
12
5
11
10
11
4
XTALOUT Output
1
100
5
54
CLKOUT
O/Z
12 MHz CLKOUT. 12, 24 or 48 MHz clock, phase locked to the 24 MHz
input clock. The 8051 defaults to 12 MHz operation. The 8051
may three-state this output by setting CPUCS.1 = 1.
82
67
40
33
PA0 or
INT0#
I/O/Z
I (PA0) Multiplexed pin whose function is selected by PORTACFG.0
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which
is either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
83
68
41
34
PA1 or
INT1#
I/O/Z
I (PA1) Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which
is either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
84
69
42
35
PA2 or
SLOE
I/O/Z
I (PA2) Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional I/O port pin.
SLOE is an input-only output enable with programmable
polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to
FD[7..0] or FD[15..0].
85
70
43
36
PA3 or
WU2
I/O/Z
I (PA3) Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by
WU2EN bit (WAKEUP.1) and polarity set by WU2POL
(WAKEUP.4). If the 8051 is in suspend and WU2EN = 1, a
transition on this pin starts up the oscillator and interrupts the
8051 to allow it to exit the suspend mode. Asserting this pin
inhibits the chip from suspending, if WU2EN = 1.
Port A
Document Number: 38-08039 Rev. *J
Page 21 of 72
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CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin
TQFP TQFP SSOP
56-pin
QFN
Name
Type
Default
Description
89
71
44
37
PA4 or
FIFOADR0
I/O/Z
I (PA4) Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
90
72
45
38
PA5 or
FIFOADR1
I/O/Z
I (PA5) Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
91
73
46
39
PA6 or
PKTEND
I/O/Z
I (PA6) Multiplexed pin whose function is selected by the
IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet data to
the endpoint and whose polarity is programmable via
FIFOPINPOLAR.5.
92
74
47
40
PA7 or
FLAGD or
SLCS#
I/O/Z
I (PA7) Multiplexed pin whose function is selected by the
IFCONFIG[1:0] and PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag
signal.
SLCS# gates all other slave FIFO enable/strobes
44
34
25
18
PB0 or
FD[0]
I/O/Z
I (PB0) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
45
35
26
19
PB1 or
FD[1]
I/O/Z
I (PB1) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
46
36
27
20
PB2 or
FD[2]
I/O/Z
I (PB2) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
47
37
28
21
PB3 or
FD[3]
I/O/Z
I (PB3) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
54
44
29
22
PB4 or
FD[4]
I/O/Z
I (PB4) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
55
45
30
23
PB5 or
FD[5]
I/O/Z
I (PB5) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
56
46
31
24
PB6 or
FD[6]
I/O/Z
I (PB6) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
Port B
Document Number: 38-08039 Rev. *J
Page 22 of 72
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CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin
TQFP TQFP SSOP
57
47
32
56-pin
QFN
Name
Type
Default
25
PB7 or
FD[7]
I/O/Z
I (PB7) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
Description
PORT C
72
57
PC0 or
GPIFADR0
I/O/Z
I (PC0) Multiplexed pin whose function is selected by PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
73
58
PC1 or
GPIFADR1
I/O/Z
I (PC1) Multiplexed pin whose function is selected by PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
74
59
PC2 or
GPIFADR2
I/O/Z
I (PC2) Multiplexed pin whose function is selected by PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
75
60
PC3 or
GPIFADR3
I/O/Z
I (PC3) Multiplexed pin whose function is selected by PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
76
61
PC4 or
GPIFADR4
I/O/Z
I (PC4) Multiplexed pin whose function is selected by PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
77
62
PC5 or
GPIFADR5
I/O/Z
I (PC5) Multiplexed pin whose function is selected by PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
78
63
PC6 or
GPIFADR6
I/O/Z
I (PC6) Multiplexed pin whose function is selected by PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
79
64
PC7 or
GPIFADR7
I/O/Z
I (PC7) Multiplexed pin whose function is selected by PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
PORT D
102
80
52
45
PD0 or
FD[8]
I/O/Z
I (PD0) Multiplexed pin whose function is selected by
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
the
103
81
53
46
PD1 or
FD[9]
I/O/Z
I (PD1) Multiplexed pin whose function is selected by
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
the
104
82
54
47
PD2 or
FD[10]
I/O/Z
I (PD2) Multiplexed pin whose function is selected by
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
the
105
83
55
48
PD3 or
FD[11]
I/O/Z
I (PD3) Multiplexed pin whose function is selected by
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
the
121
95
56
49
PD4 or
FD[12]
I/O/Z
I (PD4) Multiplexed pin whose function is selected by
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
the
122
96
1
50
PD5 or
FD[13]
I/O/Z
I (PD5) Multiplexed pin whose function is selected by
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
the
123
97
2
51
PD6 or
FD[14]
I/O/Z
I (PD6) Multiplexed pin whose function is selected by
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
the
Document Number: 38-08039 Rev. *J
Page 23 of 72
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CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin
TQFP TQFP SSOP
124
98
3
56-pin
QFN
Name
Type
Default
52
PD7 or
FD[15]
I/O/Z
I (PD7) Multiplexed pin whose function is selected by
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Description
the
Port E
108
86
PE0 or
T0OUT
I/O/Z
I (PE0) Multiplexed pin whose function is selected by the PORTECFG.0
bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active HIGH signal from 8051 Timer-counter0.
T0OUT outputs a high level for one CLKOUT clock cycle when
Timer0 overflows. If Timer0 is operated in Mode 3 (two separate
timer/counters), T0OUT is active when the low byte
timer/counter overflows.
109
87
PE1 or
T1OUT
I/O/Z
I (PE1) Multiplexed pin whose function is selected by the PORTECFG.1
bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active HIGH signal from 8051 Timer-counter1.
T1OUT outputs a high level for one CLKOUT clock cycle when
Timer1 overflows. If Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte
timer/counter overflows.
110
88
PE2 or
T2OUT
I/O/Z
I (PE2) Multiplexed pin whose function is selected by the PORTECFG.2
bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active HIGH output signal from 8051 Timer2.
T2OUT is active (HIGH) for one clock cycle when
Timer/Counter 2 overflows.
111
89
PE3 or
RXD0OUT
I/O/Z
I (PE3) Multiplexed pin whose function is selected by the PORTECFG.3
bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active HIGH signal from 8051 UART0. If
RXD0OUT is selected and UART0 is in Mode 0, this pin
provides the output data for UART0 only when it is in sync
mode. Otherwise it is a 1.
112
90
PE4 or
RXD1OUT
I/O/Z
I (PE4) Multiplexed pin whose function is selected by the PORTECFG.4
bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active HIGH output from 8051 UART1. When
the RXD1OUT is selected and UART1 is in Mode 0, this pin
provides the output data for UART1 only when it is in sync
mode. In Modes 1, 2, and 3, this pin is HIGH.
113
91
PE5 or
INT6
I/O/Z
I (PE5) Multiplexed pin whose function is selected by the PORTECFG.5
bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input signal. The INT6
pin is edge-sensitive, active HIGH.
114
92
PE6 or
T2EX
I/O/Z
I (PE6) Multiplexed pin whose function is selected by the PORTECFG.6
bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active HIGH input signal to the 8051 Timer2. T2EX
reloads timer 2 on its falling edge. T2EX is active only if the
EXEN2 bit is set in T2CON.
115
93
PE7 or
GPIFADR8
I/O/Z
I (PE7) Multiplexed pin whose function is selected by the PORTECFG.7
bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
Document Number: 38-08039 Rev. *J
Page 24 of 72
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CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin
TQFP TQFP SSOP
56-pin
QFN
Name
Type
Default
Description
4
3
8
1
RDY0 or
SLRD
Input
N/A
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7..0]
or FD[15..0].
5
4
9
2
RDY1 or
SLWR
Input
N/A
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7..0]
or FD[15..0].
6
5
RDY2
Input
N/A
RDY2 is a GPIF input signal.
7
6
RDY3
Input
N/A
RDY3 is a GPIF input signal.
8
7
RDY4
Input
N/A
RDY4 is a GPIF input signal.
9
8
RDY5
Input
N/A
69
54
36
29
CTL0 or
FLAGA
O/Z
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag
signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
RDY5 is a GPIF input signal.
70
55
37
30
CTL1 or
FLAGB
O/Z
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag
signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0]
pins.
71
56
38
31
CTL2 or
FLAGC
O/Z
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag
signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0]
pins.
66
51
CTL3
O/Z
H
CTL3 is a GPIF control output.
67
52
CTL4
Output
H
CTL4 is a GPIF control output.
98
76
32
26
28
106
CTL5
Output
H
CTL5 is a GPIF control output.
IFCLK
I/O/Z
Z
Interface Clock, used for synchronously clocking data into or
out of the slave FIFOs. IFCLK also serves as a timing reference
for all slave FIFO control signals and GPIF. When internal
clocking is used (IFCONFIG.7 = 1) the IFCLK pin is configured
to output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6.
IFCLK may be inverted, whether internally or externally
sourced, by setting the bit IFCONFIG.4 = 1.
22
INT4
Input
N/A
INT4 is the 8051 INT4 interrupt request input signal. The INT4
pin is edge-sensitive, active HIGH.
84
INT5#
Input
N/A
INT5# is the 8051 INT5 interrupt request input signal. The INT5
pin is edge-sensitive, active LOW.
20
13
Document Number: 38-08039 Rev. *J
Page 25 of 72
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CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin
TQFP TQFP SSOP
56-pin
QFN
Name
Type
Default
Description
31
25
T2
Input
N/A
T2 is the active-HIGH T2 input signal to 8051 Timer2, which
provides the input to Timer2 when C/T2 = 1. When C/T2 = 0,
Timer2 does not use this pin.
30
24
T1
Input
N/A
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides
the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1
does not use this bit.
29
23
T0
Input
N/A
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides
the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0
does not use this bit.
53
43
RXD1
Input
N/A
RXD1 is an active-HIGH input signal for 8051 UART1, which
provides data to the UART in all modes.
52
42
TXD1
Output
H
TXD1 is an active-HIGH output pin from 8051 UART1, which
provides the output clock in sync mode, and the output data in
async mode.
51
41
RXD0
Input
N/A
RXD0 is the active-HIGH RXD0 input to 8051 UART0, which
provides data to the UART in all modes.
50
40
TXD0
Output
H
TXD0 is the active-HIGH TXD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in
async mode.
CS#
Output
H
CS# is the active-LOW chip select for external memory.
41
32
WR#
Output
H
WR# is the active-LOW write strobe output for external memory.
40
31
42
38
RD#
Output
H
RD# is the active-LOW read strobe output for external memory.
OE#
Output
H
OE# is the active LOW output enable for external memory.
33
27
21
14
Reserved
Input
N/A
Reserved. Connect to ground.
101
79
51
44
WAKEUP
Input
N/A
USB Wakeup. If the 8051 is in suspend, asserting this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the
suspend mode. Holding WAKEUP asserted inhibits the
EZ-USB FX1 chip from suspending. This pin has
programmable polarity (WAKEUP.4).
36
29
22
15
SCL
OD
Z
Clock for the I2C interface. Connect to VCC with a 2.2K
resistor, even if no I2C peripheral is attached.
37
30
23
16
SDA
OD
Z
Data for I2C interface. Connect to VCC with a 2.2K resistor,
even if no I2C peripheral is attached.
2
1
6
55
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
26
20
18
11
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
43
33
24
17
48
38
64
49
68
53
34
27
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
81
66
39
32
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
100
78
50
43
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
107
85
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
3
2
7
56
GND
Ground
N/A
Ground.
27
21
19
12
GND
Ground
N/A
Ground.
Document Number: 38-08039 Rev. *J
Page 26 of 72
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CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin
TQFP TQFP SSOP
49
56-pin
QFN
39
Name
Type
Default
GND
Ground
N/A
Description
Ground.
58
48
33
26
GND
Ground
N/A
Ground.
65
50
35
28
GND
Ground
N/A
Ground.
48
41
4
53
80
65
93
75
116
94
125
99
14
13
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
NC
N/A
N/A
No Connect. This pin must be left open.
15
14
NC
N/A
N/A
No Connect. This pin must be left open.
16
15
NC
N/A
N/A
No Connect. This pin must be left open.
Document Number: 38-08039 Rev. *J
Page 27 of 72
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CY7C64713
Register Summary
FX1 register bit definitions are described in the EZ-USB TRM in greater detail.
Table 9. FX1 Register Summary
Hex Size
Name
Description
b7
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF
D7
Waveform
Descriptor 0,
1, 2, 3 data
E480 128 reserved
GENERAL CONFIGURATION
E600 1 CPUCS
CPU Control
0
& Status
E601 1 IFCONFIG
Interface
IFCLKSRC
Configuration
(Ports, GPIF,
slave FIFOs)
E602 1 PINFLAGSAB[7]
Slave FIFO
FLAGB3
FLAGA and
FLAGB Pin
Configuration
E603 1 PINFLAGSCD[7]
Slave FIFO
FLAGD3
FLAGC and
FLAGD Pin
Configuration
E604 1 FIFORESET[7]
Restore
NAKALL
FIFOS to
default state
E605 1 BREAKPT
Breakpoint
0
Control
E606 1 BPADDRH
Breakpoint
A15
Address H
E607 1 BPADDRL
Breakpoint
A7
Address L
E608 1 UART230
230 Kbaud
0
internally
generated ref.
clock
E609 1 FIFOPINPOLAR[7]
Slave FIFO
0
Interface pins
polarity
E60A 1 REVID
Chip Revision
rv7
E60B
1
REVCTL[7]
Chip Revision
Control
0
b6
b5
b4
b3
b2
b1
b0
Default Access
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
CLKSPD0
CLKINV
CLKOE
8051RES
0
PORTCSTB CLKSPD1
RW
00000010 rrbbbbbr
3048MHZ
IFCLKOE
IFCLKPOL
ASYNC
GSTATE
IFCFG1
IFCFG0
10000000
RW
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
00000000
RW
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
00000000
RW
0
0
0
EP3
EP2
EP1
EP0
xxxxxxxx
W
0
0
0
BREAK
BPPULSE
BPEN
0
A14
A13
A12
A11
A10
A9
A8
xxxxxxxx
RW
A6
A5
A4
A3
A2
A1
A0
xxxxxxxx
RW
0
0
0
0
0
230UART1
0
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000 rrbbbbbb
rv6
rv5
rv4
rv3
rv2
rv1
rv0
0
0
0
0
0
dyn_out
enh_pkt
RevA
R
00000001
00000000 rrrrrrbb
00000000 rrrrbbbr
230UART0 00000000 rrrrrrbb
Note
7. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 28 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
E60C
1
3
E610
1
E611
1
E612
1
E613
1
E614
1
E615
1
E618
2
1
E619
1
E61A
1
E61B
1
E61C
E620
4
1
E621
1
Name
UDMA
GPIFHOLDAMOUNT
Description
MSTB Hold
Time (for
UDMA)
reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
Endpoint
1-OUT
Configuration
EP1INCFG
Endpoint 1-IN
Configuration
EP2CFG
Endpoint 2
Configuration
EP4CFG
Endpoint 4
Configuration
EP6CFG
Endpoint 6
Configuration
EP8CFG
Endpoint 8
Configuration
reserved
EP2FIFOCFG[8]
Endpoint 2 /
slave FIFO
configuration
EP4FIFOCFG[8]
Endpoint 4 /
slave FIFO
configuration
EP6FIFOCFG[8]
Endpoint 6 /
slave FIFO
configuration
EP8FIFOCFG[8]
Endpoint 8 /
slave FIFO
configuration
reserved
EP2AUTOINLENH[8]
Endpoint 2
AUTOIN
Packet
Length H
EP2AUTOINLENL[8]
Endpoint 2
AUTOIN
Packet
Length L
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
0
0
0
0
0
0
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
VALID
DIR
TYPE1
TYPE0
SIZE
0
BUF1
BUF0
10100010 bbbbbrbb
VALID
DIR
TYPE1
TYPE0
0
0
0
0
10100000 bbbbrrrr
VALID
DIR
TYPE1
TYPE0
SIZE
0
BUF1
BUF0
11100010 bbbbbrbb
VALID
DIR
TYPE1
TYPE0
0
0
0
0
11100000 bbbbrrrr
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
RW
Note
8. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 29 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E622
1
EP4AUTOINLENH[9]
E623
1
EP4AUTOINLENL[9]
E624
1
EP6AUTOINLENH[9]
E625
1
EP6AUTOINLENL[9]
E626
1
EP8AUTOINLENH[9]
E627
1
EP8AUTOINLENL[9]
E628
1
ECCCFG
E629
E62A
1
1
ECCRESET
ECC1B0
E62B
1
ECC1B1
E62C
1
ECC1B2
E62D
1
ECC2B0
E62E
1
ECC2B1
E62F
1
ECC2B2
Description
b7
b6
b5
b4
b3
b2
b1
b0
Endpoint 4
AUTOIN
Packet
Length H
Endpoint 4
AUTOIN
Packet
Length L
Endpoint 6
AUTOIN
Packet
Length H
Endpoint 6
AUTOIN
Packet
Length L
Endpoint 8
AUTOIN
Packet
Length H
Endpoint 8
AUTOIN
Packet
Length L
ECC Configuration
ECC Reset
ECC1 Byte 0
Address
ECC1 Byte 1
Address
ECC1 Byte 2
Address
ECC2 Byte 0
Address
ECC2 Byte 1
Address
ECC2 Byte 2
Address
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
Default Access
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
0
0
0
0
0
0
0
ECCM
00000000 rrrrrrrb
x
LINE15
x
LINE14
x
LINE13
x
LINE12
x
LINE11
x
LINE10
x
LINE9
x
LINE8
00000000
11111111
W
R
LINE7
LINE6
LINE5
LINE4
LINE3
LINE2
LINE1
LINE0
11111111
R
COL5
COL4
COL3
COL2
COL1
COL0
LINE17
LINE16
11111111
R
LINE15
LINE14
LINE13
LINE12
LINE11
LINE10
LINE9
LINE8
11111111
R
LINE7
LINE6
LINE5
LINE4
LINE3
LINE2
LINE1
LINE0
11111111
R
COL5
COL4
COL3
COL2
COL1
COL0
0
0
11111111
R
RW
RW
RW
Note
9. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 30 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
Endpoint 2 /
slave FIFO
Programmable
Flag H ISO
Mode
Endpoint 2 /
slave FIFO
Programmable
Flag H
Non-ISO Mode
DECIS
PKTSTAT
DECIS
PKTSTAT
E630
1
EP2FIFOPFH[10]
E630
1
EP2FIFOPFH[10]
E631
1
EP2FIFOPFL[10]
Endpoint 2 /
IN:PKTS[1] IN:PKTS[0]
slave FIFO
OUT:PFC7 OUT:PFC6
Programmable
Flag L
E632
1
EP4FIFOPFH[10]
E632
1
EP4FIFOPFH[10]
Endpoint 4 /
slave FIFO
Programmable
Flag H ISO
Mode
Endpoint 4 /
slave FIFO
Programmable
Flag H
Non-ISO Mode
E633
1
EP4FIFOPFL[10]
Endpoint 4 /
IN: PKTS[1] IN: PKTS[0]
slave FIFO
OUT:PFC7 OUT:PFC6
Programmable
Flag L
E634
1
EP6FIFOPFH[10]
E634
1
EP6FIFOPFH[10]
Endpoint 6 /
slave FIFO
Programmable
Flag H ISO
Mode
Endpoint 6 /
slave FIFO
Programmable
Flag H
Non-ISO Mode
b5
b2
b1
b0
Default Access
IN: PKTS[2] IN: PKTS[1] IN: PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
0
PFC9
PFC8
10001000 bbbbbrbb
OUT:PFC12 OUT:PFC11 OUT:PFC10
0
PFC9
PFC2
PFC1
PFC0
00000000
PFC5
b4
PFC4
b3
PFC3
IN:PKTS[2] 10001000 bbbbbrbb
OUT:PFC8
RW
DECIS
PKTSTAT
0
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
0
0
PFC8
10001000 bbrbbrrb
DECIS
PKTSTAT
0
OUT:PFC10 OUT:PFC9
0
0
PFC8
10001000 bbrbbrrb
PFC2
PFC1
PFC0
00000000
PFC8
00001000 bbbbbrbb
PFC5
PFC4
PFC3
DECIS
PKTSTAT
INPKTS[2] IN: PKTS[1] IN: PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
0
PFC9
DECIS
PKTSTAT
OUT:PFC12 OUT:PFC11 OUT:PFC10
0
PFC9
RW
IN:PKTS[2] 00001000 bbbbbrbb
OUT:PFC8
Note
10. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 31 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
E635
1
EP6FIFOPFL[11]
Endpoint 6 /
IN:PKTS[1] IN:PKTS[0]
slave FIFO
OUT:PFC7 OUT:PFC6
Programmable
Flag L
E636
1
EP8FIFOPFH[11]
E636
1
EP8FIFOPFH[11]
Endpoint 8 /
slave FIFO
Programmable
Flag H ISO
Mode
Endpoint 8 /
slave FIFO
Programmable
Flag H
Non-ISO Mode
E637
1
EP8FIFOPFL[11] ISO
Mode
E637
1
EP8FIFOPFL[11]
Non-ISO Mode
E640
E641
E642
E643
E644
E648
8
1
1
1
1
4
1
reserved
reserved
reserved
reserved
reserved
reserved
INPKTEND[11]
E649
7
OUTPKTEND[11]
E650
1
INTERRUPTS
EP2FIFOIE[13]
Endpoint 2
slave FIFO
Flag Interrupt
Enable
b4
b3
b2
b1
b0
Default Access
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
DECIS
PKTSTAT
0
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
0
0
PFC8
00001000 bbrbbrrb
DECIS
PKTSTAT
0
OUT:PFC10 OUT:PFC9
0
0
PFC8
00001000 bbrbbrrb
Endpoint 8 /
PFC7
PFC6
slave FIFO
Programmable
Flag L
Endpoint 8 /
IN: PKTS[1] IN: PKTS[0]
slave FIFO
OUT:PFC7 OUT:PFC6
Programmable
Flag L
Force IN
Packet End
Force OUT
Packet End
b5
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
Skip
0
0
0
EP3
EP2
EP1
EP0
xxxxxxxx
W
Skip
0
0
0
EP3
EP2
EP1
EP0
xxxxxxxx
W
0
0
0
0
EDGEPF
PF
EF
FF
00000000
RW
Note
11. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 32 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E651
1
EP2FIFOIRQ[12, 13]
E652
1
EP4FIFOIE[13]
E653
1
EP4FIFOIRQ[12, 13]
E654
1
EP6FIFOIE[13]
E655
1
EP6FIFOIRQ[14, 15]
E656
1
EP8FIFOIE[15]
E657
1
EP8FIFOIRQ[12, 13]
E658
1
IBNIE
E659
1
IBNIRQ[12]
E65A
1
NAKIE
E65B
1
NAKIRQ[12]
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
Endpoint 2
slave FIFO
Flag Interrupt
Request
Endpoint 4
slave FIFO
Flag Interrupt
Enable
Endpoint 4
slave FIFO
Flag Interrupt
Request
Endpoint 6
slave FIFO
Flag Interrupt
Enable
Endpoint 6
slave FIFO
Flag Interrupt
Request
Endpoint 8
slave FIFO
Flag Interrupt
Enable
Endpoint 8
slave FIFO
Flag Interrupt
Request
IN-BULK-NA
K Interrupt
Enable
IN-BULK-NA
K interrupt
Request
Endpoint
Ping-NAK /
IBN Interrupt
Enable
Endpoint
Ping-NAK /
IBN Interrupt
Request
0
0
0
0
0
PF
EF
FF
00000111 rrrrrbbb
0
0
0
0
EDGEPF
PF
EF
FF
00000000
0
0
0
0
0
PF
EF
FF
00000111 rrrrrbbb
0
0
0
0
EDGEPF
PF
EF
FF
00000000
0
0
0
0
0
PF
EF
FF
00000110 rrrrrbbb
0
0
0
0
EDGEPF
PF
EF
FF
00000000
0
0
0
0
0
PF
EF
FF
00000110 rrrrrbbb
0
0
EP8
EP6
EP4
EP2
EP1
EP0
00000000
0
0
EP8
EP6
EP4
EP2
EP1
EP0
00xxxxxx rrbbbbbb
EP8
EP6
EP4
EP2
EP1
EP0
0
IBN
00000000
EP8
EP6
EP4
EP2
EP1
EP0
0
IBN
xxxxxx0x bbbbbbrb
RW
RW
RW
RW
RW
Notes
12. SFRs not part of the standard 8051 architecture.
13. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 33 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E65C
1
USBIE
E65D
1
USBIRQ[14]
E65E
1
EPIE
E65F
1
EPIRQ[14]
E660
1
GPIFIE[15]
E661
1
GPIFIRQ[15]
E662
1
USBERRIE
E663
1
USBERRIRQ[14]
E664
1
ERRCNTLIM
E665
1
CLRERRCNT
E666
1
INT2IVEC
E667
1
INT4IVEC
E668
1
INTSETUP
E669
7
E670
1
reserved
INPUT / OUTPUT
PORTACFG
Description
b7
b6
b5
b4
b3
b2
b1
b0
USB Int
Enables
USB Interrupt
Requests
Endpoint
Interrupt
Enables
Endpoint
Interrupt
Requests
GPIF Interrupt
Enable
GPIF Interrupt
Request
USB Error
Interrupt
Enables
USB Error
Interrupt
Requests
USB Error
counter and
limit
Clear Error
Counter
EC3:0
Interrupt 2
(USB)
Autovector
Interrupt 4
(slave FIFO &
GPIF)
Autovector
Interrupt 2 & 4
setup
0
EP0ACK
0
URES
SUSP
SUTOK
SOF
SUDAV
00000000
0
EP0ACK
0
URES
SUSP
SUTOK
SOF
SUDAV
0xxxxxxx rbbbbbbb
EP8
EP6
EP4
EP2
EP1OUT
EP1IN
EP0OUT
EP0IN
00000000
RW
EP8
EP6
EP4
EP2
EP1OUT
EP1IN
EP0OUT
EP0IN
0
RW
0
0
0
0
0
0
GPIFWF
GPIFDONE 00000000
RW
0
0
0
0
0
0
GPIFWF
GPIFDONE 000000xx
RW
ISOEP8
ISOEP6
ISOEP4
ISOEP2
0
0
0
ERRLIMIT 00000000
RW
ISOEP8
ISOEP6
ISOEP4
ISOEP2
0
0
0
ERRLIMIT 0000000x bbbbrrrb
EC3
EC2
EC1
EC0
LIMIT3
LIMIT2
LIMIT1
LIMIT0
x
x
x
x
x
x
x
x
xxxxxxxx
W
0
I2V4
I2V3
I2V2
I2V1
I2V0
0
0
00000000
R
1
0
I4V3
I4V2
I4V1
I4V0
0
0
10000000
R
0
0
0
0
AV2EN
0
INT4SRC
AV4EN
00000000
RW
FLAGD
SLCS
0
0
0
0
INT1
INT0
00000000
RW
I/O PORTA
Alternate
Configuration
Default Access
RW
xxxx0100 rrrrbbbb
Notes
14. SFRs not part of the standard 8051 architecture.
15. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 34 of 72
[+] Feedback
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E671
1
PORTCCFG
E672
1
PORTECFG
E673
4
XTALINSRC
E677
E678
1
1
reserved
I2CS
E679
E67A
1
1
I2DAT
I2CTL
E67B
1
XAUTODAT1
E67C
1
XAUTODAT2
E67D
1
UDMA CRC
UDMACRCH[16]
E67E
1
E67F
1
E680
1
E681
1
E682
1
E683
1
E684
1
Description
b7
b6
b5
b4
b3
b2
b1
b0
I/O PORTC
Alternate
Configuration
I/O PORTE
Alternate
Configuration
XTALIN Clock
Source
GPIFA7
GPIFA6
GPIFA5
GPIFA4
GPIFA3
GPIFA2
GPIFA1
GPIFA0
00000000
RW
GPIFA8
T2EX
INT6
RXD1OUT
RXD0OUT
T2OUT
T1OUT
T0OUT
00000000
RW
0
0
0
0
0
0
0
EXTCLK
00000000 rrrrrrrb
I²C Bus
Control &
Status
I²C Bus Data
I²C Bus
Control
Autoptr1
MOVX
access, when
APTREN = 1
Autoptr2
MOVX
access, when
APTREN = 1
START
STOP
LASTRD
ID1
ID0
BERR
ACK
DONE
000xx000 bbbrrrrr
d7
0
d6
0
d5
0
d4
0
d3
0
d2
0
d1
STOPIE
d0
400KHZ
xxxxxxxx
00000000
RW
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
CRC15
CRC14
CRC13
CRC12
CRC11
CRC10
CRC9
CRC8
01001010
RW
CRC7
CRC6
CRC5
CRC4
CRC3
CRC2
CRC1
CRC0
10111010
RW
QENABLE
0
0
0
QSTATE
QSIGNAL2
QSIGNAL1
QSIGNAL0 00000000 brrrbbbb
0
0
0
0
DISCON
NOSYNSOF
RENUM
SIGRSUME x0000000 rrrrbbbb
x
x
x
x
x
x
x
x
WU2
WU
WU2POL
WUPOL
0
DPEN
WU2EN
WUEN
xx000101 bbbbrbbb
Q
S
R
I/O
EP3
EP2
EP1
EP0
x0000000 rrrbbbbb
0
0
0
0
0
FC10
FC9
FC8
00000xxx
UDMA CRC
MSB
UDMACRCL[16]
UDMA CRC
LSB
UDMACRC-QUALIFIER UDMA CRC
Qualifier
USB CONTROL
USBCS
USB Control
& Status
SUSPEND
Put chip into
suspend
WAKEUPCS
Wakeup
Control &
Status
TOGCTL
Toggle
Control
USBFRAMEH
USB Frame
count H
Default Access
xxxxxxxx
W
R
Note
16. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 35 of 72
[+] Feedback
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E685
1
USBFRAMEL
E686
E687
1
1
reserved
FNADDR
E688
2
E68A
1
reserved
ENDPOINTS
EP0BCH[17]
E68B
1
EP0BCL[17]
E68C
E68D
1
1
reserved
EP1OUTBC
E68E
E68F
1
1
reserved
EP1INBC
E690
1
EP2BCH[17]
E691
1
EP2BCL[17]
E692
E694
2
1
reserved
EP4BCH[17]
E695
1
EP4BCL[17]
E696
E698
2
1
reserved
EP6BCH[17]
E699
1
EP6BCL[17]
E69A
E69C
2
1
reserved
EP8BCH[17]
E69D
1
EP8BCL[17]
E69E
2
reserved
Description
b7
b6
b5
b4
b3
b2
b1
b0
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
xxxxxxxx
R
USB Function
address
0
FA6
FA5
FA4
FA3
FA2
FA1
FA0
0xxxxxxx
R
Endpoint 0
Byte Count H
Endpoint 0
Byte Count L
(BC15)
(BC14)
(BC13)
(BC12)
(BC11)
(BC10)
(BC9)
(BC8)
xxxxxxxx
RW
(BC7)
BC6
BC5
BC4
BC3
BC2
BC1
BC0
xxxxxxxx
RW
Endpoint 1
OUT Byte
Count
0
BC6
BC5
BC4
BC3
BC2
BC1
BC0
xxxxxxxx
RW
Endpoint 1 IN
Byte Count
Endpoint 2
Byte Count H
Endpoint 2
Byte Count L
0
BC6
BC5
BC4
BC3
BC2
BC1
BC0
xxxxxxxx
RW
0
0
0
0
0
BC10
BC9
BC8
xxxxxxxx
RW
BC7/SKIP
BC6
BC5
BC4
BC3
BC2
BC1
BC0
xxxxxxxx
RW
0
0
0
0
0
0
BC9
BC8
xxxxxxxx
RW
BC7/SKIP
BC6
BC5
BC4
BC3
BC2
BC1
BC0
xxxxxxxx
RW
0
0
0
0
0
BC10
BC9
BC8
xxxxxxxx
RW
BC7/SKIP
BC6
BC5
BC4
BC3
BC2
BC1
BC0
xxxxxxxx
RW
0
0
0
0
0
0
BC9
BC8
xxxxxxxx
RW
BC7/SKIP
BC6
BC5
BC4
BC3
BC2
BC1
BC0
xxxxxxxx
RW
USB Frame
count L
Endpoint 4
Byte Count H
Endpoint 4
Byte Count L
Endpoint 6
Byte Count H
Endpoint 6
Byte Count L
Endpoint 8
Byte Count H
Endpoint 8
Byte Count L
Default Access
Note
17. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 36 of 72
[+] Feedback
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E6A0
1
EP0CS
E6A1
1
EP1OUTCS
E6A2
1
EP1INCS
E6A3
1
EP2CS
E6A4
1
EP4CS
E6A5
1
EP6CS
E6A6
1
EP8CS
E6A7
1
EP2FIFOFLGS
E6A8
1
EP4FIFOFLGS
E6A9
1
EP6FIFOFLGS
E6AA
1
EP8FIFOFLGS
E6AB
1
EP2FIFOBCH
E6AC
1
EP2FIFOBCL
E6AD
1
EP4FIFOBCH
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
Endpoint 0
Control and
Status
Endpoint 1
OUT Control
and Status
Endpoint 1 IN
Control and
Status
Endpoint 2
Control and
Status
Endpoint 4
Control and
Status
Endpoint 6
Control and
Status
Endpoint 8
Control and
Status
Endpoint 2
slave FIFO
Flags
Endpoint 4
slave FIFO
Flags
Endpoint 6
slave FIFO
Flags
Endpoint 8
slave FIFO
Flags
Endpoint 2
slave FIFO
total byte
count H
Endpoint 2
slave FIFO
total byte
count L
Endpoint 4
slave FIFO
total byte
count H
HSNAK
0
0
0
0
0
BUSY
STALL
10000000 bbbbbbrb
0
0
0
0
0
0
BUSY
STALL
00000000 bbbbbbrb
0
0
0
0
0
0
BUSY
STALL
00000000 bbbbbbrb
0
NPAK2
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00101000 rrrrrrrb
0
0
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00101000 rrrrrrrb
0
NPAK2
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00000100 rrrrrrrb
0
0
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00000100 rrrrrrrb
0
0
0
0
0
PF
EF
FF
00000010
R
0
0
0
0
0
PF
EF
FF
00000010
R
0
0
0
0
0
PF
EF
FF
00000110
R
0
0
0
0
0
PF
EF
FF
00000110
R
0
0
0
BC12
BC11
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
0
0
0
0
0
BC10
BC9
BC8
00000000
R
Document Number: 38-08039 Rev. *J
Page 37 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E6AE
1
EP4FIFOBCL
E6AF
1
EP6FIFOBCH
E6B0
1
EP6FIFOBCL
E6B1
1
EP8FIFOBCH
E6B2
1
EP8FIFOBCL
E6B3
1
SUDPTRH
E6B4
1
SUDPTRL
E6B5
1
SUDPTRCTL
E6B8
2
8
reserved
SETUPDAT
Description
b7
b6
b5
b4
b3
b2
b1
b0
Endpoint 4
slave FIFO
total byte
count L
Endpoint 6
slave FIFO
total byte
count H
Endpoint 6
slave FIFO
total byte
count L
Endpoint 8
slave FIFO
total byte
count H
Endpoint 8
slave FIFO
total byte
count L
Setup Data
Pointer high
address byte
Setup Data
Pointer low
address byte
Setup Data
Pointer Auto
Mode
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
0
0
0
0
BC11
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
0
0
0
0
0
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
A15
A14
A13
A12
A11
A10
A9
A8
xxxxxxxx
RW
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
FIFOWR0
FIFORD1
FIFORD0
11100100
RW
8 bytes of
setup data
Default Access
xxxxxxx0 bbbbbbbr
SDPAUTO 00000001
RW
SETUPDAT[0]
=
bmRequestTy
pe
SETUPDAT[1]
= bmRequest
SETUPDAT[2:
3] = wValue
SETUPDAT[4:
5] = wIndex
SETUPDAT[6:
7] = wLength
E6C0
1
GPIF
GPIFWFSELECT
Waveform
Selector
Document Number: 38-08039 Rev. *J
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1
Page 38 of 72
[+] Feedback
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E6C1
1
GPIFIDLECS
E6C2
1
GPIFIDLECTL
E6C3
1
GPIFCTLCFG
E6C4
1
GPIFADRH[18]
E6C5
1
GPIFADRL[18]
E6C6
1
FLOWSTATE
FLOWSTATE
E6C7
1
FLOWLOGIC
E6C8
1
FLOWEQ0CTL
E6C9
1
FLOWEQ1CTL
E6CA
1
FLOWHOLDOFF
E6CB
1
FLOWSTB
E6CC
1
FLOWSTBEDGE
E6CD
1
FLOWSTBPERIOD
E6CE
1
GPIFTCB3[18]
E6CF
1
GPIFTCB2[18]
Description
b7
b6
b5
b4
b3
b2
b1
b0
GPIF Done,
GPIF IDLE
drive mode
Inactive Bus,
CTL states
CTL Drive
Type
GPIF Address
H
GPIF Address
L
DONE
0
0
0
0
0
0
IDLEDRV
10000000
RW
0
0
CTL5
CTL4
CTL3
CTL2
CTL1
CTL0
11111111
RW
TRICTL
0
CTL5
CTL4
CTL3
CTL2
CTL1
CTL0
00000000
RW
0
0
0
0
0
0
0
GPIFA8
00000000
RW
GPIFA7
GPIFA6
GPIFA5
GPIFA4
GPIFA3
GPIFA2
GPIFA1
GPIFA0
00000000
RW
FS2
FS1
FS0
TERMB2
TERMB1
TERMB0
00000000
RW
CTL2
CTL1
CTL0
00000000
RW
CTL2
CTL1
CTL0
00000000
RW
HOCTL2
HOCTL1
HOCTL0
00000000
RW
MSTB2
MSTB1
MSTB0
00100000
RW
0
FALLING
RISING
00000001 rrrrrrbb
D2
D1
D0
00000010
RW
Flowstate
FSE
0
0
0
0
Enable and
Selector
Flowstate
LFUNC1
LFUNC0
TERMA2
TERMA1
TERMA0
Logic
CTL-Pin
CTL0E3
CTL0E2 CTL0E1/CTL5 CTL0E0/CTL4
CTL3
States in
Flowstate
(when
Logic = 0)
CTL-Pin
CTL0E3
CTL0E2 CTL0E1/CTL5 CTL0E0/CTL4
CTL3
States in
Flowstate
(when
Logic = 1)
HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE
Holdoff
Configuration
Flowstate
SLAVE
RDYASYNC CTLTOGL SUSTAIN
0
Strobe
Configuration
Flowstate
0
0
0
0
0
Rising/Falling
Edge
Configuration
Master-Strobe
D7
D6
D5
D4
D3
Half-Period
GPIF
Transaction
Count Byte 3
GPIF
Transaction
Count Byte 2
Default Access
00000000 brrrrbbb
TC31
TC30
TC29
TC28
TC27
TC26
TC25
TC24
00000000
RW
TC23
TC22
TC21
TC20
TC19
TC18
TC17
TC16
00000000
RW
Note
18. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 39 of 72
[+] Feedback
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E6D0
1
GPIFTCB1[19]
E6D1
1
GPIFTCB0[19]
2
E6D2
1
reserved
reserved
reserved
EP2GPIFFLGSEL[19]
E6D3
1
EP2GPIFPFSTOP
E6D4
1
EP2GPIFTRIG[19]
3
E6DA
1
reserved
reserved
reserved
EP4GPIFFLGSEL[19]
E6DB
1
EP4GPIFPFSTOP
E6DC
1
EP4GPIFTRIG[19]
3
E6E2
1
reserved
reserved
reserved
EP6GPIFFLGSEL[19]
E6E3
1
EP6GPIFPFSTOP
E6E4
1
EP6GPIFTRIG[19]
Description
b7
b6
b5
b4
b3
b2
b1
b0
GPIF
Transaction
Count Byte 1
GPIF
Transaction
Count Byte 0
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
00000000
RW
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
00000001
RW
00000000
RW
00000000
RW
FIFO2FLAG 00000000
RW
FS0
Default Access
Endpoint 2
GPIF Flag
select
Endpoint 2
GPIF stop
transaction on
prog. flag
Endpoint 2
GPIF Trigger
0
0
0
0
0
0
FS1
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
xxxxxxxx
W
Endpoint 4
GPIF Flag
select
Endpoint 4
GPIF stop
transaction on
GPIF Flag
Endpoint 4
GPIF Trigger
0
0
0
0
0
0
FS1
FS0
00000000
RW
0
0
0
0
0
0
0
FIFO4FLAG 00000000
RW
x
x
x
x
x
x
x
x
xxxxxxxx
W
Endpoint 6
GPIF Flag
select
Endpoint 6
GPIF stop
transaction on
prog. flag
Endpoint 6
GPIF Trigger
0
0
0
0
0
0
FS1
FS0
00000000
RW
0
0
0
0
0
0
0
FIFO6FLAG 00000000
RW
x
x
x
x
x
x
x
x
xxxxxxxx
W
Note
19. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 40 of 72
[+] Feedback
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
3
Name
E6EA
1
reserved
reserved
reserved
EP8GPIFFLGSEL[20]
E6EB
1
EP8GPIFPFSTOP
E6EC
1
EP8GPIFTRIG[20]
E6F0
3
1
reserved
XGPIFSGLDATH
E6F1
1
XGPIFSGLDATLX
E6F2
1
XGPIFSGLDATLNOX
E6F3
1
GPIFREADYCFG
E6F4
1
GPIFREADYSTAT
E6F5
1
GPIFABORT
E6F6
2
E740
reserved
ENDPOINT BUFFERS
64 EP0BUF
E780
64 EP10UTBUF
E7C0 64 EP1INBUF
2048 reserved
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
Endpoint 8
GPIF Flag
select
Endpoint 8
GPIF stop
transaction on
prog. flag
Endpoint 8
GPIF Trigger
0
0
0
0
0
0
FS1
FS0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
xxxxxxxx
W
GPIF Data H
(16-bit mode
only)
Read/Write
GPIF Data L &
trigger
transaction
Read GPIF
Data L, no
transaction
trigger
Internal RDY,
Sync/Async,
RDY pin
states
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
INTRDY
SAS
TCXRDY5
0
0
0
0
0
GPIF Ready
Status
Abort GPIF
Waveforms
0
0
RDY5
RDY4
RDY3
RDY2
RDY1
RDY0
00xxxxxx
R
x
x
x
x
x
x
x
x
xxxxxxxx
W
EP0-IN/-OUT
buffer
EP1-OUT
buffer
EP1-IN buffer
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
RW
00000000
RW
FIFO8FLAG 00000000
RW
00000000 bbbrrrrr
Note
20. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 41 of 72
[+] Feedback
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
F000 1023 EP2FIFOBUF
F400
64 EP4FIFOBUF
F600 64 reserved
F800 1023 EP6FIFOBUF
FC00 64 EP8FIFOBUF
FE00
xxxx
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
64/1023-byte
EP 2 / slave
FIFO buffer
(IN or OUT)
64 byte EP 4 /
slave FIFO
buffer (IN or
OUT)
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
64/1023-byte
EP 6 / slave
FIFO buffer
(IN or OUT)
64 byte EP 8 /
slave FIFO
buffer (IN or
OUT)
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
0
DISCON
0
0
0
0
0
400KHZ
xxxxxxxx[22]
n/a
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
00000111
00000000
RW
RW
A15
A14
A13
A12
A11
A10
A9
A8
00000000
RW
A7
A6
A5
A4
A3
A2
A1
A0
00000000
RW
A15
A14
A13
A12
A11
A10
A9
A8
00000000
RW
0
0
0
0
0
0
0
SEL
00000000
RW
SMOD0
TF1
x
TR1
1
TF0
1
TR0
x
IE1
x
IT1
x
IE0
IDLE
IT0
00110000
00000000
RW
RW
GATE
CT
M1
M0
GATE
CT
M1
M0
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
87
88
64 reserved
I²C Configuration Byte
Special Function Registers (SFRs)
1 IOA[21]
Port A (bit
addressable)
1 SP
Stack Pointer
1 DPL0
Data Pointer 0
L
1 DPH0
Data Pointer 0
H
1 DPL1[21]
Data Pointer 1
L
1 DPH1[21]
Data Pointer 1
H
1 DPS[21]
Data Pointer
0/1 select
1 PCON
Power Control
Timer/Counter
1 TCON
89
1
TMOD
8A
1
TL0
80
81
82
83
84
85
86
Control (bit
addressable)
Timer/Counter
Mode Control
Timer 0 reload
L
Notes
21. SFRs not part of the standard 8051 architecture.
22. If no EEPROM is detected by the SIE then the default is 00000000.
Document Number: 38-08039 Rev. *J
Page 42 of 72
[+] Feedback
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
8B
1
TL1
8C
1
TH0
8D
1
TH1
8E
8F
90
1
1
1
CKCON[23]
reserved
IOB[23]
91
1
EXIF[23]
92
1
MPAGE[23]
93
98
5
1
reserved
SCON0
99
1
SBUF0
9A
1
AUTOPTRH1[23]
9B
1
AUTOPTRL1[23]
9C
9D
1
1
reserved
AUTOPTRH2[23]
9E
1
AUTOPTRL2[23]
9F
A0
1
1
reserved
IOC[23]
A1
1
INT2CLR[23]
A2
1
INT4CLR[23]
A3
5
reserved
Description
b7
b6
b5
b4
b3
b2
b1
b0
Timer 1 reload
L
Timer 0 reload
H
Timer 1 reload
H
Clock Control
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
D15
D14
D13
D12
D11
D10
D9
D8
00000000
RW
D15
D14
D13
D12
D11
D10
D9
D8
00000000
RW
x
x
T2M
T1M
T0M
MD2
MD1
MD0
00000001
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
IE5
IE4
I²CINT
USBNT
1
0
0
0
00001000
RW
A15
A14
A13
A12
A11
A10
A9
A8
00000000
RW
Serial Port 0
Control (bit
addressable)
Serial Port 0
Data Buffer
Autopointer 1
Address H
Autopointer 1
Address L
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
A15
A14
A13
A12
A11
A10
A9
A8
00000000
RW
A7
A6
A5
A4
A3
A2
A1
A0
00000000
RW
Autopointer 2
Address H
Autopointer 2
Address L
A15
A14
A13
A12
A11
A10
A9
A8
00000000
RW
A7
A6
A5
A4
A3
A2
A1
A0
00000000
RW
Port C (bit
addressable)
Interrupt 2
clear
Interrupt 4
clear
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
x
x
x
x
x
x
x
x
xxxxxxxx
W
x
x
x
x
x
x
x
x
xxxxxxxx
W
Port B (bit
addressable)
External
Interrupt
Flag(s)
Upper Addr
Byte of MOVX
using @R0 /
@R1
Default Access
Note
23. SFRs not part of the standard 8051 architecture.
Document Number: 38-08039 Rev. *J
Page 43 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
A8
1
IE
A9
AA
1
1
reserved
EP2468STAT[24]
AB
1
EP24FIFOFLGS[24]
AC
1
EP68FIFOFLGS[24]
AD
AF
2
1
reserved
AUTOPTRSETUP[24]
B0
1
IOD[23]
B1
1
IOE[24]
B2
1
OEA[24]
B3
1
OEB[24]
B4
1
OEC[24]
B5
1
OED[24]
B6
1
OEE[24]
B7
B8
1
1
reserved
IP
B9
BA
1
1
reserved
EP01STAT[24]
BB
1
GPIFTRIG[24, 25]
Description
b7
b6
b5
b4
b3
b2
b1
b0
Interrupt
Enable (bit
addressable)
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00000000
RW
Endpoint 2, 4,
6, 8 status
flags
Endpoint 2, 4
slave FIFO
status flags
Endpoint 6, 8
slave FIFO
status flags
EP8F
EP8E
EP6F
EP6E
EP4F
EP4E
EP2F
EP2E
01011010
R
0
EP4PF
EP4EF
EP4FF
0
EP2PF
EP2EF
EP2FF
00100010
R
0
EP8PF
EP8EF
EP8FF
0
EP6PF
EP6EF
EP6FF
01100110
R
Autopointer
1&2 setup
Port D (bit
addressable)
Port E
(NOT bit
addressable)
Port A Output
Enable
Port B Output
Enable
Port C Output
Enable
Port D Output
Enable
Port E Output
Enable
0
0
0
0
0
APTR2INC
APTR1INC
APTREN
00000110
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
Interrupt
Priority (bit
addressable)
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
10000000
RW
Endpoint 0&1
Status
Endpoint 2, 4,
6, 8 GPIF
slave FIFO
Trigger
0
0
0
0
0
EP0BSY
00000000
R
DONE
0
0
0
0
EP1INBSY EP1OUTBSY
RW
EP1
EP0
Default Access
10000xxx brrrrbbb
Notes
24. SFRs not part of the standard 8051 architecture.
25. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *J
Page 44 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
6
1
GPIF Data H
(16-bit mode
only)
GPIFSGLDATLX[26]
GPIF Data L
w/ Trigger
GPIFSGLDATLNOX[26] GPIF Data L
w/ No Trigger
SCON1[26]
Serial Port 1
Control (bit
addressable)
SBUF1[26]
Serial Port 1
Data Buffer
reserved
Timer/Counter
T2CON
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CT2
CPRL2
00000000
RW
C9
CA
1
1
reserved
RCAP2L
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
CB
1
RCAP2H
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
CC
1
TL2
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
CD
1
TH2
D15
D14
D13
D12
D11
D10
D9
D8
00000000
RW
CE
D0
2
1
reserved
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
00000000
RW
D1
D8
7
1
reserved
EICON[26]
SMOD1
1
ERESI
RESI
INT6
0
0
0
01000000
RW
D9
E0
7
1
reserved
ACC
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
BC
BD
1
1
BE
1
BF
1
C0
1
C1
1
C2
C8
Name
reserved
GPIFSGLDATH[26]
2 Control (bit
addressable)
Capture for
Timer 2,
auto-reload,
up-counter
Capture for
Timer 2,
auto-reload,
up-counter
Timer 2 reload
L
Timer 2 reload
H
Program
Status Word
(bit
addressable)
External
Interrupt
Control
Accumulator
(bit
addressable)
Note
26. SFRs not part of the standard 8051 architecture.
Document Number: 38-08039 Rev. *J
Page 45 of 72
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CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
E1
E8
7
1
reserved
EIE[27]
E9
F0
7
1
reserved
B
F1
F8
7
1
reserved
EIP[27]
Description
External
Interrupt
Enable(s)
B (bit
addressable)
External
Interrupt
Priority
Control
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
1
1
1
EX6
EX5
EX4
EI²C
EUSB
11100000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
1
1
1
PX6
PX5
PX4
PI²C
PUSB
11100000
RW
F9
7 reserved
Legend (For the Access column)
R = all bits read-only
W = all bits write-only
r = read-only bit
w = write-only bit
b = both read/write bit
Note
27. SFRs not part of the standard 8051 architecture.
Document Number: 38-08039 Rev. *J
Page 46 of 72
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CY7C64713
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................ –65 °C to +150 °C
Ambient Temperature with Power Supplied.... 0 °C to +70 °C
Supply Voltage to Ground Potential..............–0.5 V to +4.0 V
Max Output Current, per I/O port................................ 10 mA
Max Output Current, all five I/O ports
(128 and 100 pin packages) ....................................... 50 mA
Operating Conditions
DC Input Voltage to Any Input Pin ......................... 5.25 V[28]
TA (Ambient Temperature Under Bias) ........... 0 °C to +70 °C
DC Voltage Applied to Outputs
in High Z State ................................... –0.5 V to VCC + 0.5 V
Supply Voltage..........................................+3.15 V to +3.45 V
Power Dissipation.................................................... 235 mW
FOSC (Oscillator or Crystal Frequency).... 24 MHz ± 100 ppm
Parallel Resonant
Static Discharge Voltage......................................... > 2000 V
Ground Voltage................................................................. 0 V
DC Characteristics
Parameter
VCC
Description
Conditions
Supply Voltage
Min
Typ
Max
Unit
3.15
3.3
3.45
V
200
–
–
s
VIH
Input HIGH Voltage
2
–
5.25
V
VIL
Input LOW Voltage
–0.5
–
0.8
V
VIH_X
Crystal input HIGH Voltage
2
–
5.25
V
VIL_X
Crystal input LOW Voltage
–0.05
–
0.8
V
II
Input Leakage Current
–
–
±10
A
VOH
Output Voltage HIGH
IOUT = 4 mA
2.4
–
–
V
VOL
Output LOW Voltage
IOUT = –4 mA
–
–
0.4
V
VCC Ramp Up 0 to 3.3 V
0 < VIN < VCC
IOH
Output Current HIGH
–
–
4
mA
IOL
Output Current LOW
–
–
4
mA
CIN
Input Pin Capacitance
ISUSP
Suspend Current
Except D+/D–
–
3.29
10
pF
D+/D–
–
12.96
15
pF
Connected
–
0.5
1.2
mA
Disconnected
–
0.3
1.0
mA
ICC
Supply Current
8051 running, connected to USB
TRESET
Reset Time after Valid Power
VCC min = 3.0 V
Pin Reset after powered on
–
35
65
mA
5.0
–
–
ms
200
–
–
s
USB Transceiver
USB 2.0 compliant in full speed mode.
Note
28. It is recommended to not power I/O when chip power is off.
Document Number: 38-08039 Rev. *J
Page 47 of 72
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CY7C64713
AC Electrical Characteristics
USB Transceiver
USB 2.0 compliant in full speed mode.
Figure 12. Program Memory Read Timing Diagram
tCL
CLKOUT[29]
tAV
tAV
A[15..0]
tSTBH
tSTBL
PSEN#
[30]
tACC1
D[7..0]
tDH
data in
tSOEL
OE#
tSCSL
CS#
Table 10. Program Memory Read Parameters
Parameter
tCL
Description
1/CLKOUT Frequency
Min
Typ
Max
Unit
Notes
–
20.83
–
ns
48 MHz
–
41.66
–
ns
24 MHz
–
83.2
–
ns
12 MHz
tAV
Delay from Clock to Valid Address
0
–
10.7
ns
tSTBL
Clock to PSEN Low
0
–
8
ns
tSTBH
Clock to PSEN High
0
–
8
ns
tSOEL
Clock to OE Low
–
–
11.1
ns
tSCSL
Clock to CS Low
tDSU
Data Setup to Clock
tDH
Data Hold Time
–
–
13
ns
9.6
–
–
ns
0
–
–
ns
Notes
29. CLKOUT is shown with positive polarity.
30. tACC1 is computed from the parameters in Table 10 as follows:
tACC1(24 MHz) = 3 × tCL – tAV – tDSU = 106 ns
tACC1(48 MHz) = 3 × tCL – tAV – tDSU = 43 ns.
Document Number: 38-08039 Rev. *J
Page 48 of 72
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CY7C64713
Figure 13. Data Memory Read Timing Diagram
tCL
Stretch = 0
CLKOUT[31]
tAV
tAV
A[15..0]
tSTBH
tSTBL
RD#
tSCSL
CS#
tSOEL
OE#
tDSU
[32]
tDH
tACC1
D[7..0]
data in
tCL
Stretch = 1
CLKOUT[31]
tAV
A[15..0]
RD#
CS#
tDSU
tACC1[32]
D[7..0]
tDH
data in
Table 11. Data Memory Read Parameters
Parameter
tCL
Description
1/CLKOUT Frequency
Min
Typ
Max
Unit
Notes
–
20.83
–
ns
48 MHz
–
41.66
–
ns
24 MHz
–
83.2
–
ns
12 MHz
tAV
Delay from Clock to Valid Address
–
–
10.7
ns
tSTBL
Clock to RD LOW
–
–
11
ns
tSTBH
Clock to RD HIGH
–
–
11
ns
tSCSL
Clock to CS LOW
–
–
13
ns
tSOEL
Clock to OE LOW
tDSU
Data Setup to Clock
tDH
Data Hold Time
–
–
11.1
ns
9.6
–
–
ns
0
–
–
ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is active only when either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
Notes
31. CLKOUT is shown with positive polarity.
32. tACC2 and tACC3 are computed from the parameters in Table 11 as follows:
tACC2(24 MHz) = 3 × tCL – tAV – tDSU = 106 ns
tACC2(48 MHz) = 3 × tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5 × tCL – tAV – tDSU = 190 ns
tACC3(48 MHz) = 5 × tCL – tAV – tDSU = 86 ns.
Document Number: 38-08039 Rev. *J
Page 49 of 72
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CY7C64713
Figure 14. Data Memory Write Timing Diagram
tCL
CLKOUT
tAV
tSTBL
tSTBH
tAV
A[15..0]
WR#
tSCSL
CS#
tON1
tOFF1
data out
D[7..0]
Stretch = 1
tCL
CLKOUT
tAV
A[15..0]
WR#
CS#
tON1
tOFF1
data out
D[7..0]
Table 12. Data Memory Write Parameters
Min
Max
Unit
tAV
Parameter
Delay from Clock to Valid Address
Description
0
10.7
ns
tSTBL
Clock to WR Pulse LOW
0
11.2
ns
tSTBH
Clock to WR Pulse HIGH
0
11.2
ns
tSCSL
Clock to CS Pulse LOW
–
13.0
ns
tON1
Clock to Data Turn-on
0
13.1
ns
tOFF1
Clock to Data Hold Time
0
13.1
ns
Notes
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is active only when either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
Document Number: 38-08039 Rev. *J
Page 50 of 72
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CY7C64713
PORTC Strobe Feature Timings
The RD# and WR# are present in the 100 pin version and the
128 pin package. In these 100 pin and 128 pin versions, an 8051
control bit is set to pulse the RD# and WR# pins when the 8051
reads from or writes to the PORTC. This feature is enabled by
setting the PORTCSTB bit in CPUCS register.
The RD# and WR# strobes are asserted for two CLKOUT cycles
when the PORTC is accessed.
The WR# strobe is asserted two clock cycles after the PORTC is
updated and is active for two clock cycles after that as shown in
Figure 16.
As for read, the value of the PORTC three clock cycles before
the assertion of RD# is the value that the 8051 reads in. The RD#
is pulsed for 2 clock cycles after 3 clock cycles from the point
when the 8051 has performed a read function on PORTC.
In this feature the RD# signal prompts the external logic to
prepare the next data byte. Nothing gets sampled internally on
assertion of the RD# signal itself. It is just a “prefetch” type signal
to get the next data byte prepared. Therefore, using it meets the
set up time to the next read.
The purpose of this pulsing of RD# is to let the external peripheral
know that the 8051 is done reading PORTC and that the data
was latched into the PORTC three CLKOUT cycles prior to
asserting the RD# signal. After the RD# is pulsed the external
logic may update the data on PORTC.
The timing diagram of the read and write strobing function on
accessing PORTC follows. Refer to Figure 13 on page 49 and
Figure 14 on page 50 for details on propagation delay of RD#
and WR# signals.
Figure 16. WR# Strobe Function when PORTC is Accessed by 8051
tCLKOUT
CLKOUT
PORTC IS UPDATED
tSTBL
tSTBH
WR#
Figure 17. RD# Strobe Function when PORTC is Accessed by 8051
tCLKOUT
CLKOUT
8051 READS PORTC
DATA IS UPDATED BY EXTERNAL LOGIC
DATA MUST BE HELD FOR 3 CLK CYLCES
tSTBL
tSTBH
RD#
Document Number: 38-08039 Rev. *J
Page 51 of 72
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CY7C64713
GPIF Synchronous Signals
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 18. GPIF Synchronous Signals Timing Diagram
tIFCLK
IFCLK
tSGA
GPIFADR[8:0]
RDYX
tSRY
tRYH
DATA(input)
valid
tSGD
tDAH
CTLX
tXCTL
DATA(output)
N
N+1
tXGD
The following table provides the GPIF Synchronous Signals Parameters with Internally Sourced IFCLK. [33, 34]
Table 13. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
Parameter
Description
Min
Max
Unit
20.83
–
ns
8.9
–
ns
0
–
ns
9.2
–
ns
tIFCLK
IFCLK Period
tSRY
RDYX to Clock Setup Time
tRYH
Clock to RDYX
tSGD
GPIF Data to Clock Setup Time
tDAH
GPIF Data Hold Time
0
–
ns
tSGA
Clock to GPIF Address Propagation Delay
–
7.5
ns
tXGD
Clock to GPIF Data Output Propagation Delay
–
11
ns
tXCTL
Clock to CTLX Output Propagation Delay
–
6.7
ns
Min
Max
Unit
20.83
200
ns
The following table provides the GPIF Synchronous Signals Parameters with Externally Sourced IFCLK.[34]
Table 14. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
Parameter
Description
tIFCLK
IFCLK Period
tSRY
RDYX to Clock Setup Time
2.9
–
ns
tRYH
Clock to RDYX
3.7
–
ns
tSGD
GPIF Data to Clock Setup Time
3.2
–
ns
tDAH
GPIF Data Hold Time
4.5
–
ns
tSGA
Clock to GPIF Address Propagation Delay
–
11.5
ns
tXGD
Clock to GPIF Data Output Propagation Delay
–
15
ns
tXCTL
Clock to CTLX Output Propagation Delay
–
10.7
ns
Notes
33. GPIF asynchronous RDYx signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
34. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *J
Page 52 of 72
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CY7C64713
Slave FIFO Synchronous Read
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 19. Slave FIFO Synchronous Read Timing Diagram
tIFCLK
IFCLK
tSRD
tRDH
SLRD
tXFLG
FLAGS
DATA
N
tOEon
N+1
tXFD
tOEoff
SLOE
The following table provides the Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK. [35]
Table 15. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Min
Max
Unit
tIFCLK
Parameter
IFCLK Period
Description
20.83
–
ns
tSRD
SLRD to Clock Setup Time
18.7
–
ns
tRDH
Clock to SLRD Hold Time
0
–
ns
tOEon
SLOE Turn on to FIFO Data Valid
–
10.5
ns
tOEoff
SLOE Turn off to FIFO Data Hold
–
10.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
–
9.5
ns
tXFD
Clock to FIFO Data Output Propagation Delay
–
11
ns
The following table provides the Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK.[35]
Table 16. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK Period
20.83
200
ns
tSRD
SLRD to Clock Setup Time
12.7
–
ns
tRDH
Clock to SLRD Hold Time
3.7
–
ns
tOEon
SLOE Turn on to FIFO Data Valid
–
10.5
ns
tOEoff
SLOE Turn off to FIFO Data Hold
–
10.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
–
13.5
ns
tXFD
Clock to FIFO Data Output Propagation Delay
–
15
ns
Note
35. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *J
Page 53 of 72
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CY7C64713
Slave FIFO Asynchronous Read
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 20. Slave FIFO Asynchronous Read Timing Diagram
tRDpwh
SLRD
tRDpwl
FLAGS
tXFD
tXFLG
DATA
N
tOEon
SLOE
N+1
tOEoff
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Table 17. Slave FIFO Asynchronous Read Parameters
Min
Max
Unit
tRDpwl
Parameter
SLRD Pulse Width LOW
Description
50
–
ns
tRDpwh
SLRD Pulse Width HIGH
50
–
ns
tXFLG
SLRD to FLAGS Output Propagation Delay
–
70
ns
tXFD
SLRD to FIFO Data Output Propagation Delay
–
15
ns
tOEon
SLOE Turn-on to FIFO Data Valid
–
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
–
10.5
ns
Document Number: 38-08039 Rev. *J
Page 54 of 72
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CY7C64713
Slave FIFO Synchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 21. Slave FIFO Synchronous Write Timing Diagram
tIFCLK
IFCLK
SLWR
DATA
tSWR
tWRH
N
Z
tSFD
Z
tFDH
FLAGS
tXFLG
The following table provides the Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK. [36]
Table 18. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
Min
Max
Unit
tIFCLK
Parameter
IFCLK Period
Description
20.83
–
ns
tSWR
SLWR to Clock Setup Time
18.1
–
ns
tWRH
Clock to SLWR Hold Time
0
–
ns
tSFD
FIFO Data to Clock Setup Time
9.2
–
ns
tFDH
Clock to FIFO Data Hold Time
0
–
ns
tXFLG
Clock to FLAGS Output Propagation Time
–
9.5
ns
The following table provides the Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK. [36]
Table 19. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK [36]
Min
Max
Unit
tIFCLK
Parameter
IFCLK Period
Description
20.83
200
ns
tSWR
SLWR to Clock Setup Time
12.1
–
ns
tWRH
Clock to SLWR Hold Time
3.6
–
ns
tSFD
FIFO Data to Clock Setup Time
3.2
–
ns
tFDH
Clock to FIFO Data Hold Time
4.5
–
ns
tXFLG
Clock to FLAGS Output Propagation Time
–
13.5
ns
Note
36. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *J
Page 55 of 72
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Slave FIFO Asynchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 22. Slave FIFO Asynchronous Write Timing Diagram
tWRpwh
SLWR/SLCS#
tWRpwl
tSFD
tFDH
DATA
tXFD
FLAGS
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Table 20. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
Parameter
Description
Min
Max
Unit
tWRpwl
SLWR Pulse LOW
50
–
ns
tWRpwh
SLWR Pulse HIGH
70
–
ns
tSFD
SLWR to FIFO DATA Setup Time
10
–
ns
tFDH
FIFO DATA to SLWR Hold Time
10
–
ns
tXFD
SLWR to FLAGS Output Propagation Delay
–
70
ns
Slave FIFO Synchronous Packet End Strobe
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 23. Slave FIFO Synchronous Packet End Strobe Timing Diagram
IFCLK
tPEH
PKTEND
tSPE
FLAGS
tXFLG
The following table provides the Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK. [37]
Table 21. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Min
Max
Unit
tIFCLK
Parameter
IFCLK Period
Description
20.83
–
ns
tSPE
PKTEND to Clock Setup Time
14.6
–
ns
tPEH
Clock to PKTEND Hold Time
0
–
ns
tXFLG
Clock to FLAGS Output Propagation Delay
–
9.5
ns
Note
37. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *J
Page 56 of 72
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The following table provides the Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK. [38]
Table 22. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK Period
20.83
200
ns
tSPE
PKTEND to Clock Setup Time
8.6
–
ns
tPEH
Clock to PKTEND Hold Time
2.5
–
ns
tXFLG
Clock to FLAGS Output Propagation Delay
–
13.5
ns
There is no specific timing requirement that needs to be met for
asserting the PKTEND pin concerning asserting SLWR.
PKTEND is asserted with the last data value clocked into the
FIFOs or thereafter. The only consideration is that the set up time
tSPE and the hold time tPEH for PKTEND must be met.
Although there are no specific timing requirements for asserting
PKTEND in relation to SLWR, there exists a specific case
condition that needs attention. When using the PKTEND to
commit a one byte or word packet, an additional timing
requirement must be met when the FIFO is configured to operate
in auto mode and it is necessary to send two packets back to
back:
■
A full packet (defined as the number of bytes in the FIFO
meeting the level set in the AUTOINLEN register) committed
automatically followed by
■
A short one byte or word packet committed manually using the
PKTEND pin.
In this particular scenario, the developer must assert the
PKTEND at least one clock cycle after the rising edge that
caused the last byte or word to be clocked into the previous auto
committed packet. Figure 24 shows this scenario. X is the value
the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 24 shows a scenario where two packets are being
committed. The first packet is committed automatically when the
number of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte or word short packet being
committed manually using PKTEND. Note that there is at least
one IFCLK cycle timing between asserting PKTEND and
clocking of the last byte of the previous packet (causing the
packet to be committed automatically). Failing to adhere to this
timing results in the FX2 failing to send the one byte or word short
packet.
Figure 24. Slave FIFO Synchronous Write Sequence and Timing Diagram
tIFCLK
IFCLK
tSFA
tFAH
FIFOADR
>= tWRH
>= tSWR
SLWR
tSFD
DATA
X-4
tFDH
tSFD
X-3
tFDH
tSFD
X-2
tFDH
tSFD
X-1
tFDH
tSFD
X
tFDH
tSFD
tFDH
1
At least one IFCLK cycle
tSPE
tPEH
PKTEND
Note
38. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *J
Page 57 of 72
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Slave FIFO Asynchronous Packet End Strobe
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 25. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
tPEpwh
PKTEND
tPEpwl
FLAGS
tXFLG
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Table 23. Slave FIFO Asynchronous Packet End Strobe Parameters
Parameter
Description
Min
Max
Unit
tPEpwl
PKTEND Pulse Width LOW
50
–
ns
tPWpwh
PKTEND Pulse Width HIGH
50
–
ns
tXFLG
PKTEND to FLAGS Output Propagation Delay
–
115
ns
Slave FIFO Output Enable
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 26. Slave FIFO Output Enable Timing Diagram
SLOE
DATA
tOEoff
tOEon
Table 24. Slave FIFO Output Enable Parameters
Max
Unit
tOEon
Parameter
SLOE Assert to FIFO DATA Output
Description
10.5
ns
tOEoff
SLOE Deassert to FIFO DATA Hold
10.5
ns
Max
Unit
Slave FIFO Address to Flags/Data
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 27. Slave FIFO Address to Flags/Data Timing Diagram
FIFOADR [1.0]
tXFLG
FLAGS
tXFD
DATA
N
N+1
Table 25. Slave FIFO Address to Flags/Data Parameters
Parameter
Description
tXFLG
FIFOADR[1:0] to FLAGS Output Propagation Delay
10.7
ns
tXFD
FIFOADR[1:0] to FIFODATA Output Propagation Delay
14.3
ns
Document Number: 38-08039 Rev. *J
Page 58 of 72
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Slave FIFO Synchronous Address
Figure 28. Slave FIFO Synchronous Address Timing Diagram
IFCLK
SLCS/FIFOADR [1:0]
tSFA
tFAH
The following table provides the Slave FIFO Synchronous Address Parameters.[39]
Table 26. Slave FIFO Synchronous Address Parameters
Parameter
Description
Min
Max
Unit
20.83
200
ns
FIFOADR[1:0] to Clock Setup Time
25
–
ns
Clock to FIFOADR[1:0] Hold Time
10
–
ns
tIFCLK
Interface Clock Period
tSFA
tFAH
Slave FIFO Asynchronous Address
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 29. Slave FIFO Asynchronous Address Timing Diagram
SLCS/FIFOADR [1:0]
tSFA
tFAH
RD/WR/PKTEND
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Table 27. Slave FIFO Asynchronous Address Parameters
Min
Unit
tSFA
Parameter
FIFOADR[1:0] to RD/WR/PKTEND Setup Time
Description
10
ns
tFAH
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
10
ns
Note
39. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *J
Page 59 of 72
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Sequence Diagram
Single and Burst Synchronous Read Example
Figure 30. Slave FIFO Synchronous Read Sequence and Timing Diagram
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSRD
T=0
tRDH
>= tSRD
>= tRDH
SLRD
t=3
t=2
T=3
T=2
SLCS
tXFLG
FLAGS
tXFD
tXFD
Data Driven: N
DATA
N+1
N+1
N+2
N+3
tOEon
tOEoff
tOEon
tXFD
tXFD
N+4
tOEoff
SLOE
t=4
t=1
T=4
T=1
Figure 31. Slave FIFO Synchronous Sequence of Events Diagram
IFCLK
FIFO POINTER
N
IFCLK
IFCLK
N
N+1
FIFO DATA BUS Not Driven
Driven: N
N+1
N+1
Not Driven
■
At t = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that is
driven on the bus is the data that the internal FIFO pointer is
currently pointing to. In this example it is the first data value in
the FIFO.
Note The data is pre-fetched and is driven on the bus when
SLOE is asserted.
Document Number: 38-08039 Rev. *J
IFCLK
N+3
IFCLK
N+4
N+1
IFCLK
N+4
SLRD
N+2
N+3
N+4
IFCLK
N+4
SLOE
N+4
Not Driven
■
At t = 2, SLRD is asserted. SLRD must meet the setup time of
tSRD (time from asserting the SLRD signal to the rising edge of
the IFCLK) and maintain a minimum hold time of tRDH (time
from the IFCLK edge to the deassertion of the SLRD signal).
If the SLCS signal is used, it must be asserted with SLRD, or
before SLRD is asserted (that is, the SLCS and SLRD signals
must both be asserted to start a valid read condition).
■
The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge of
IFCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
MUST also be asserted.
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
IFCLK
N+2
SLRD
SLOE
Figure 30 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. This diagram illustrates a single read
followed by a burst read.
■
N+1
SLOE
SLRD
SLRD
SLOE
IFCLK
IFCLK
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Page 60 of 72
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Note For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when
SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle, on the rising edge of the clock the
FIFO pointer is updated and increments to point to address N + 1. For each subsequent rising edge of IFCLK, while the SLRD is
asserted, the FIFO pointer is incremented and the next data value is placed on the data bus.
Single and Burst Synchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 32. Slave FIFO Synchronous Write Sequence and Timing Diagram
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSWR
tWRH
>= tWRH
>= tSWR
T=0
SLWR
t=2
T=2
t=3
T=5
SLCS
tXFLG
tXFLG
FLAGS
tFDH
tSFD
tSFD
N+1
N
DATA
t=1
tFDH
T=1
tSFD
tSFD
tFDH
N+3
N+2
T=3
tFDH
T=4
tSPE
tPEH
PKTEND
Figure 32 shows the timing relationship of the SLAVE FIFO
signals during a synchronous write using IFCLK as the
synchronizing clock. This diagram illustrates a single write
followed by burst write of 3 bytes and committing all 4 bytes as
a short packet using the PKTEND pin.
■
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
■
At t = 1, the external master or peripheral must output the data
value onto the data bus with a minimum set up time of tSFD
before the rising edge of IFCLK.
■
At t = 2, SLWR is asserted. The SLWR must meet the setup
time of tSWR (time from asserting the SLWR signal to the rising
edge of IFCLK) and maintain a minimum hold time of tWRH (time
from the IFCLK edge to the deassertion of the SLWR signal).
If SLCS signal is used, it must be asserted with SLWR or before
SLWR is asserted. (that is the SLCS and SLWR signals must
both be asserted to start a valid write condition).
■
While the SLWR is asserted, data is written to the FIFO and on
the rising edge of the IFCLK, the FIFO pointer is incremented.
Document Number: 38-08039 Rev. *J
The FIFO flag is also updated after a delay of tXFLG from the
rising edge of the clock.
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5.
Note For the burst mode, SLWR and SLCS are left asserted for
the entire duration of writing all the required data values. In this
burst write mode, after the SLWR is asserted, the data on the
FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 32, after the four bytes are written to the FIFO,
SLWR is deasserted. The short 4-byte packet is committed to the
host by asserting the PKTEND signal.
There is no specific timing requirement that must be met for
asserting the PKTEND signal with regards to asserting the
SLWR signal. PKTEND is asserted with the last data value or
thereafter. The only consideration is the setup time tSPE and the
hold time tPEH must be met. In the scenario of Figure 32, the
number of data values committed includes the last value written
to the FIFO. In this example, both the data value and the
PKTEND signal are clocked on the same rising edge of IFCLK.
PKTEND is asserted in subsequent clock cycles. The
FIFOADDR lines must be held constant during the PKTEND
assertion.
Page 61 of 72
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CY7C64713
packet committed manually using the PKTEND pin. In this case,
the external master must make sure to assert the PKTEND pin
at least one clock cycle after the rising edge that caused the last
byte or word to be clocked into the previous auto committed
packet (the packet with the number of bytes equal to what is set
in the AUTOINLEN register). Refer to Table 19 on page 55 for
further details on this timing.
Although there are no specific timing requirement for asserting
PKTEND, there is a specific corner case condition that needs
attention while using the PKTEND to commit a one byte or word
packet. Additional timing requirements exist when the FIFO is
configured to operate in auto mode and it is necessary to send
two packets: a full packet (full defined as the number of bytes in
the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte or word
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 33. Slave FIFO Asynchronous Read Sequence and Timing Diagram
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tRDpwl
tRDpwh
tRDpwl
T=0
tRDpwl
tRDpwh
tRDpwl
tRDpwh
tRDpwh
SLRD
t=2
t=3
T=2
T=3
T=5
T=4
T=6
SLCS
tXFLG
tXFLG
FLAGS
tXFD
Data (X)
Driven
DATA
tXFD
tXFD
N
N
N+3
N+2
tOEon
tOEoff
tOEon
tXFD
N+1
tOEoff
SLOE
t=4
t=1
T=7
T=1
Figure 34. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLOE
FIFO POINTER
N
FIFO DATA BUS Not Driven
SLRD
SLRD
SLOE
SLOE
SLRD
SLRD
SLRD
SLRD
SLOE
N
N
N+1
N+1
N+1
N+1
N+2
N+2
N+3
N+3
Driven: X
N
N
Not Driven
N
N+1
N+1
N+2
N+2
Not Driven
Figure 33 shows the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■
The data that drives after asserting SLRD, is the updated data
from the FIFO. This data is valid after a propagation delay of
tXFD from the activating edge of SLRD. In Figure 33, data N is
the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is, SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
■
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
■
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of tRDpwl and minimum de-active pulse width of
tRDpwh. If SLCS is used then, SLCS must be in asserted with
SLRD or before SLRD is asserted (that is, the SLCS and SLRD
signals must both be asserted to start a valid read condition).
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After the SLRD
is asserted, the data from the FIFO is driven on the data bus
(SLOE must also be asserted) and then the FIFO pointer is
incremented.
■
Document Number: 38-08039 Rev. *J
Page 62 of 72
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Sequence Diagram of a Single and Burst Asynchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 35. Slave FIFO Asynchronous Write Sequence and Timing Diagram
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tWRpwl
tWRpwh
T=0
tWRpwl
tWRpwl
tWRpwh
tWRpwl
tWRpwh
tWRpwh
SLWR
t=3
t =1
T=1
T=3
T=4
T=6
T=7
T=9
SLCS
tXFLG
tXFLG
FLAGS
tSFD tFDH
tSFD tFDH
tSFD tFDH
tSFD tFDH
N+1
N+2
N+3
N
DATA
t=2
T=2
T=5
T=8
tPEpwl
tPEpwh
PKTEND
Figure 35 shows the timing relationship of the SLAVE FIFO write
in an asynchronous mode. This diagram shows a single write
followed by a burst write of 3 bytes and committing the
4-byte-short packet using PKTEND.
■
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of tSFA. If SLCS is used, it must also be asserted
(SLCS may be tied low in some applications).
■
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of tWRpwl and minimum de-active pulse width of
tWRpwh. If the SLCS is used, it must be in asserted with SLWR
or before SLWR is asserted.
■
At t = 2, data must be present on the bus tSFD before the
deasserting edge of SLWR.
■
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after tXFLG from the deasserting
edge of SLWR.
Document Number: 38-08039 Rev. *J
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post
incremented.
In Figure 35, after the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet is committed to the
host using the PKTEND. The external device must be designed
to not assert SLWR and the PKTEND signal at the same time. It
must be designed to assert the PKTEND after SLWR is
deasserted and has met the minimum deasserted pulse width.
The FIFOADDR lines are to be held constant during the
PKTEND assertion.
Page 63 of 72
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CY7C64713
Ordering Information
Ordering Code
Package Type
RAM Size
# Prog I/Os
8051
Address/Data
Busses
CY7C64713-128AXC
128-pin TQFP - Pb-free
16K
40
16/8 bit
CY7C64713-100AXC
100-pin TQFP - Pb-free
16K
40
–
CY7C64713-56PVXC
56-pin SSOP - Pb-free
16K
24
–
CY7C64713-56LTXC
56-pin QFN - Pb-free
16K
24
–
CY3674
EZ-USB FX1 Development Kit
Ordering Code Definitions
CY
7
C
64 713 - XXXXX
X X X
Tape and Reel
Temperature Range: X = C or I or A
C = Commercial grade; I = Industrial grade; A = Automotive grade
X = Pb-free
Package Type: XXXXX = 128A or 100A or 56PV or 56LT
128A = 128-pin TQFP;
100A = 100-pin TQFP;
56PV = 56-pin SSOP;
56LT = 56-pin QFN
Part Number
Family Code: 64 = USB
Technology Code: C = CMOS
Marketing Code: 7 = Cypress Products
Company ID: CY = Cypress
Document Number: 38-08039 Rev. *J
Page 64 of 72
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CY7C64713
Package Diagrams
The FX1 is available in four packages:
■
56-pin SSOP
■
56-pin QFN
■
100-pin TQFP
■
128-pin TQFP
Figure 36. 56-pin SSOP 300 Mils O563
51-85062 *D
Document Number: 38-08039 Rev. *J
Page 65 of 72
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Figure 37. 56-pin QFN 8 × 8 × 1 mm LT56B 4.5 × 5.2 EPAD (Sawn)
001-53450 *B
Document Number: 38-08039 Rev. *J
Page 66 of 72
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Figure 38. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA
51-85050 *D
Document Number: 38-08039 Rev. *J
Page 67 of 72
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Figure 39. 128-pin TQFP (14 × 20 × 1.4 mm) A128RA
51-85101 *E
Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. As a result, special attention is required to
the heat transfer area below the package to provide a good
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package. Heat
is transferred from the FX1 through the device’s metal paddle on
the bottom side of the package. Heat from here, is conducted to
the PCB at the thermal pad. It is then conducted from the thermal
pad to the PCB inner ground plane by a 5 × 5 array of via. A via
is a plated through hole in the PCB with a finished diameter of
13 mil. The QFN’s metal die paddle must be soldered to the
PCB’s thermal pad. Solder mask is placed on the board top side
over each via to resist solder flow into the via. The mask on the
top side also minimizes outgassing during the solder reflow
process.
Document Number: 38-08039 Rev. *J
For further information on this package design please refer to
‘Application Notes for Surface Mount Assembly of Amkor's
MicroLeadFrame (MLF) Packages’. This can be found on
Amkor's website http://www.amkor.com.
The application note provides detailed information on board
mounting guidelines, soldering flow, rework process, and so on.
Figure 40 on page 69 displays a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50% solder
coverage. The thickness of the solder paste template must be
5 mil. It is recommended that ‘No Clean’ type 3 solder paste is
used for mounting the part. Nitrogen purge is recommended
during reflow.
Figure 41 on page 69 is a plot of the solder mask pattern and
Figure 42 on page 69 displays an X-Ray image of the assembly
(darker areas indicate solder).
Page 68 of 72
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Figure 40. Cross section of the Area Underneath the QFN Package
0.017” dia
Solder Mask
Cu Fill
Cu Fill
PCB Material
Via hole for thermally connecting the
QFN to the circuit board ground plane.
0.013” dia
PCB Material
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane.
Figure 41. Plot of the Solder Mask (White Area)
Figure 42. X-ray Image of the Assembly
Document Number: 38-08039 Rev. *J
Page 69 of 72
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Acronyms
Acronym
Document Conventions
Description
Units of Measure
ASIC
application specific integrated circuit
ATA
advanced technology attachment
cm
centi meter
CPU
central processing unit
°C
degree Celsius
DID
device identifier
kHZ
kilo Hertz
DSL
digital service line
k
kilo ohms
DSP
digital signal processor
Mbps
Mega bits per second
ECC
error correction code
MBPs
Mega bytes per second
EEPROM
electrically erasable programmable read-only
memory
MHz
Mega Hertz
EPP
enhanced parallel port
µA
micro Amperes
FIFO
first in first out
µs
micro seconds
GPIF
general programmable interface
µW
micro Watts
GPIO
general purpose input/output
mA
milli Amperes
I/O
input/output
mm
milli meter
LAN
local area network
ms
milli seconds
LSB
least significant bit
mW
milli Watts
MSB
most significant bit
ns
nano seconds
PCB
printed circuit board

ohms
PCMCIA
personal computer memory card international
association
ppm
parts per million
%
percent
PID
product identifier
pF
pico Farad
PLL
phase-locked loop
V
Volts
QFN
quad flat no leads
RAM
random access memory
SFR
special function register
SIE
serial interface engine
SOF
start of frame
SSOP
shrink small-outline package
TQFP
thin quad flat pack
USARTS
universal serial asynchronous receiver/transmitter
USB
universal serial bus
UTOPIA
universal test and operations physical-layer
interface
VID
vendor identifier
Document Number: 38-08039 Rev. *J
Symbol
Unit of Measure
Page 70 of 72
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CY7C64713
Document History Page
Document Title: CY7C64713, EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller
Document Number: 38-08039
Revision
ECN
Orig. of
Change
Submission
Date
**
132091
KKU
02/10/04
New Datasheet.
*A
230709
KKU
SEE ECN
Changed Lead free Marketing part numbers in Ordering Information according
to spec change in 28-00054.
*B
307474
BHA
SEE ECN
Changed default PID in Table 2 on page 5.
Updated register table.
Removed word compatible where associated with I2C.
Changed Set-up to Setup.
Added Power Dissipation.
Changed Vcc from ± 10% to ± 5%
Added values for VIH_X, VIL_X
Added values for ICC
Added values for ISUSP
Removed IUNCONFIGURED from DC Characteristics on page 47.
Changed PKTEND to FLAGS output propagation delay (asynchronous
interface) in Table 10-14 from a maximum value of 70 ns to 115 ns.
Removed 56 SSOP and added 56 QFN package.
Provided additional timing restrictions and requirement regarding the use of
PKTEND pin to commit a short one byte/word packet subsequent to committing
a packet automatically (when in auto mode).
Added part number CY7C64714 ideal for battery powered applications.
Changed Supply Voltage in section 8 to read +3.15V to +3.45V.
Added Min Vcc Ramp Up time (0 to 3.3 V).
Removed Preliminary.
*C
392702
BHA
SEE ECN
Corrected signal name for pin 54 in Figure 10 on page 18.
Added information on the AUTOPTR1/AUTOPTR2 address timing with regards
to data memory read/write timing diagram.
Removed TBD in Table 15 on page 53.
Added section PORTC Strobe Feature Timings on page 51.
*D
1664787
CMCC/
JASM
See ECN
Added the 56 pin SSOP pinout and package information.
Delete CY7C64714.
*E
2088446
JASM
See ECN
Updated package diagrams.
*F
2710327
DPT
05/22/2009
Added 56-Pin QFN (8 × 8 mm) package diagram
Updated ordering information for CY7C64713-56LTXC part
*G
2765406
ODC
09/17/2009
Added Pb-free for the CY7C64713-56LTXC part in the ordering information
table.
Updated 56-Pin Sawn QFN package diagram.
*H
2896318
ODC
03/18/2010
Removed obsolete part CY7C64713-56LFXC. Updated all package diagrams.
*I
3186891
ODC
03/03/2011
Template updates.
Updated package diagrams: 51-85144 , 51-85050, 51-85101
*J
3259101
ODC
05/17/2011
Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
Document Number: 38-08039 Rev. *J
Description of Change
Page 71 of 72
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CY7C64713
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
Clocks & Buffers
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
Optical & Image Sensing
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-08039 Rev. *J
Revised May 17, 2011
Page 72 of 72
EZ-USB FX1, EZ-USB FX2LP, EZ-USB FX2, and ReNumeration are trademarks, and EZ-USB is a registered trademark, of Cypress Semiconductor. All product and company names mentioned in this
document are the trademarks of their respective holders.
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