Exar MP7529B 5 v cmos dual buffered multiplying 8-bit digital-to-analog converter Datasheet

MP7529B
5 V CMOS
Dual Buffered Multiplying 8-Bit
Digital-to-Analog Converter
FEATURES
BENEFITS
•
•
•
•
•
•
•
•
•
•
• Quiet Operation in Audio Applications
• Easy Interface to Microprocessors
Very Low Total Harmonic Distortion
Low Glitch Energy
Fast Settling Time
Four Quadrant Multiplication
On-Chip Latches for Both DACs
4.5 V to 5.5 V Operation
Low Power Consumption
TTL/5V CMOS Compatible
Latch-Up Free
15 V Operation: MP7529A
Data is transferred to either of the two D/A Converter latches
via a common 8-bit TTL/5 V CMOS compatible input port. The
control input DAC A/DAC B determines which D/A is to be
loaded.
GENERAL DESCRIPTION
The MP7529B is a dual 8-bit Digital-to-Analog Converter
featuring excellent DAC to DAC matching, tracking and
specifically optimized for applications requiring low total
harmonic distortion. The MP7529B is manufactured using
advanced thin film resistors on a double metal CMOS process.
The MP7529B incorporates a unique bit decoding technique
yielding lower glitch energy, higher speed and excellent
accuracy over temperature and time.
The device operates from a 4.5 V to 5.5 V power supply, and
is TTL-compatible over this range. Power dissipation is only 10
mW. Both DACs offer excellent four quadrant multiplication
characteristics, and include separate reference inputs and
feedback resistors. An improved latch-up resistant design
eliminates the need for external protective Schottky diodes in
most applications.
SIMPLIFIED BLOCK AND TIMING DIAGRAM
VDD
VREFA
RFBA
D
Q
LATCH A
E
DB7-DB0
DAC A/DAC B
IOUTA
DAC A
DB7-DB0
DAC A/DAC B
CS
WR
RFBB
D
Q
LATCH B
E
CS
WR
DGND
IOUTB
DAC B
AGND
VREFB
Rev. 2.00
1
OUT
MP7529B
ORDERING INFORMATION
Package
Type
Temperature
Range
Part No.
INL
(LSB)
DNL
(LSB)
Gain Error
(LSB)
Plastic Dip
–40 to +85°C
MP7529BJN
+1
+1
+5
Plastic Dip
–40 to +85°C
MP7529BKN
+1/2
+1
+3
SOIC
–40 to +85°C
MP7529BJS
+1
+1
+5
SOIC
–40 to +85°C
MP7529BKS
+1/2
+1
+3
PLCC
–40 to +85°C
MP7529BJP
+1
+1
+5
PLCC
–40 to +85°C
MP7529BKP
+1/2
+1
+3
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
IOUTB
IOUTA
AGND
RFBA
RFBB
3
AGND
IOUTA
RFBA
VREFA
DGND
DAC A/DAC B
(MSB) DB7
DB6
DB5
DB4
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
IOUTB
RFBB
VREFB
VDD
WR
CS
DB0 (LSB)
DB1
DB2
DB3
20 Pin PDIP (0.300”)
N20
1
20
2
19
3
18
4
5
6
See
Pin Out
at Left
17
8
13
9
12
10
11
20
19
4
18
VREFB
DGND
5
17
VDD
DAC A/DAC B
6
16
WR
(MSB) DB7
7
15
CS
DB6
8
14
DB0
(LSB)
15
14
1
VREFA
16
7
2
9
10
11
12
13
DB5
DB3
DB1
DB4
DB2
20 Pin SOIC (Jedec, 0.300”)
S20
20 Pin PLCC
P20
PIN OUT DEFINITIONS
PIN NO.
NAME
DESCRIPTION
PIN NO.
NAME
DESCRIPTION
1
AGND
Analog Ground
11
DB3
Data Input Bit 3
2
IOUTA
Current Output of DAC A
12
DB2
Data Input Bit 2
3
RFBA
Internal Feedback Resistor of DAC A
13
DB1
Data Input Bit 1
4
VREFA
Reference Input Voltage of DAC A
14
DB0
Data Input Bit 0 (LSB)
5
DGND
Digital Ground
15
CS
Chip Select (Active Low)
6
DACA/
DACB
DAC selection control
16
WR
Write Enable (Active Low)
17
DB7
Data Input Bit 7 (MSB)
VDD
Power Supply
7
18
DB6
Data Input Bit 6
VREFB
Reference Input Voltage of DAC B
8
19
DB5
Data Input Bit 5
RFBB
Internal Feedback Resistor of DAC B
9
20
DB4
Data Input Bit 4
IOUTB
Current Output of DAC B
10
Rev. 2.00
2
MP7529B
ELECTRICAL CHARACTERISTICS
(VDD = 4.5 V to 5.5 V, Nominal VDD = 5 V, VREF = 10 V unless otherwise noted)
Parameter
Symbol
Min
N
8
25°C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
STATIC PERFORMANCE1
Resolution (All Grades)
Integral Non-Linearity
(Relative Accuracy)
J
K
Differential Non-Linearity
J
K
Gain Error
J
K
8
Bits
INL
+1
+1/2
+1
+1/2
+1
+1
+1
+1
+4
+2
+5
+3
DNL
GE
LSB
End Point Linearity Spec.
LSB
All grades monotonic over full
temperature range.
LSB
Using Internal RFB
Gain Temperature Coefficient2
TCGE
+15
+15
ppm/°C
∆Gain/∆Temperature
Power Supply Rejection Ratio
PSRR
+100
+200
ppm/%
|∆Gain/∆VDD|, ∆VDD = + 5%
VDD = 4.75 V, +5%, & 5.25 V +5%
ILKG
+50
+200
nA
Output Leakage Current
DYNAMIC PERFORMANCE2
Harmonic Distortion
Digital Crosstalk
AC Feedthrough
VREFA to IOUTA
VREFB to IOUTB
Channel-to-Channel Isolation
VREFA to IOUTB
VREFB to IOUTA
Glitch Energy
Current Settling Time
Propagation Delay
THD
Q
FT
FTA
FTB
CCI
CCIBA
CCIAB
Egl
tS
tPD
–95
30
–70
–70
–65
–65
–77
–77
10
200
100
250
150
dB
nVs
dB
dB
dB
dB
dB
dB
nVs
ns
ns
15
+1
kΩ
%
REFERENCE INPUT
Input Resistance
Input Resistance Matching
RIN
8
VIH
VIL
2.4
15
+1
8
DIGITAL INPUTS3
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
Input Capacitance2
Data
Control
2.4
ILKG
0.8
+1
0.8
+10
CIN
CIN
10
15
10
15
Rev. 2.00
3
V
V
µA
pF
pF
VIN = 6VRMS @ 1 KHz
All zeros to all ones Input Change.
To 1/2 LSB,RL=100Ω, CEXT=13pF
From 50% of digital input to 90%
of final analog output current
RL=100Ω, CEXT=13pF
MP7529B
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
25°C
Typ
Max
Tmin to Tmax
Min
Max
COUTA/B
COUTA/B
120
50
120
50
IDD
1
2
1
2
Symbol
Min
Units
Test Conditions/Comments
ANALOG OUTPUTS2
Output Capacitance
pF
pF
DAC inputs all 1’s
DAC inputs all 0’s
mA
mA
All digital inputs = 0 V or 5 V
All digital inputs = VIL or VIH
POWER SUPPLY
Supply Current
TIMING SPECIFICATIONS4
Chip Select to Write Set-Up Time
Chip Select to Write Hold Time
DAC Select to Write Set-Up Time
DAC Select to Write Hold Time
Data Valid to Write Set-Up Time
Data Valid to Write Hold Time
Write Pulse Width5
tCS
tCH
tAS
tAH
tDS
tDH
tWR
60
15
60
15
60
0
60
80
20
80
20
80
0
80
ns
ns
ns
ns
ns
ns
ns
NOTES:
Full Scale Range (FSR) is 10V for unipolar mode.
2
Guaranteed but not production tested.
3
Digital input levels should not go below GND or exceed the positive supply voltage, otherwise damage may occur.
4
See timing diagram.
5
tWR = 40ns minimum if tDH > 15ns (@T = 25°C)
1
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3
VRFBA, VRFBB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C
Package Power Dissipation Rating to 75°C
PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . . 900mW
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 12mW/°C
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V
(Functionality Guaranteed +0.5 V)
Digital Input Voltage to GND . . . . GND –0.5 to VDD +0.5 V
IOUTA, IOUTB to GND . . . . . . . . . . . GND –0.5 to VDD +0.5 V
VREFA, VREFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100µs.
3
GND refers to AGND and DGND.
Rev. 2.00
4
MP7529B
are both low the selected DAC is in the write mode. The input
data latches of the selected DAC are transparent and its analog
output responds to activity on DB0-DB7 (Write mode). The selected DAC latch retains the data which was present on
DB0-DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches (Hold mode).
DIGITAL INTERFACE
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 10nA.
The control input DAC A/DAC B selects which DAC can accept data from the input port. Inputs CS and WR control the operating mode of the selected DAC (Table 1.). When CS and WR
tCS
tCH
tAS
tAH
CS
DAC A/
DAC B
VALID
DAC A/
DAC B
tWR
L
H
X
X
L = Low State
WR
tDS
DB7-DB0
CS
tDH
VALID
WR
L
L
L
L
H
X
X
H
H = High State
DAC A
WRITE
HOLD
HOLD
HOLD
X = Don’t Care
DAC B
HOLD
WRITE
HOLD
HOLD
NOTE:
1. Timing measured from (VIH + VIL) /2
Figure 1. Write Cycle Timing Diagram
Table 1. DAC’s Mode Selection
MICROPROCESSOR INTERFACE
NOTE:
8085 instruction shld (store H & L direct) can update
both DACS with data from H and L registers
A0-A15
Address Bus
A**
VMA
CPU
6800
φ2
D0–D7
ADDRESS
DECODE
LOGIC
A**
DAC A/DAC B
CS
A+1***
Address Bus
A8-A15
DAC A
CPU
8085
WR MP7529B*
DAC B
DB0
DB7
WR
ALE
Data Bus
AD0–AD7
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 752B9 DAC B Address
ADDRESS
DECODE
LOGIC
DAC A/DAC B
CS
A+1***
LATCH
8212
WR
DB0
DB7
DAC A
MP7529B*
DAC B
ADDR/Data Bus
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 7529B DAC B Address
Figure 2. MP7529B Dual DAC to 6800
CPU Interface
Figure 3. MP7529B Dual DAC to 8085
CPU Interface
Rev. 2.00
5
MP7529B
PERFORMANCE CHARACTERISTICS
Graph 1. Relative Accuracy vs. Digital Code
APPLICATION NOTES
Refer to Section 8 for Applications Information
Rev. 2.00
6
MP7529B
20 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
S20
D
20
11
E
H
10
h x 45°
C
A
Seating
Plane
B
e
α
A1
L
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
A
0.097
0.104
2.464
A1
0.0050
0.0115
0.127
0.292
B
0.014
0.019
0.356
0.483
C
0.0091
0.0125
0.231
0.318
D
0.500
0.510
12.70
12.95
E
0.292
0.299
7.42
7.59
e
0.050 BSC
MAX
2.642
1.27 BSC
H
0.400
0.410
10.16
10.41
h
0.010
0.016
0.254
0.406
L
0.016
0.035
0.406
0.889
α
0°
8°
0°
8°
Rev. 2.00
7
MP7529B
20 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
P20
D
D1
Seating
Plane
A2
1
D
B
D1
D2
e1
C
D3
A1
A
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
MAX
A
0.165
0.180
4.19
4.57
A1
0.100
0.110
2.54
2.79
A2
0.148
0.156
3.76
3.96
B
0.013
0.021
0.330
0.533
C
0.008
0.012
0.203
0.305
D
0.385
0.395
9.78
10.03
D1 (1)
0.350
0.354
8.89
8.99
D2
0.290
0.330
7.37
8.38
D3
0.200 Ref
5.08 Ref.
e1
0.050 BSC
1.27 BSC
Note:
(1)
Dimension D1 does not include mold protrusion.
Allowed mold protrusion is 0.254 mm/0.010 in.
Rev. 2.00
8
MP7529B
20 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
N20
S
20
11
1
10
Q1
E1
E
D
A1
Seating
Plane
A
L
B
e
B1
α
MILLIMETERS
INCHES
SYMBOL
A
MIN
MAX
MIN
MAX
––
0.200
––
5.08
A1
0.015
––
0.38
––
B
0.014
0.023
0.356
0.584
B1 (1)
0.038
0.065
0.965
1.65
C
0.008
0.015
0.203
0.381
D
0.945
1.060
24.0
26.92
E
0.295
0.325
7.49
8.26
E1
0.220
0.310
5.59
7.87
e
0.100 BSC
2.54 BSC
L
0.115
0.150
2.92
3.81
α
0°
15°
0°
15°
Q1
0.055
0.070
1.40
1.78
S
0.040
0.080
1.02
2.03
Note:
(1)
The minimum limit for dimensions B1 may be 0.023”
(0.58 mm) for all four corner leads only.
Rev. 2.00
9
C
MP7529B
Notes
Rev. 2.00
10
MP7529B
Notes
Rev. 2.00
11
MP7529B
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00
12
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