TI1 MSP430X12X Mixed signal microcontroller Datasheet

MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
D Low Supply Voltage Range 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D Serial Communication Interface (USART0)
− Active Mode: 200 μA at 1 MHz, 2.2 V
− Standby Mode: 0.7 μA
− Off Mode (RAM Retention): 0.1 μA
Five Power Saving Modes
Wake-Up From Standby Mode in less
than 6 μs
16-Bit RISC Architecture, 125 ns
Instruction Cycle Time
Basic Clock Module Configurations:
− Various Internal Resistors
− Single External Resistor
− 32 kHz Crystal
− High Frequency Crystal
− Resonator
− External Clock Source
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
D
D
D
D
Software-Selects Asynchronous UART or
Synchronous SPI
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Family Members Include:
MSP430F122: 4KB + 256B Flash Memory
256B RAM
MSP430F123: 8KB + 256B Flash Memory
256B RAM
Available in a 28-Pin Plastic Small-Outline
Wide Body (SOWB) Package, 28-Pin Plastic
Thin Shrink Small-Outline Package
(TSSOP) and 32-Pin QFN Package
For Complete Module Descriptions, See the
MSP430x1xx Family User’s Guide,
Literature Number SLAU049
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6μs.
The MSP430F12x series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and
twenty-two I/O pins. The MSP430F12x series also has a built-in communication capability using asynchronous
(UART) and synchronous (SPI) protocols in addition to a versatile analog comparator.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. Stand alone RF sensor front end is another
area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C
40°C to 85°C
PLASTIC 28-PIN SOWB
(DW)
PLASTIC 28-PIN TSSOP
(PW)
PLASTIC 32-PIN QFN
(RHB)
MSP430F122IDW
MSP430F123IDW
MSP430F122IPW
MSP430F123IPW
MSP430F122IRHB
MSP430F123IRHB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2001 − 2004 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
pin designation, MSP430x12x
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
VSS
P2.4/CA1/TA2
XOUT
P2.3/CA0/TA1
XIN
P3.7
NC
P3.6
RST/NMI
P3.5/URXD0
P2.0/ACLK
P3.4/UTXD0
P2.1/INCLK
P2.2/CAOUT/TA0
1 31 30 29 28 27 26 24
2
23
3
22
4
21
20
5
6
19
18
7
8 10 11 12 13 14 15 17
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
NC
P2.4/CA1/TA2
P2.3/CA0/TA1
NC
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
P3.5/URXD0
P3.6
P3.7
TEST
VCC
P2.5/ROSC
VSS
XOUT
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/CAOUT/TA0
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P2.5/ROSC
NC
VCC
TEST
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
RHB PACKAGE
(TOP VIEW)
DW OR PW PACKAGE
(TOP VIEW)
Note: NC pins not internally connected
Power Pad connection to VSS recommended
functional block diagram
XIN
XOUT
VCC
VSS
P1
RST/NMI
JTAG
ROSC
Oscillator
System
Clock
ACLK
8KB Flash
SMCLK
4KB Flash
256B RAM
P2
8
I/O Port 1
8 I/Os, with
Interrupt
Capability
P3
6
8
I/O Port 2
6 I/Os, with
Interrupt
Capability
I/O Port 3
8 I/Os
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
TEST
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
Watchdog
Timer
Timer_A3
MDB, 8 Bit
POR
3 CC Reg
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USART0
UART Mode
SPI Mode
15/16-Bit
2
Comparator
A
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
DW, PW
RHB
NO.
NO.
P1.0/TACLK
21
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
22
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL
transmit
P1.2/TA1
23
23
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
24
24
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK/TCK
25
25
I/O
General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device
programming and test
P1.5/TA0/TMS
26
26
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input
terminal for device programming and test
P1.6/TA1/TDI/TCLK
27
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal or
test clock input
P1.7/TA2/TDO/TDI †
28
28
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or
data input during programming
P2.0/ACLK
8
6
I/O
General-purpose digital I/O pin/ACLK output
P2.1/INCLK
9
7
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0
10
8
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output/BSL
receive
P2.3/CA0/TA1
19
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/comparator_A, input
P2.4/CA1/TA2
20
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/comparator_A, input
P2.5/ROSC
3
32
I/O
General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal
frequency
NAME
DESCRIPTION
P3.0/STE0
11
9
I/O
General-purpose digital I/O pin/slave transmit enable—USART0/SPI mode
P3.1/SIMO0
12
10
I/O
General-purpose digital I/O pin/slave in/master out of USART0/SPI mode
P3.2/SOMI0
13
11
I/O
General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
P3.3/UCLK0
14
12
I/O
General-purpose digital I/O pin/external clock input—USART0/UART or SPI mode, clock
output—USART0/SPI mode clock input
P3.4/UTXD0
15
13
I/O
General-purpose digital I/O pin/transmit data out—USART0/UART mode
P3.5/URXD0
16
14
I/O
General-purpose digital I/O pin/receive data in—USART0/UART mode
P3.6
17
15
I/O
General-purpose digital I/O pin
P3.7
18
16
I/O
General-purpose digital I/O pin
RST/NMI
7
5
I
Reset or nonmaskable interrupt input
TEST
1
29
I
Selects test mode for JTAG pins on Port1
VCC
2
30
VSS
4
1
XIN
6
3
I
Input terminal of crystal oscillator
XOUT
5
2
O
Output terminal of crystal oscillator
NC
QFN Pad
†
I/O
Supply voltage
Ground reference
4, 17,
20, 31
NA
Package
Pad
No internal connection
NA
QFN package pad connection to VSS recommended.
TDO or TDI is selected via JTAG instruction.
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MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers
are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Indirect
D
D
D
D
D
Indirect
autoincrement
Register
Indexed
Symbolic (PC relative)
Absolute
Immediate
NOTE: S = source
4
S D
D
D
D
D
SYNTAX
EXAMPLE
MOV Rs,Rd
MOV R10,R11
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
MOV EDE,TONI
OPERATION
R10
−−> R11
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
D
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
D
MOV #X,TONI
MOV #45,TONI
D = destination
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#45
−−> M(TONI)
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh-0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash memory
WDTIFG (see Note1)
KEYV (see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG (see Notes 1 and 4)
OFIFG (see Notes 1 and 4)
ACCVIFG (see Notes 1 and 4)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
14
0FFFAh
13
0FFF8h
12
Comparator_A
CAIFG
maskable
0FFF6h
11
Watchdog timer
WDTIFG
maskable
0FFF4h
10
Timer_A3
TACCR0 CCIFG (see Note 2)
maskable
0FFF2h
9
Timer_A3
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 and 2)
maskable
0FFF0h
8
USART0 receive
URXIFG0
maskable
0FFEEh
7
USART0 transmit
UTXIFG0
maskable
0FFECh
6
0FFEAh
5
0FFE8h
4
I/O Port P2
(eight flags − see Note 3)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
maskable
0FFE6h
3
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
maskable
0FFE4h
2
NOTES: 1.
2.
3.
4.
6
0FFE2h
1
0FFE0h
0, lowest
Multiple source flags
Interrupt flags are located in the module
There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’12x devices.
(non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
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MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
Address
7
6
0h
5
4
ACCVIE
NMIIE
rw-0
3
2
1
OFIE
rw-0
0
WDTIE
rw-0
rw-0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash access violation interrupt enable
Address
7
6
5
4
3
2
01h
1
UTXIE0
USART0: UART and SPI receive-interrupt enable
UTXIE0:
USART0: UART and SPI transmit-interrupt enable
URXIE0
rw-0
rw-0
URXIE0:
0
interrupt flag register 1 and 2
Address
7
6
5
02h
4
3
2
NMIIFG
1
OFIFG
rw-0
rw-1
0
WDTIFG
rw-(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
Address
7
6
5
4
3
03h
2
1
UTXIFG0
rw-0
URXIFG0:
USART0: UART and SPI receive flag
UTXIFG0:
USART0: UART and SPI transmit flag
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0
URXIFG0
rw-0
7
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
module enable registers 1 and 2
Address
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
04h
Address
05h
UTXE0
rw-0
URXE0:
USART0: UART receive enable
UTXE0:
USART0: UART transmit enable
USPIE0:
USART0: SPI (synchronous peripheral interface) transmit and receive enable
Legend
0
URXE0
USPIE0
rw:
rw-0,1:
rw-(0,1):
rw-0
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC
Bit can be read and written. It is Reset or Set by POR
SFR bit is not present in device.
memory organization
MSP430F122
MSP430F123
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
4KB Flash
0FFFFh−0FFE0h
0FFFFh−0F000h
8KB Flash
0FFFFh−0FFE0h
0FFFFh−0E000h
Information memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
256 Byte
02FFh − 0200h
256 Byte
02FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
8
BSL Function
DW & PW Package Pins
RHB Package Pins
Data Transmit
22 - P1.1
22 - P1.1
Data Receive
10 - P2.2
8 - P2.2
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MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number
SLAU049.
oscillator and system clock
The clock system in the MSP430x12x devices is supported by the basic clock module that includes support for
a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal
oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The basic
clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
digital I/O
There are three 8-bit I/O ports implemented—ports P1, P2, and P3 (only six port P2 I/O signals are available
on external pins):
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and six bits of port P2.
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port
P2 are implemented. Port P3 has no interrupt capability.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
USART0
The MSP430x12x devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Output Pin Number
Input Pin Number
DW, PW
RHB
21 - P1.0
21 - P1.0
Device Input Signal Module Input Name
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
9 - P2.1
7 - P2.1
INCLK
INCLK
22 - P1.1
22 - P1.1
TA0
CCI0A
10 - P2.2
8 - P2.2
23 - P1.2
24 - P1.3
23 - P1.2
24 - P1.3
TA0
CCI0B
DVSS
GND
DVCC
VCC
Module Block
Module Output Signal
Timer
NA
CCR0
DW, PW
RHB
22 - P1.1
22 - P1.1
26 - P1.5
26 - P1.5
TA0
TA1
CCI1A
19 - P2.3
18 - P2.3
CAOUT (internal)
CCI1B
23 - P1.2
23 - P1.2
DVSS
GND
27 - P1.6
27 - P1.6
20 - P2.4
19 - P2.4
24 - P1.3
24 - P1.3
28 - P1.7
28 - P1.7
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR1
CCR2
TA1
TA2
comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
peripheral file map
PERIPHERALS WITH WORD ACCESS
Timer_A
Flash Memory
Watchdog
Reserved
Reserved
Reserved
Reserved
Capture/compare
Capture/compare
Capture/compare
Timer_A register
Reserved
Reserved
Reserved
Reserved
Capture/compare
Capture/compare
Capture/compare
Timer_A control
Timer_A interrupt
register
register
register
TACCR2
TACCR1
TACCR0
TAR
control
control
control
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
0166h
0164h
0162h
0160h
012Eh
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog/timer control
WDTCTL
0120h
vector
PERIPHERALS WITH BYTE ACCESS
USART0
Transmit buffer
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL
077h
076h
075h
074h
073h
072h
071h
070h
Comparator_A
Comparator_A port disable
Comparator_A control2
Comparator_A control1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock
Basic clock sys. control2
Basic clock sys. control1
DCO clock freq. control
BCSCTL2
BCSCTL1
DCOCTL
058h
057h
056h
Port P3
Port P3 selection
Port P3 direction
Port P3 output
Port P3 input
P3SEL
P3DIR
P3OUT
P3IN
01Bh
01Ah
019h
018h
Port P2
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
026h
025h
024h
023h
022h
021h
020h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Special Function
Module enable2
Module enable1
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
ME2
ME1
IFG2
IFG1
IE2
IE1
005h
004h
003h
002h
001h
000h
absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TEST pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX
UNITS
Supply voltage during program execution,
execution VCC (see Note 1)
18
1.8
36
3.6
V
Supply voltage during program/erase flash memory, VCC
Supply voltage, VSS
2.7
3.6
V
Operating free-air temperature range, TA
−40
85
°C
0
LF mode selected, XTS=0
LFXT1 crystal
t l ffrequency, f(LFXT1)
(see Note 2)
Watch crystal
32 768
Ceramic resonator
XT1 selected mode,
mode XTS=1
XTS 1
Processor frequency f(system) (MCLK signal)
V
Hz
450
8000
1000
8000
VCC = 1.8 V
dc
4.15
VCC = 3.6 V
dc
8
Crystal
kHz
MHz
NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to VSS when VCC <2.5 V. The LFXT1 oscillator in
XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC ≥ 2.2 V. The LFXT1 oscillator in XT1-mode accepts
a ceramic resonator or a crystal frequency of 8 MHz at VCC ≥ 2.8 V.
2. The LFXT1 oscillator in LF-mode requires a watch crystal. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or crystal.
f(system) (MHz)
8.0 MHz
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Supply voltage range,
’F12x, during
program execution
4.15 MHz
1.8 V
Supply voltage range, ’F12x,
during flash memory programming
2.7 V 3 V
3.6 V
Supply Voltage − V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.7 V.
Figure 1. Frequency vs Supply Voltage, MSP430F12x
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current (into VCC) excluding external current
PARAMETER
I(AM)
Active mode
I(CPUOff)
(C Off)
Low power mode,
Low-power
mode (LPM0)
I(LPM2)
(
)
Low power mode,
Low-power
mode (LPM2)
TEST CONDITIONS
MIN
VCC = 2.2 V
200
250
VCC = 3 V
300
350
TA = −40°C +85°C,
f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz,
Hz
Program executes in Flash
VCC = 2.2 V
3
5
VCC = 3 V
11
18
TA = −40°C +85°C,
f(MCLK) = 0
0, f(SMCLK) = 1 MHz
MHz,
f(ACLK) = 32,768 Hz
VCC = 2.2 V
32
45
VCC = 3 V
55
70
TA = −40°C +85°C,
MHz,
f(MCLK) = f(SMCLK) = 0 MHz
f(ACLK) = 32,768 Hz, SCG0 = 0
VCC = 2.2 V
11
14
VCC = 3 V
17
22
0.8
1.2
0.7
1
1.6
2.3
1.8
2.2
1.6
1.9
TA = 85°C
2.3
3.4
TA = −40°C
0.1
0.5
0.1
0.5
0.8
1.9
VCC = 2.2 V
TA = 85°C
TA = −40°C
TA = 25°C
I(LPM4)
Low-power
p
mode,, ((LPM4))
UNIT
μA
TA = 25°C
Low power mode,
Low-power
mode (LPM3)
MAX
TA = −40°C +85°C,
fMCLK = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz,
Program executes in Flash
TA = −40°C
I(LPM3)
(
)
TYP
VCC = 3 V
TA = 25°C
VCC = 2.2 V/3 V
TA = 85°C
μA
μA
μA
μA
μ
μA
μ
μA
μ
NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
current consumption of active mode versus system frequency
IAM = IAM[1 MHz] × fsystem [MHz]
current consumption of active mode versus supply voltage
IAM = IAM[3 V] + 120 μA/V × (VCC−3 V)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs Port P1 to Port P3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
PARAMETER
VIT+
Positive going input threshold voltage
Positive-going
VIT−
Negative going input threshold voltage
Negative-going
Vhys
Input voltage hysteresis,
hysteresis (VIT+ − VIT−)
VCC
MIN
2.2 V
1.1
TYP
MAX
1.5
3V
1.5
1.9
2.2 V
0.4
0.9
3V
0.9
1.3
2.2 V
0.3
1.1
3V
0.5
1
VCC
MIN
UNIT
V
V
V
standard inputs − RST/NMI, TEST; JTAG: TCK, TMS, TDI/TCLK
PARAMETER
VIL
Low-level input voltage
VIH
High-level input voltage
2 2 V/3 V
2.2
TYP
MAX
UNIT
VSS
VSS+0.6
V
0.8×VCC
VCC
V
MAX
UNIT
inputs Px.x, TAx
PARAMETER
t(int)
External interrupt
p timing
g
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External
trigger
gg signal
g
for the interrupt
p flag,
g,
(
(see
Note 1))
t(cap)
Timer A capture timing
Timer_A,
TA0
TA0, TA1
TA1, TA2
f(TAext)
Timer_A clock frequency
externally applied to pin
TACLK,
TACLK INCLK t(H) = t(L)
f(TAint)
Timer A clock frequency
Timer_A
SMCLK or ACLK signal selected
VCC
MIN
2.2 V/3 V
1.5
2.2 V
62
3V
50
2.2 V
62
3V
50
TYP
cycle
ns
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
leakage current (see Notes 1 and 2)
PARAMETER
Ilkg(Px.x)
High impedance leakage current
High-impedance
TEST CONDITIONS
VCC
MIN
TYP
MAX
Port P1: P1.x, 0 ≤ × ≤ 7
2.2 V/3 V
±50
Port P2: P2.x, 0 ≤ × ≤ 5
2.2 V/3 V
±50
UNIT
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs Port 1 to Port 3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
PARAMETER
TEST CONDITIONS
I(OHmax) = −1.5 mA
VOH
High level output voltage
High-level
I(OHmax) = −6 mA
I(OHmax) = −1.5 mA
I(OHmax) = −6 mA
I(OLmax) = 1.5 mA
VOL
Low level output voltage
Low-level
I(OLmax) = 6 mA
I(OLmax) = 1.5 mA
I(OLmax) = 6 mA
VCC = 2
2.2
2V
VCC = 3 V
VCC = 2
2.2
2V
VCC = 3 V
MIN
TYP
MAX
See Note 1
VCC−0.25
VCC
See Note 2
VCC−0.6
VCC
See Note 1
VCC−0.25
VCC
See Note 2
VCC−0.6
VCC
See Note 1
VSS
VSS+0.25
See Note 2
VSS
VSS+0.6
See Note 1
VSS
VSS+0.25
See Note 2
VSS
VSS+0.6
UNIT
V
V
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
outputs P1.x, P2.x, P3.x, TAx
PARAMETER
f(P20)
f(TAx)
Output frequency
TEST CONDITIONS
VCC
P2.0/ACLK; CL = 20 pF
2.2 V/3 V
TA0, TA1, TA2; CL = 20 pF,
Internal clock source, SMCLK signal applied (see Note 1)
2.2 V/3 V
fSMCLK = fLFXT1 = fXT1
P1.4/SMCLK,
P1
4/SMCLK
CL = 20 pF
t(Xdc)
Duty cycle of O/P
frequency
fSMCLK = fLFXT1 = fLF
2 2 V/3 V
2.2
fSMCLK = fLFXT1/n
fSMCLK = fDCOCLK
2.2 V/3 V
fP20 = fLFXT1 = fXT1
P2.0/ACLK,
P2
0/ACLK
CL = 20 pF
fP20 = fLFXT1 = fLF
MIN
dc
fSystem
40%
60%
35%
65%
50%−
15 ns
50%
50%+
15 ns
50%−
15 ns
50%
50%+
15 ns
40%
2.2 V/3 V
TA0, TA1, TA2; CL = 20 pF, Duty cycle = 50%
MAX
UNIT
fSystem
MHz
60%
30%
fP20 = fLFXT1/n
t(TAdc)
TYP
70%
50%
2.2 V/3 V
0
±50
ns
NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, and P3
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
32
VCC = 2.2 V
P1.0
28
TA = 25°C
24
TA = 85°C
20
16
12
8
4
0
0.0
0.5
1.0
1.5
2.0
50
VCC = 3 V
P1.0
TA = 85°C
30
20
10
0
0.0
2.5
TA = 25°C
40
0.5
1.0
2.0
2.5
3.0
3.5
Figure 3
Figure 2
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
I OH − Typical High-Level Output Current − mA
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
I OH − Typical High-Level Output Current − mA
1.5
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
0
VCC = 2.2 V
P1.0
−4
−8
−12
−16
−20
TA = 85°C
−24
0
VCC = 3 V
P1.0
−10
−20
−30
−40
TA = 85°C
−50
TA = 25°C
TA = 25°C
−28
0.0
0.5
1.0
1.5
2.0
2.5
−60
0.0
Figure 4
1.0
1.5
Figure 5
NOTE: Only one output is loaded at a time.
16
0.5
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
• DALLAS, TEXAS 75265
3.5
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USART (see Note 1)
PARAMETER
t(τ)
( )
TEST CONDITIONS
USART: deglitch time
MIN
TYP
MAX
VCC = 2.2 V
200
430
800
VCC = 3 V
150
280
500
UNIT
ns
NOTE 1: The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD line.
wake-up from lower power modes (LPMx)
PARAMETER
TEST CONDITIONS
MIN
TYP
t(LPM0)
VCC = 2.2 V/3 V
100
t(LPM2)
VCC = 2.2 V/3 V
100
t(LPM3)
Delay time (see Note 1)
t(LPM4)
MAX
UNIT
ns
f(MCLK) = 1 MHz,
VCC = 2.2 V/3 V
6
f(MCLK) = 2 MHz,
VCC = 2.2 V/3 V
6
f(MCLK) = 3 MHz,
VCC = 2.2 V/3 V
6
f(MCLK) = 1 MHz,
VCC = 2.2 V/3 V
6
f(MCLK) = 2 MHz,
VCC = 2.2 V/3 V
6
f(MCLK) = 3 MHz,
VCC = 2.2 V/3 V
6
μs
μ
μs
μ
NOTE 1: Parameter applicable only if DCOCLK is used for MCLK.
RAM
PARAMETER
V(RAMh)
MIN
CPU halted (see Note 1)
1.6
NOM
MAX
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program
execution should happen during this supply voltage condition.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
I(DD)
( )
CAON=1 CARSEL=0,
CAON=1,
CARSEL=0 CAREF=0
CAON=1, CARSEL=0,
CAREF 1/2/3 No load at
CAREF=1/2/3,
P2.3/CA0/TA1 and P2.4/CA1/TA2
I(Refladder/
RefDiode)
V(IC)
V(Ref025)
Common-mode input voltage
Voltage at 0.25 V
V
V(Ref050)
CC
node
CC
Voltage at 0.5V
V
CC
node
CC
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
CAON =1
2.2 V/3 V
0
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.23
0.24
0.25
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0/TA1
P2 3/CA0/TA1 and
P2.4/CA1/TA2, TA = 85°C
VCC−1
UNIT
μA
μA
V
V(RefVT)
(see Figure 6 and Figure 7)
V(offset)
Offset voltage
See Note 2
2.2 V/3 V
−30
30
mV
Vhys
Input hysteresis
CAON=1
2.2 V/3 V
0
0.7
1.4
mV
TA = 25°C,
25 C, Overdrive 10 mV,
Without filter: CAF=0
2.2 V
160
210
300
3V
80
150
240
TA = 25°C,
25 C, Overdrive 10 mV,
With filter: CAF=1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
TA = 25°C,
25 C,
Overdrive 10 mV, without filter: CAF=0
2.2 V
130
210
300
3V
80
150
240
TA = 25°C,
25 C,
Overdrive 10 mV, with filter: CAF=1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
t(response LH)
t(response HL)
mV
ns
μs
ns
μs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
650
650
VCC = 2.2 V
V(REFVT) − Reference Volts −mV
V(REFVT) − Reference Volts −mV
VCC = 3 V
600
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
600
Typical
550
500
450
400
−45
95
−25
TA − Free-Air Temperature − °C
0
15
35
55
75
95
Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 6. V(RefVT) vs Temperature, VCC = 3 V
0V
−5
TA − Free-Air Temperature − °C
VCC
1
CAF
CAON
Low Pass Filter
V+
V−
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 μs
Figure 8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V−
400 mV
V+
t(response)
Figure 9. Overdrive Definition
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PUC/POR
PARAMETER
TEST CONDITIONS
t(POR_Delay)
Internal time delay to release POR
VCC threshold at which POR
release delay time begins
(see Note 1)
TA = −40°C
VPOR
TA = 25°C
V(min)
VCC threshold required to
generate a POR (see Note 2)
VCC |dV/dt| ≥ 1V/ms
t(reset)
RST/NMI low time for PUC/POR
Reset is accepted internally
MIN
VCC = 2.2 V/3 V
TA = 85°C
TYP
MAX
UNIT
150
250
μs
1.4
1.8
V
1.1
1.5
V
0.8
1.2
V
0.2
V
2
μs
NOTES: 1. VCC rise time dV/dt ≥ 1V/ms.
2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less
than −1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms.
V
VCC
V
POR
No POR
POR
V
(min)
POR
t
Figure 10. Power-On Reset (POR) vs Supply Voltage
2.0
1.8
1.8
V POR [V]
1.6
1.5
Max
1.4
1.2
1.2
1.4
1.0
Min
1.1
0.8
0.8
0.6
0.4
0.2
25°C
0
−40
−20
0
20
40
Temperature [°C]
Figure 11. VPOR vs Temperature
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
60
80
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO
PARAMETER
TEST CONDITIONS
f(DCO03)
Rsel = 0,
0 DCO = 3,
3 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
f(DCO13)
Rsel = 1,
1 DCO = 3,
3 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
f(DCO23)
( CO )
Rsel = 2,
2 DCO = 3,
3 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
f(DCO33)
( CO )
Rsel = 3,
3 DCO = 3,
3 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
f(DCO43)
( CO )
Rsel = 4,
4 DCO = 3,
3 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
f(DCO53)
( CO )
Rsel = 5,
5 DCO = 3,
3 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
f(DCO63)
( CO )
Rsel = 6,
6 DCO = 3,
3 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
f(DCO73)
( CO )
Rsel = 7,
7 DCO = 3,
3 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
f(DCO77)
( CO )
Rsel = 7,
7 DCO = 7,
7 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
f(DCO47)
( CO )
Rsel = 4,
4 DCO = 7,
7 MOD = 0,
0 DCOR = 0,
0
TA = 25°C
S(Rsel)
S(DCO)
Dt
Temperature drift,
drift Rsel = 4
4, DCO = 3,
3 MOD = 0 (see Note 1)
DV
Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0
(see Note 1)
VCC
MIN
TYP
MAX
2.2 V
0.08
0.12
0.15
3V
0.08
0.13
0.16
2.2 V
0.14
0.19
0.23
3V
0.14
0.18
0.22
2.2 V
0.22
0.30
0.36
3V
0.22
0.28
0.34
2.2 V
0.37
0.49
0.59
3V
0.37
0.47
0.56
2.2 V
0.61
0.77
0.93
3V
0.61
0.75
0.9
2.2 V
1
1.2
1.5
3V
1
1.3
1.5
2.2 V
1.6
1.9
2.2
3V
1.69
2
2.29
2.2 V
2.4
2.9
3.4
3V
2.7
3.2
3.65
2.2 V
4
4.5
4.9
4.4
4.9
5.4
2 2 V/3 V
2.2
FDCO40
x1.7
FDCO40
x2.1
FDCO40
x2.5
SR = fRsel+1/fRsel
2.2 V/3 V
1.35
1.65
2
SDCO = fDCO+1/fDCO
2.2 V/3 V
1.07
1.12
1.16
2.2 V
−0.31
−0.36
−0.40
3V
−0.33
−0.38
−0.43
0
5
10
3V
2.2 V/3 V
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ratio
%/°C
%/V
f(DCOx7)
f(DCOx0)
Max
Min
Max
Min
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
2.2 V
1
f DCOCLK
Frequency Variance
NOTES: 1. These parameters are not production tested.
3V
0
1
2
VCC
3
4
5
6
7
DCO Steps
Figure 12. DCO Characteristics
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D Individual devices have a minimum and maximum operation frequency. The specified parameters for
f(DCOx0) to f(DCOx7) are valid for all devices.
D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO.
D Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to:
f average +
MOD
32 f (DCO) f (DCO)1)
f (DCO))(32*MOD) f(DCO)1)
DCO when using ROSC (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
fDCO, DCO output frequency
Rsel = 4, DCO = 3, MOD = 0, DCOR = 1,
TA = 25°C
2.2 V
Dt, Temperature drift
Rsel = 4, DCO = 3, MOD = 0, DCOR = 1
Dv, Drift with VCC variation
Rsel = 4, DCO = 3, MOD = 0, DCOR = 1
MIN
NOM
MAX
UNIT
1.8±15%
MHz
1.95±15%
MHz
2.2 V/3 V
±0.1
%/°C
2.2 V/3 V
10
%/V
3V
NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.
crystal oscillator, LFXT1
PARAMETER
CXIN
CXOUT
O
VIL
VIH
Input capacitance
Output capacitance
Input levels at XIN
TEST CONDITIONS
MIN
XTS=0; LF mode selected.
VCC = 2.2 V / 3 V
MAX
pF
2
XTS=0; LF mode selected.
VCC = 2.2 V / 3 V
12
pF
XTS=1; XT1 mode selected.
VCC = 2.2 V / 3 V (see Note 1)
2
VSS
0.2×VCC
0.8×VCC
VCC
NOTES: 1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
12
XTS=1; XT1 mode selected.
VCC = 2.2 V / 3 V (see Note 1)
VCC = 2
2.2
2 V/3 V (see Note 2)
TYP
V
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
TEST
CONDITIONS
PARAMETER
VCC
MIN
NOM
MAX
UNIT
VCC(PGM/
ERASE)
Program and Erase supply voltage
2.7
3.6
V
fFTG
Flash Timing Generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.7 V/ 3.6 V
3
5
mA
IERASE
Supply current from VCC during erase
2.7 V/ 3.6 V
3
7
mA
tCPT
Cumulative program time
see Note 1
2.7 V/ 3.6 V
4
ms
tCMErase
Cumulative mass erase time
see Note 2
2.7 V/ 3.6 V
200
104
Program/Erase endurance
TJ = 25°C
ms
105
tRetention
Data retention duration
tWord
Word or byte program time
35
tBlock, 0
Block program time for 1st byte or word
30
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
5297
tSeg Erase
Segment erase time
4819
cycles
100
years
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine; tFTG = 1/fFTG.
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-down resistance on TEST
see Note 2
VCC
MIN
2.2 V
3V
2.2 V/ 3 V
25
MIN
NOM
MAX
UNIT
0
5
MHz
0
10
MHz
60
90
kΩ
NOM
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TEST pull-down resistor implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse-blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
TA = 25°C
VCC
2.5
6
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
P1SEL.x
0
P1DIR.x
1
Direction Control
From Module
0
P1OUT.x
Pad Logic
1
Module X OUT
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1IN.x
EN
D
Module X IN
P1IRQ.x
P1IE.x
P1IFG.x
Q
Interrupt
Edge
Select
EN
Set
Interrupt
Flag
P1IES.x
P1SEL.x
NOTE: x = Bit/identifier, 0 to 3 for port P1
†
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
VSS
P1IN.0
TACLK†
P1IE.0
P1IFG.0
P1IES.0
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
Out0 signal†
P1IN.1
CCI0A†
P1IE.1
P1IFG.1
P1IES.1
signal†
P1IN.2
CCI1A†
P1IE.2
P1IFG.2
P1IES.2
P1IN.3
CCI2A†
P1IE.3
P1IFG.3
P1IES.3
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
Out2 signal†
Signal from or to Timer_A
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
P1SEL.x
0
P1DIR.x
1
Direction Control
From Module
0
P1OUT.x
Pad Logic
P1.4−P1.7
1
Module X OUT
TST
Bus Keeper
P1IN.x
EN
Module X IN
P1IRQ.x
DVCC
D
P1IE.x
P1IFG.x
Q
Set
Interrupt
Flag
TEST
60 kΩ
Typical
Interrupt
Edge
Select
EN
Control by
JTAG
P1IES.x
P1SEL.x
Bum
and
Test Fuse
P1.x
TDO
Controlled By JTAG
P1.7/TA2/TDO/TDI
Controlled by JTAG
TDI/TCLK
TST
P1.x
P1.6/TA1/TDI/TCLK
NOTE: The test pin should be protected from potential EMI
and ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
TST
P1.x
TMS
P1.5/TA0/TMS
x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing
the fuse, the pin TDO/TDI is used to apply the test
input for JTAG circuitry.
P1Sel.4
P1DIR.4
P1OUT.4
P1.x
P1.4/SMCLK/TCK
SMCLK
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
signal†
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
Out0
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
Out1 signal†
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1OUT.7
signal†
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
P1Sel.7
†
P1DIR.4
TST
TCK
P1DIR.7
P1DIR.7
Out2
Signal from or to Timer_A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.0 to P2.2, input/output with Schmitt-trigger
P2SEL.x
0
P2DIR.x
0: Input
1
Direction Control
From Module
1: Output
Pad Logic
0
P2OUT.x
P2.0/ACLK
P2.1/INCLK
P2.2/CAOUT/TA0
1
Module X OUT
Bus Keeper
P2IN.x
EN
D
Module X IN
CAPD.X
P2IRQ.x
P2IE.x
P2IFG.x
Q
Set
Interrupt
Flag
NOTE: x = Bit identifier, 0 to 2 for port P2
Interrupt
Edge
Select
EN
P2IES.x
P2SEL.x
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
ACLK
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
VSS
P2Sel.2
†
P2DIR.2
P2DIR.2
P2OUT.2
CAOUT
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2IN.0
unused
P2IE.0
P2IFG.0
P1IES.0
P2IN.1
INCLK†
P2IE.1
P2IFG.1
P1IES.1
P2IN.2
CCI0B†
P2IE.2
P2IFG.2
P1IES.2
Signal from or to Timer_A
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3
P2DIR.3
0
Direction Control
From Module
P2OUT.3
0: Input
1
1: Output
0
Pad Logic
P2.3/CA0/TA1
1
Module X
OUT
P2IN.3
Bus Keeper
EN
D
Module X IN
P2IRQ.3
P2IE.3
P2IFG.3
EN
Q
Set
Interrupt
Flag
Interrupt
Edge
Select
CAPD.3
Comparator_A
CAREF P2CA CAEX
P2IES.3 P2SEL.3
CAF
+
_
CCI1B
0V
Interrupt
Flag
P2IFG.4
P2IRQ.4
Q
Set
EN
P2IE.4
P2IES.4 P2SEL.4
CAREF
Interrupt
Edge
Select
Reference Block
CAPD.4
D
Module X IN
EN
Bus Keeper
P2IN.4
Module X OUT
P2OUT.4
0
Pad Logic
Direction Control
From Module
1
1: Output
P2DIR.4
P2SEL.4
0
P2.4/CA1/TA2
0: Input
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
Out1 signal†
P2IN.3
unused
P2IE.3
P2IFG.3
P1IES.3
P2OUT.4
signal†
P2IN.4
unused
P2IE.4
P2IFG.4
P1IES.4
P2Sel.4
†
1
P2DIR.4
P2DIR.4
Out2
Signal from Timer_A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module
P2SEL.5
0: Input
1: Output
0
P2DIR.5
Pad Logic
1
Direction Control
From Module
0
P2OUT.5
P2.5/ROSC
1
Module X OUT
Bus Keeper
P2IN.5
EN
Module X IN
P2IRQ.5
D
P2IE.5
P2IFG.5
Q
EN
Set
Interrupt
Flag
Internal to
Basic Clock
Module
0
VCC
Interrupt
Edge
Select
P2IES.5
1
DC
Generator
DCOR
P2SEL.5
CAPD.5
NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
VSS
P2IN.5
unused
P2IE.5
P2IFG.5
P2IES.5
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, unbonded bits P2.6 and P2.7
P2SEL.x
0: Input
1: Output
0
P2DIR.x
1
Direction Control
From Module
0
P2OUT.x
1
Module X OUT
P2IN.x
Node Is Reset With PUC
EN
Bus Keeper
Module X IN
P2IRQ.x
D
P2IE.x
P2IFG.x
Q
PUC
Interrupt
Edge
Select
EN
Set
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins
P2Sel.x
P2DIR.x
DIRECTIONCONTROL
FROM MODULE
P2OUT.x
MODULE X OUT
P2IN.x
MODULE X IN
P2IE.x
P2IFG.x
P2IES.x
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
VSS
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
VSS
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
NOTE: Unbonded bits 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software
interrupts.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
Pad Logic
P3OUT.x
Module X OUT
0
P3.0/STE0
1
P3.4/UTXD0
P3.5/URXD0
P3.6
P3.7
P3IN.x
EN
D
Module X IN
x: Bit Identifier, 0 and 4 to 7 for Port P3
†
‡
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
P3DIR.0
VSS
P3DIR.4
VCC
P3Sel.5
P3DIR.5
P3Sel.6
P3Sel.7
PnSel.x
PnDIR.x
MODULE X OUT
PnIN.x
P3Sel.0
P3Sel.4
MODULE X IN
P3OUT.0
VSS
P3IN.0
STE0
P3OUT.4
UTXD0†
P3IN.4
Unused
VSS
P3OUT.5
VSS
P3IN.5
URXD0‡
P3DIR.6
VSS
P3OUT.6
VSS
P3IN.6
Unused
P3DIR.7
VSS
P3OUT.7
VSS
P3IN.7
Unused
Output from USART0 module
Input to USART0 module
port P3, P3.1, input/output with Schmitt-trigger
P3SEL.1
SYNC
MM
STC
STE
0
P3DIR.1
0: Input
1: Output
1
DCM_SIMO
Pad Logic
P3.1/SIMO0
0
P3OUT1
(SI)MO0
From USART0
1
P3IN.1
EN
SI(MO)0
To USART0
30
D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.2, input/output with Schmitt-trigger
P3SEL.2
SYNC
MM
STC
STE
0
P3DIR.2
0: Input
1: Output
1
DCM_SOMI
Pad Logic
P3.2/SOMI0
0
P3OUT.2
SO(MI)0
From USART0
1
P3IN.2
EN
(SO)MI0
To USART0
D
port P3, P3.3, input/output with Schmitt-trigger
P3SEL.3
SYNC
MM
STC
STE
0
P3DIR.3
0: Input
1: Output
1
DCM_UCLK
Pad Logic
P3.3/UCLK0
0
P3OUT.3
UCLK.0
From USART0
1
P3IN.3
EN
UCLK0
D
To USART0
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode:
The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from from the TEST pin to ground if
the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing
overall system power consumption.
When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITEST
ITF
Figure 13. Fuse Check Mode Current, MSP430F12x
NOTE:
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader
access key is used. Also see the bootstrap loader section for more information.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430A012IDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F123
MSP430A012IDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F123
MSP430A052IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F123
MSP430A052IPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F123
MSP430F122IDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F122
MSP430F122IDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F122
MSP430F122IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F122
MSP430F122IPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F122
MSP430F122IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F122
MSP430F122IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F122
MSP430F123IDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F123
MSP430F123IDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F123
MSP430F123IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F123
MSP430F123IPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F123
MSP430F123IPWR-HYD
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430F123
MSP430F123IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F123
MSP430F123IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
F123
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
MSP430F122IDWR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
MSP430F122IPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430F122IRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F122IRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F123IDWR
SOIC
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
MSP430F123IPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430F123IRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F123IRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F122IDWR
SOIC
DW
28
1000
367.0
367.0
55.0
MSP430F122IPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
MSP430F122IRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
MSP430F122IRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
MSP430F123IDWR
SOIC
DW
28
1000
367.0
367.0
55.0
MSP430F123IPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
MSP430F123IRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
MSP430F123IRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
Pack Materials-Page 2
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