Anpec APW7290 1.5mhz, 1a synchronous buck regulator Datasheet

APW7290
1.5MHz, 1A Synchronous Buck Regulator
Features
General Description
•
1A Output Current
•
Support 4 AA alkaline, NiCd or NiMH batteries
The APW7290 is a high efficiency monolithic synchronous buck regulator. APW7290 operates with a constant
•
Wide 3.5V~7.2V Input Voltage
•
Fixed 1.5MHz Switching Frequency
•
Low Dropout Operating at 100% duty cycle
•
Low 25µA Quiescent Current
•
Integrate Synchronous Rectifier
•
0.6V Low Reference Voltage
•
<0.5µA Input Current during Shutdown
•
Current-Mode Operation with Internal
1.5MHz switching frequency and using the inductor current as a controlled quantity in the current mode
architecture. The 3.5V to 7.2V input voltage range makes
the APW7290 ideally suited for single Li-Ion battery powered applications. 100% duty cycle provides low dropout
operation, extending battery life in portable electrical
devices. The internally fixed 1.5MHz operating frequency
allows the use of small surface mount inductors and
Compensation
capacitors. The synchronous switches included inside
increase the efficiency and eliminate the need for an ex-
- Stable with Ceramic Output Capacitors
- Fast Line Transient Response
ternal Schottky diode.
The APW7290 is available in TDFN2x2-8 package.
•
Short-Circuit Protection
•
Over-Temperature Protection with Hysteresis
•
Available in TDFN2x2-8 Package
•
Lead Free and Green Devices Available
Pin Configuration
(RoHS Compliant)
GND
VIN
RUN
LBI
Applications
1
8 LBO
2
7 SW
3
6 VOUT
4
5 FB
TDFN2x2-8
(Top View)
•
E-Book
•
Toy
•
Portable Instrument
Simplified Application Circuit
Low Battery
Output
1
2
VIN
C1
ON
3
R4
4
R3
GND
VIN
RUN
LBI
LBO
8
SW
7
VOUT
6
5
FB
L1
VOUT
C2
R1
OFF
R5
R2
APW7290
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jun., 2013
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APW7290
Ordering and Marking Information
Package Code
QB : TDFN2x2-8
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
L : Lead Free Device
APW7290
Assembly Material
Handling Code
Temperature Range
Package Code
APW7290 QB :
W90
X
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
VIN
Input Bias Supply Voltage (VIN to GND)
VSW
SW to GND Voltage
LBO and RUN to GND Voltage
VI/O
PD
LBI and FB to GND Voltage
Power Dissipation
TSDR
Unit
V
-0.3 ~ VIN+0.3
V
-0.3 ~ 8
V
-0.3 ~ 3.3
V
Internally Limited
Maximum Junction Temperature
TSTG
Rating
-0.3 ~ 8
Storage Temperature
Maximum Lead Soldering Temperature (10 Seconds)
W
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
Parameter
θJA
Junction-to-Ambient Resistance in Free Air
θJC
Junction-to-Case Resistance
Typical Value
(Note 2)
Unit
o
TDFN2x2-8
165
TDFN2x2-8
20
C/W
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
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APW7290
Recommended Operating Conditions (Note 3)
Symbol
VIN
VOUT
Parameter
Input Bias Supply Voltage (VIN to GND)
Converter Output Voltage
Range
Unit
3.5 ~ 7.2
V
Adj : 0.6 ~ 6
Fixed : 1.8
V
IOUT
Converter Output Current
0~1
A
L1
Converter Output Inductor
1.0 ~ 10
µH
CIN
Converter Input Capacitor
4.7 ~
µF
4.7 ~
µF
COUT
TA
TJ
Converter Output Capacitor
Ambient Temperature
Junction Temperature
-40 ~ 85
o
-40 ~ 125
o
C
C
Note 3: Refer to the typical application circuit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=5V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
Test Conditions
APW7290
Unit
Min
Typ
Max
3.5
-
7.2
V
SUPPLY VOLTAGE AND CURRENT
VIN
Input Voltage Range
IDD
Quiescent Current
VFB = 0.66V
-
25
40
µA
ISD
Shutdown Input Current
RUN = GND
-
-
0.5
µA
POWER-ON-RESET (POR) and LOCKOUT VOLTAGE THRESHOLDS
UVLO Threshold
3.0
3.2
3.4
V
UVLO Hysteresis
-
200
-
mV
0.588
0.6
0.612
V
-2.5
-
+2.5
%
-50
-
50
nA
1.764
1.8
1.836
V
REFERENCE VOLTAGE
VREF
IFB
VOUT
Regulated Voltage
VIN=3.5V~7.2V, TA = -40~85 oC,
Output Voltage Accuracy
0A < IOUT < 1A
FB Input Current
Output Voltage
FB=GND, No Load
INTERNAL POWER MOSFETS
FSW
Switching Frequency
VFB = 0.6V
1.2
1.5
1.8
MHz
Fold Back Frequency
VFB = 0.1V
-
210
-
KHz
Fold Back Voltage on FB
VFB Falling
-
0.2
-
V
Fold Back
VFB Rising
-
120
-
mV
Hysteresis
RP-FET
High Side P-FET Switch ON
Resistance
ISW =200mA
-
0.28
-
Ω
RN-FET
Low Side N-FET Switch ON
Resistance
ISW =200mA
-
0.25
-
Ω
Minimum On-Time
-
-
100
ns
Maximum Duty Cycle
-
-
100
%
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APW7290
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=5V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
Test Conditions
APW7290
Min
Typ
Max
1.4
1.6
-
Unit
PROTECTION
ILIM
Maximum Inductor Current Limit
IP-FET, 3.5V≦VIN≦7.2V
TOTP
Over-Temperature Protection
TJ Rising
-
150
-
Over-Temperature Protection
Hysteresis
TJ Falling
-
30
-
Soft-start Duration
(Note 4)
-
0.7
-
ms
RUN Input High Threshold
VIN = 3.5V~7.2V
-
-
1
V
RUN Input Low Threshold
VIN = 3.5V~7.2V
0.4
-
-
V
RUN Leakage Current
VRUN = 5V, VIN = 5V
-1
-
1
µA
0.588
0.6
0.612
V
-
1
50
nA
-
10
-
mV
A
°C
START-UP AND SHUTDOWN
TSS
VLBI
LBI Threshold
ILBI
LBI Input Current
VLBI=0.8V
LBI Input Hysteresis
VLBO
LBO Logic Low
VLBI=3.3V, ISINK=1mA
-
0.2
0.4
V
ILBO
LBO Off Leakage Current
VLBO=5.5V, VLBI=0V
-
0.07
1
µA
Note 4: Guarantee by design, not production test.
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APW7290
Typical Operating Characteristics
Vin Input Voltage vs. Shutdown
Current
Vin Input Voltage vs. Quiescent
Current
1
40
0.8
30
Shutdown Current (uA)
Quiescent Current (uA)
35
25
20
15
10
0.6
0.4
0.2
5
0
0
3
3.5
4
4.5
5
5.5
6
6.5
7
3
3.5
4
Vin Input Voltage (V)
5
5.5
6
6.5
7
Temperature vs. Frequency
Temperature vs. Feedback Voltage
1.8
0.62
0.615
1.7
0.61
Frequency (MHz)
Feedback Voltage(V)
4.5
Vin Input Voltage (V)
0.605
0.6
0.595
1.6
1.5
1.4
0.59
1.3
0.585
0.58
-60 -40 -20
1.2
0
20
40
60
-40
80 100 120 140
-20
0
20
40
60
80
100 120 140
Temperature (oC)
o
Temperature ( C)
Io vs. Efficiency
100.0
95.0
Efficiency (%)
90.0
85.0
80.0
75.0
70.0
65.0
60.0
Vo=3V,L=2.2uH,Cin=10u
F,Co=10uF
55.0
50.0
0
Vin=4V
Vin=5.5V
Vin=7V
100 200 300 400 500 600 700 800 900 1000
Io(mA)
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APW7290
Operating Waveforms
Power on EN
Power off EN
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
CH1:VIN-2V/div
CH2:VOUT-1V/div
CH3:SW-5V/div
CH4:IL-500mA/div
Time:100us/div
CH1:VIN-2V/div
CH2:VOUT-1V/div
CH3:SW-5V/div
CH4:IL-500mA/div
Time:1s/div
Normal Operation
CH1
CH2
CH3
CH4
CH1:VIN-2V/div
CH2:VOUT-1V/div
CH3:SW-5V/div
CH4:IL-1A/div
Time:500ns/div
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APW7290
Pin Description
PIN
Function
NO.
NAME
1
GND
Power and Signal Ground.
2
VIN
Device and Converter Supply Pin. Must be closely decoupled to GND with a 4.7µF or greater ceramic
capacitor.
3
RUN
Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this pin below 0.4V shuts
it down. In shutdown, all functions are disabled to decrease the supply current below 0.5µA. Do not
leave RUN pin floating.
4
LBI
Low-battery comparator input. Internally set to trip at 0.6V.
5
FB
Feedback Input Pin and output voltage select Pin. The buck regulator senses feedback voltage via FB
and regulates the FB voltage at 0.6V. Connecting FB with a resistor-divider from the output sets the
output voltage of the buck converter. If FB connects to GND, VOUT is fixed 1.8V.
6
VOUT
7
SW
Switch Node Connected to Inductor. This pin connects to the drains of the internal main and
synchronous power MOSFETs switches.
8
LBO
Open-drain low battery comparator output. Connect LBO to OUT through a 100kΩ resistor. LBO is low
as VLBI < 0.6V. Open-drain device is turned off during shutdown.
Output Voltage. Output voltage feedback input if FB pin is connected to VOUT or GND.
Block Diagram
Current Sense
Amplifier
VIN
Shutdown
Control
RUN
Logic Control
SW
OverTemperature
Protection
Gate
Driver
Current
Limit
Slope
Compensation
∑
Oscillator
Zero-Crossing
Comparator
GND
COMP
ICMP
Error
Amplifier
LBO
EAMP
FB
VOUT
Selector
VOUT
LBI
Softstart
0.6V
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VREF
0.6V
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APW7290
Typical Application Circuit
Toy Application
Low Battery
Output
1
VIN
3.6 ~7.2V
2
C1
10µF/6.3 V/X 5R
(MLCC)
ON
3
10 k
4
100k
GND
VIN
LBO
8
RUN
SW
7
VOUT
6
5
LBI
FB
OFF
10 k
APW7290
L1
2.2µH
R1
R2 45k
10 k
VOUT
3.3V/1A
C2
10µF/6.3 V/X 5R
(MLCC)
R1 ≤ 900 KΩ is recommended
R2 ≤ 200 KΩ is recommended
E-Book Application
Low Battery Output
1
V IN
3.6~7.2V
2
C1
10µF/6.3 V/X 5R
(MLCC)
ON
3
10k
4
100 k
GND
VIN
RUN
LBO
SW
VOUT
LBI
FB
8
7
6
5
L1
2.2µH
V OUT
1.8V /300 mA
C2
10µF/6.3V/X5R
(MLCC)
OFF
10k
APW7290
Power Sequence: a. VIN Rise up -> RUN Rise up b. RUN Rise up -> VIN Rise up
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APW7290
Function Description
Main Control Loop
tion to reduce the dominant switching losses. In PFM
The APW7290 is a constant frequency, synchronous rec-
operation, the inductor current may reach zero or reverse
on each pulse. A zero current comparator turn off the N-
tifier and current-mode switching regulator. In normal
operation, the internal P-channel power MOSFET is
FET, forcing DCM operation at light load. These controls
get very low quiescent current, help to maintain high effi-
turned on each cycle. The peak inductor current at which
ICMP turn off the P-FET is controlled by the voltage on the
ciency over the complete load range.
COMP node, which is the output of the error amplifier
(EAMP). An external resistive divider connected between
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscil-
VOUT and ground allows the EAMP to receive an output
feedback voltage VFB at FB pin. When the load current
lations at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
increases, it causes a slightly decrease in VFB relative to
the 0.6V reference, which in turn causes the COMP volt-
signal at duty cycles in excess of 40%. Normally, the result is in a reduction of maximum inductor peak current
age to increase until the average inductor current matches
the new load current.
Under-Voltage Lockout
for duty cycles > 40%. However, the APW7290 uses a
special scheme that counteracts this compensating
An under-voltage lockout function prevents the device from
operating if the input voltage on VIN is lower than approxi-
ramp, which allows the maximum inductor peak current
to remain unaffected throughout all duty cycles.
mately 3V (Typ.). The device automatically enters the shutdown mode if the voltage on VIN drops below approxi-
Adaptive Shoot-Through Protection
mately 3V. This under-voltage lockout function is implemented in order to prevent the malfunctioning of the
The gate driver incorporates adaptive shoot-through pro-
converter.
tection to high-side and low-side MOSFETs from conducting simultaneously and shorting the input supply.
This is accomplished by ensuring the falling gate has
turned off one MOSFET before the other is allowed to
Soft-Start
The APW7290 has a built-in soft-start to control the output voltage rise during start-up. During soft-start, an in-
rise.
During turn-off the low-side MOSFET, the internal LGATE
ternal ramp voltage, connected to the one of the positive
inputs of the error amplifier, raises up to replace the ref-
voltage is monitored until it below 1.5V threshold, at which
time the UGATE is released to rise after a constant delay.
erence voltage (0.6V typical) until the ramp voltage
reaches the reference voltage. Then the voltage on FB
During turn-off the high-side MOSFET, the UGATE voltage is also monitored until it above 1.5V threshold, at
regulated at reference voltage.
which time the LGATE is released to rise after a constant
delay.
Enable/Shutdown
Driving RUN to ground places the APW7290 in shutdown
mode. When in shutdown, the internal power MOSFETs
Dropout Operation
As the input supply voltage decreases to a value ap-
turn off, all internal circuitry shuts down and the quiescent supply current reduces to 0.5µA maximum.
proaching the output voltage, the duty cycle increases
toward the maximum on time. Further reduction of the
Pulse Frequency Modulation Mode (PFM)
The APW7290 is a fixed frequency, peak current mode
supply voltage forces the main switch to remain on for
more than one cycle until it reaches 100% duty cycle. The
PWM step-down converter. At light loads, the APW7290
will automatically enter in pulse frequency mode opera-
output voltage will then be determined by the input voltage minus the voltage drop across the P-FET and the
inductor.
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APW7290
Function Description (Cont.)
Dropout Operation (Cont.)
An important detail to remember is that on resistance of
P-FET switch will increase at low input supply voltage.
Therefore, the user should calculate the power dissipation when the APW7290 is used at 100% duty cycle with
low input voltage.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction temperature of the APW7290. When the junction temperature exceeds 150oC, a thermal sensor turns off the both power
MOSFETs, allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and
regulate the output voltage again after the junction temperature cools by 30oC. The OTP designed with a 30oC
hysteresis lowers the average Junction Temperature (TJ)
during continuous thermal overload conditions, increasing the life time of the device.
Short-Circuit Protection
When the output is shorted to ground, the frequency of
the oscillator is reduced to about 210 kHz, 1/7 of the nominal frequency. This frequency fold back ensures that the
inductor current has more time to decay, thereby preventing runaway. The oscillator’s frequency will progressively
increase to 1.5MHz when VFB or VOUT rises above 0V.
Low Battery Detection
The low battery detection is used to monitor the battery
voltage and to generate a signal. This function includes
two pins, LBI is the inverting input of the comparator and
LBO is an open drain output (See Block Diagram). When
the LBI voltage drops below the threshold voltage 0.6V,
the open drain device will turn on and LBO becomes low.
The Low battery threshold voltage can be programmed
with a resistive divider from battery to LBI pin to the round.
Since the LBO is an open drain output, it usually requires
an external pull-up resistor.
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APW7290
Application Information
Input Capacitor Selection
shown in “Typical Application Circuits”. A suggestion of
Because buck converters have a pulsating input current,
a low ESR input capacitor is required. This results in the
maximum value of R2 is 200kΩ to keep the minimum
current that provides enough noise rejection ability through
best input voltage filtering, minimizing the interference
with other circuits caused by high input voltage spikes.
the resistor divider. The output voltage can be calculated
as below:
R1 
R1 


VOUT = VREF ⋅  1 +
 = 0.6 ⋅ 1 +

R2 
R2 


Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For
good input voltage filtering, usually a 4.7µF input capacitor is sufficient. It can be increased without any limit for
VOUT
better input-voltage filtering. Ceramic capacitors show
better performance because of the low ESR value, and
R1≤1MΩ
they are less sensitive against voltage transients and
spikes compared to tantalum capacitors. Place the input
FB
R2 ≤ 200kΩ
APW7290
capacitor as close as possible to the input and GND pin of
the device for better performance.
GND
Inductor Selection
Output Capacitor Selection
For high efficiencies, the inductor should have a low DC
The current-mode control scheme of the APW7290 allows the use of tiny ceramic capacitors. The higher ca-
resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a
pacitor value provides the good load transients response.
higher impact on efficiency. When using small chip
inductors, the efficiency is reduced mainly due to higher
Ceramic capacitors with low ESR values have the lowest
output voltage ripple and are recommended. If required,
inductor core losses. This needs to be considered when
selecting the appropriate inductor. The inductor value de-
tantalum capacitors may be used as well. The output
ripple is the sum of the voltages across the ESR and the
termines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the
ideal output capacitor.
lower the conduction losses of the converter. Conversely,
larger inductor values cause a slower load transient
∆VOUT
response. A reasonable starting point for setting ripple
current, ∆IL, is 40% of maximum output current. The rec-

V
VOUT ⋅ 1 − OUT
VIN

≅
FSW ⋅ L


 
1
 ⋅  ESR +

⋅
8
F
SW ⋅ COUT





When choosing the input and output ceramic capacitors,
ommended inductor value can be calculated as below:
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-


V
VOUT 1 − OUT 
V
IN 

L≥
FSW ⋅ ∆IL
acteristics of all the ceramics for a given value and size.
VIN
IL(MAX) = IOUT(MAX) + 1/2 x ∆IL
IIN
IP-FET
To avoid the saturation of the inductor, the inductor should
IL
be rated at least for the maximum output current of the
converter plus the inductor ripple current.
CIN
Output Voltage Setting
P-FET
VOUT
SW
N-FET
In the adjustable version, the output voltage is set by a
resistive divider. The external resistive divider is con-
IOUT
ESR
COUT
nected to the output, allowing remote voltage sensing as
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APW7290
Application Information (Cont.)
Output Capacitor Selection (Cont.)
The maximum power dissipation on the device can be
shown as follow figure:
IL
0.8
Maximum Power Disspation(W)
ILIM
IPEAK
∆IL
IOUT
IP-FET
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50
-25
0
25
50
75
100
125
150
Junction Temperature(oC)
Thermal Consideration
In most applications, the APW7290 does not dissipate
much heat due to its high efficiency. But, in applications
Layout Consideration
For all switching power supplies, the layout is an important step in the design; especially at high peak currents
where the APW7290 is running at high ambient temperature with low supply voltage and high duty cycles, the heat
and switching frequencies. If the layout is not carefully
dissipated may exceed the maximum junction tempera-
done, the regulator might show noise problems and duty
cycle jitter.
ture of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned
1. The input capacitor should be placed close to the VIN
and GND. Connecting the capacitor and VIN/GND with
off and the SW node will become high impedance.
To avoid the APW7290 from exceeding the maximum junc-
short and wide trace without any via holes for good
input voltage filtering. The distance between VIN/GND
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to deter-
to capacitor less than 2mm respectively is
recommended.
mine whether the power dissipated exceeds the maximum junction temperature of the part. The power dissi-
2. To minimize copper trace connections that can inject
noise into the system, the inductor should be placed
pated by the part is approximated:
PD ≅ IOUT2 x (RP-FET x D+RN-FET x (1-D))
as close as possible to the SW pin to minimize the
noise coupling into other circuits.
The temperature rise is given by:
3. The output capacitor should be place closed to converter VOUT and GND.
TR = (PD)(θJA)
Where PD is the power dissipated by the regulator, D is
duty cycle of main switch
4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed
D = VOUT/VIN
away from the inductor. The feedback pin and feedback network should be shielded with a ground plane
The θJA is the thermal resistance from the junction of the
die to the ambient temperature. The junction temperature,
or trace to minimize noise coupling into this circuit.
5. A star ground connection or ground plane minimizes
TJ, is given by:
ground shifts and noise is recommended.
TJ = TA + TR
Where TA is the ambient temperature.
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APW7290
Application Information (Cont.)
Recommended Minimum Footprint
The via diameter =0.012
Hole size =0.008
0.009
0.022
0.051
0. 012
0.02
0.032
Unit:
Inch
layout
The via diameter =0.012
Hole size =0.008
0.225
0.54
1.3
0.3
0.5
0.8
Unit:
mm
layout
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jun., 2013
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APW7290
Package Information
TDFN2x2-8
A
b
E
D
A1
D2
A3
L
E2
Pin 1 Cornar
e
S
Y
M
B
O
L
TDFN2x2-8
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.007
0.012
D
1.90
2.10
0.075
0.083
D2
1.00
1.60
0.039
0.063
E
1.90
2.10
0.075
0.083
E2
0.60
1.00
0.024
0.039
e
L
0.50 BSC
0.30
0.020 BSC
0.012
0.45
0.018
Note : 1. Followed from JEDEC MO-229 WCCD-3.
Copyright  ANPEC Electronics Corp.
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APW7290
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TDFN2x2-8
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.20
1.75±0.10
3.50±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
3.35 MIN
3.35 MIN
1.30±0.20
4.0±0.10
4.0±0.10
1.5 0.6+0.00
MIN.
-0.4
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TDFN2x2-8
Tape & Reel
3000
Copyright  ANPEC Electronics Corp.
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15
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APW7290
Taping Direction Information
TDFN2x2-8
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
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APW7290
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
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Rev. A.2 - Jun., 2013
17
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW7290
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jun., 2013
18
www.anpec.com.tw
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