ON MC14017B Decade counter Datasheet

MC14017B
Decade Counter
The MC14017B is a five−stage Johnson decade counter with
built−in code converter. High speed operation and spike−free outputs
are obtained by use of a Johnson decade counter design. The ten
decoded outputs are normally low, and go high only at their
appropriate decimal time period. The output changes occur on the
positive−going edge of the clock pulse. This part can be used in
frequency division applications as well as decade counter or decimal
decode display applications.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
Fully Static Operation
DC Clock Input Circuit Allows Slow Rise Times
Carry Out Output for Cascading
Divide−by−N Counting
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4017B
Triple Diode Protection on All Inputs
Pb−Free Packages are Available*
PDIP−16
P SUFFIX
CASE 648
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Vin, Vout
Iin, Iout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
1
16
14017BG
AWLYWW
1
16
Value
VDD
Parameter
MC14017BCP
AWLYYWWG
SOIC−16
D SUFFIX
CASE 751B
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
16
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
SOEIAJ−16
F SUFFIX
CASE 966
MC14017B
ALYWG
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
1
Publication Order Number:
MC14017B/D
MC14017B
PIN ASSIGNMENT
Q5
1
16
VDD
Q1
2
15
RESET
Q0
3
14
CLOCK
Q2
4
13
CE
Q6
5
12
Cout
Q7
6
11
Q9
Q3
7
10
Q4
VSS
8
9
Q8
FUNCTIONAL TRUTH TABLE
(Positive Logic)
Clock
Clock
Enable
0
X
X
X
1
X
0
X
X
1
BLOCK DIAGRAM
Reset
Decode
Output=n
0
0
1
0
0
0
0
n
n
Q0
n+1
n
n
n+1
CLOCK 14
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Cout
CLOCK
13
ENABLE
RESET 15
X = Don’t Care. If n < 5 Carry = “1”,
Otherwise = “0”.
3
2
4
7
10
1
5
6
9
11
12
VDD = PIN 16
VSS = PIN 8
LOGIC DIAGRAM
Q5
Q1
1
2
C Q
C
D Q
R R
C Q
C
D Q
R R
Q7
6
Q3
7
Q9
11
14
CLOCK
CLOCK
ENABLE
RESET
13
15
3
C Q
C
D Q
R R
5
Q0
4
Q6
Q2
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2
C Q
C
D Q
R R
C Q
C
D Q
R R
9
10
Q3
Q4
12
CARRY
MC14017B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
“1” Level
VIH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
mAdc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (0.27 mA/kHz) f + IDD
IT = (0.55 mA/kHz) f + IDD
IT = (0.83 mA/kHz) f + IDD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0011.
ORDERING INFORMATION
Package
Shipping †
MC14017BCP
PDIP−16
500 Units / Rail
MC14017BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14017BD
SOIC−16
48 Units / Rail
MC14017BDR2
SOIC−16
2500 Units / Tape & Reel
MC14017BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
SOEIAJ−16
2000 Units / Tape & Reel
Device
MC14017BFEL
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
MC14017B
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time
Reset to Decode Output
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/PF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
tPLH,
tPHL
Propagation Delay Time
Clock to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns
tPLH, tPHL = (0.5 ns/pF) CL + 100 ns
tPLH,
tPHL
Propagation Delay Time
Clock to Decode Output
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
tPLH,
tPHL
Turn−Off Delay Time
Reset to Cout
tPLH = (1.7 ns/pF) CL + 315 ns
tPLH = (0.66 ns/pF) CL + 142 ns
tPLH = (0.5 ns/pF) CL + 100 ns
tPLH
Clock Pulse Width
VDD
Vdc
Min
Typ
(Note 6)
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
—
—
—
500
230
175
1000
460
350
ns
5.0
10
15
—
—
—
400
175
125
800
350
250
ns
5.0
10
15
—
—
—
500
230
175
1000
460
350
ns
5.0
10
15
—
—
—
400
175
125
800
350
250
tw(H)
5.0
10
15
250
100
75
125
50
35
—
—
—
ns
fcl
5.0
10
15
—
—
—
5.0
12
16
2.0
5.0
6.7
MHz
Reset Pulse Width
tw(H)
5.0
10
15
500
250
190
250
125
95
—
—
—
ns
Reset Removal Time
trem
5.0
10
15
750
275
210
375
135
105
—
—
—
ns
Clock Input Rise and Fall Time
tTLH,
tTHL
5.0
10
15
Clock Enable Setup Time
tsu
5.0
10
15
350
150
115
175
75
52
—
—
—
ns
Clock Enable Removal Time
trem
5.0
10
15
420
200
140
260
100
70
—
—
—
ns
Clock Frequency
—
No Limit
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14017B
VDD
VSS
VDD
VSS
A
B
S1
S1
Vout
CLOCK Q0
ENABLE
Q1
Q2
Q3
Q4
RESET Q5
Q6
Q7
Q8
Q9
CLOCK Cout
Output
Sink Drive
Output
Source Drive
Decode
Outputs
(S1 to A)
Clock to
desired
outputs
(S1 to B)
Carry
Clock to 5
thru 9
(S1 to B)
S1 to A
VGS =
VDD
− VDD
VDS =
Vout
Vout − VDD
ID
EXTERNAL
POWER
SUPPLY
VSS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
0.01 mF
CERAMIC
ID
500 mF
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Cout
CLOCK
ENABLE
RESET
PULSE
GENERATOR
fc
CLOCK
VSS
CL
CL
CL
CL
CL
Figure 2. Typical Power Dissipation Test Circuit
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5
CL
CL
CL
CL
CL
CL
MC14017B
APPLICATIONS INFORMATION
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
RESET
CLOCK
CE MC14017B
RESET
CLOCK
CE MC14017B
Q0 Q1 • • • Q8 Q9
Q0Q1 • • • Q8 Q9
9 DECODED
OUTPUTS
CLOCK
RESET
CLOCK
CE MC14017B
Q1 • • • Q8 Q9
8 DECODED
OUTPUTS
8 DECODED
OUTPUTS
FIRST STAGE
INTERMEDIATE STAGES
LAST STAGE
Figure 3. Counter Expansion
Pcp
Ncp
CLOCK
trem
CLOCK
ENABLE
trem
RESET
20 ns
Q0
Q2
Q3
Q4
Q5
Q6
Q7
Cout
10%
20 ns
20 ns
VDD
VSS
tPLH
tTLH
tPHL
90%
10%
tPHL
tPLH
tTHL
tTLH
VOH
VOL
tTHL
VOH
50%
tPLH
tPHL
tPLH
tTLH
tPHL
tPLH
tTHL
tTHL
tTLH
tTLH
tPHL
tTHL
tTHL
tPHL
tPLH
tTHL
VOL
tTHL
tPHL
90%
10%
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
tPLH
tTLH
VOH
VOL
VOH
VOL
50%
tTLH
tPHL
VDD
VSS
VSS
20 ns
tPLH
tPLH
50%
VDD
20 ns
tPHL
Q8
Q9
tsu
20 ns
tPLH
Q1
90%
tTHL
tPLH
tTLH
tPHL
tPHL
tPLH
tTHL
tPHL
tTLH
Figure 4. AC Measurement Definition and Functional Waveforms
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6
tTHL
VOH
VOL
VOH
VOL
MC14017B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
−T−
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
T A
M
M
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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7
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14017B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE O
16
LE
9
Q1
M_
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.031
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC14017B/D
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