Burr-Brown ADS5542 14-bit, 80msps analog-to-digital converter Datasheet

 SBAS308A − MAY 2004 − REVISED MARCH 2005
D Pin-Compatible with:
FEATURES
D
D
D
D
D
D
D
D
−
−
−
−
−
14-Bit Resolution
80MSPS Sample Rate
High SNR: 72.9dBFS at 100 MHz fIN
High SFDR: 88dBc at 100 MHz fIN
ADS5500 (14-Bit, 125MSPS)
ADS5541 (14-Bit, 105MSPS)
ADS5520 (12-Bit, 125MSPS)
ADS5521 (12-Bit, 105MSPS)
ADS5522 (12-Bit, 80MSPS)
APPLICATIONS
D Wireless Communication
2.3VPP Differential Input Voltage
Internal Voltage Reference
− Communication Receivers
− Base Station Infrastructure
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Communication Instrumentation
− Radar, Infrared
Video and Imaging
Medical Equipment
Military Equipment
3.3V Single-Supply Voltage
D
D
D
Analog Power Dissipation: 545mW
− Output Buffer Power: 129mW
D TQFP-64 PowerPADE Package
D Recommended Op Amps:
D
D
D
THS3202, THS3201, THS4503,
OPA695, OPA847
DESCRIPTION
The ADS5542 is a high-performance, 14-bit, 80MSPS analog-to-digital converter (ADC). To provide a complete converter
solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for
applications demanding the highest speed and highest dynamic performance in very little space, the ADS5542 has
excellent analog power dissipation of 545mW and output buffer power dissipation of 129mW from a 3.3V single-supply
voltage. This allows an even higher system integration density. The provided internal reference simplifies system design
requirements. Parallel CMOS compatible output ensures seamless interfacing with common logic.
The ADS5542 is available in a 64-pin TQFP PowerPAD package and is pin-compatible with the ADS5500, ADS5541,
ADS5520, ADS5521, and ADS5522. This device is specified over the full temperature range of −40°C to +85°C.
AVDD
DRVDD
CLK+
VIN+
S&H
VIN−
CM
CLKOUT
Timing Circuitry
CLK−
14−Bit
Pipeline
ADC Core
Output
Control
Serial Programming Register
ADS5542
SCLK
DRGND
SEN
SDATA
D0
.
.
.
D13
OVR
DFS
Control Logic
Internal
Reference
AGND
Digital
Error
Correction
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
Copyright  2004−2005, Texas Instruments Incorporated
!" # $% # ! &%'$ () (%$#
$!" #&$!$# & * "# ! +# #%"# #(( ,-)
(%$ &$## (# $##- $%( # ! &"#)
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SBAS308A − MAY 2004 − REVISED MARCH 2005
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE−LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5542
HTQFP-64(2)
PowerPAD
PAP
−40°C to +85°C
ADS5542I
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5542IPAP
Tray, 160
ADS5542IPAPR
Tape and Reel, 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website
at www.ti.com.
(2) Thermal pad size: 3.5mm x 3.5mm (min), 4mm x 4mm (max). θJA = 21.47°C/W and θJC = 2.99°C/W, when used with 2oz. copper trace and pad
soldered directly to a JEDEC standard 4 layer 3in x 3in PCB.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted(1)
ADS5542
UNIT
−0.3 to +3.7
V
±0.1
V
−0.3 to +3.6
V
Logic input to DRGND
−0.3 to DRVDD
V
Digital data output to DRGND
−0.3 to DRVDD
V
Supply
Voltage
AVDD to AGND,
DRVDD to DRGND
AGND to DRGND
Analog input to AGND(2)
Operating temperature range
Junction temperature
Storage temperature range
MIN
TYP
MAX
UNIT
Analog supply voltage, AVDD
3.0
3.3
3.6
V
Output driver supply voltage, DRVDD
3.0
3.3
3.6
V
Supplies
Analog Input
Differential input range
Input common-mode voltage, VCM(1)
−40 to +85
°C
Digital Output
+105
°C
Maximum output load
−65 to +150
°C
Clock Input
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) For more detail, refer to Input Voltage Overstress in the
Application Information section.
2
PARAMETER
2.3
1.47
1.67
10
ADCLK input sample rate (sine
wave) 1/tC
10
Clock amplitude, sine wave,
differential(2)
1
Clock duty cycle(3)
1.57
VPP
V
pF
80
MSPS
3
VPP
50
%
Open free-air temperature range
−40
+85
(1) Input common-mode should be connected to CM.
(2) See Figure 46 for more information.
(3) See Figure 45 for more information.
°C
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SBAS308A − MAY 2004 − REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
CONDITIONS
PARAMETER
MIN
Resolution
TYP
MAX
UNIT
14
Bits
2.3
VPP
4
pF
200
µA
Analog Inputs
Differential input range
Differential input capacitance
See Figure 37
Analog input common-mode current (per
input)
Analog input bandwidth
Source impedance = 50Ω
750
MHz
4
Clock Cycles
Reference bottom voltage, VREFM
1.0
V
Reference top voltage, VREFP
2.15
Voltage overload recovery time
Internal Reference Voltages
Reference error
−4
Common-mode voltage output, VCM
±0.6
V
+4
1.575
%
V
Dynamic DC Characteristics and Accuracy
No missing codes
Tested
Differential nonlinearity error, DNL
fIN = 10MHz
−0.9
±0.5
1.1
LSB
Integral nonlinearity error, INL
fIN = 10MHz
−5.0
±2.0
+5.0
LSB
Offset error
±1.5
mV
Offset temperature coefficient
0.02
mV/°C
0.25
mV/V
DC power supply rejection ratio, DC PSRR
∆offset error/∆AVDD from
AVDD = 3.0V to AVDD = 3.6V
Gain error
±0.3
%FS
Gain temperature coefficient
−0.02
∆%/°C
Dynamic AC Characteristics
+25°C to +85°C
72.7
74.3
dBFS
Full temp range
71.5
74.0
dBFS
73.7
dBFS
+25°C to +85°C
71.5
73.5
dBFS
Full temp range
70.0
73.0
dBFS
fIN = 100MHz
72.9
dBFS
fIN = 150MHz
71.9
dBFS
fIN = 220MHz
70.7
dBFS
Input tied to common-mode
1.1
LSB
fIN = 10MHz
fIN = 55MHz
Signal-to-noise ratio, SNR
RMS idle channel noise
fIN = 70MHz
Room temp
80.0
92.0
dBc
Full temp range
78.0
90.0
dBc
88.0
dBc
Room temp
80.0
87.0
dBc
Full temp range
78.0
86.0
dBc
fIN = 100MHz
88.0
dBc
fIN = 150MHz
85.0
dBc
fIN = 220MHz
77.0
dBc
fIN = 10MHz
fIN = 55MHz
Spurious-free dynamic range, SFDR
fIN = 70MHz
3
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SBAS308A − MAY 2004 − REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
PARAMETER
CONDITIONS
fIN = 10MHz
MIN
TYP
Room temp
80.0
92.0
dBc
Full temp range
78.0
90.0
dBc
88.0
dBc
fIN = 55MHz
Second-harmonic, HD2
80.0
87.0
dBc
Full temp range
78.0
86.0
dBc
fIN = 100MHz
88.0
dBc
fIN = 150MHz
85.0
dBc
fIN = 220MHz
77.0
dBc
fIN = 70MHz
Room temp
80.0
89.0
dBc
Full temp range
78.0
88.0
dBc
79.0
dBc
fIN = 55MHz
Worst-harmonic/spur
(other than HD2 and HD3)
Room temp
80.0
85.0
dBc
Full temp range
78.0
83.0
dBc
fIN = 100MHz
83.0
dBc
fIN = 150MHz
80.0
dBc
fIN = 220MHz
76.0
dBc
dBc
fIN = 70MHz
fIN = 10MHz
Room temp
88.0
fIN = 70MHz
Room temp
87.0
dBc
fIN = 10MHz
+25°C to +85°C
72.2
73.8
dBFS
Full temp range
71.0
73.5
dBFS
73.2
dBFS
fIN = 55MHz
Signal-to-noise + distortion, SINAD
fIN = 70MHz
+25°C to +85°C
71.0
73.2
dBFS
Full temp range
69.5
72.5
dBFS
fIN = 100MHz
72.5
dBFS
fIN = 150MHz
71.8
dBFS
fIN = 220MHz
69.8
dBFS
fIN = 10MHz
Room temp
78.0
90.0
dBc
Full temp range
76.0
88.0
dBc
83.4
dBc
fIN = 55MHz
Total harmonic distortion, THD
Effective number of bits, ENOB
Two-tone intermodulation distortion, IMD
4
UNIT
Room temp
fIN = 10MHz
Third-harmonic, HD3
MAX
Room temp
78.0
86.0
dBc
Full temp range
76.0
84.0
dBc
fIN = 100MHz
83.4
dBc
fIN = 150MHz
81.2
dBc
fIN = 220MHz
75.8
dBc
fIN = 70MHz
11.9
Bits
f = 10.1MHz, 15.1MHz
(−7dBFS each tone)
93.8
dBFS
f = 50.1MHz, 55.1MHz
(−7dBFS each tone)
92.4
dBFS
f = 148.1MHz, 153.1MHz
(−7dBFS each tone)
92.6
dBFS
fIN = 70MHz
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SBAS308A − MAY 2004 − REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
Total supply current, ICC
fIN = 70MHz
204
230
mA
Analog supply current, IAVDD
fIN = 70MHz
165
180
mA
Output buffer supply current, IDRVDD
fIN = 70MHz
39
50
mA
Analog only
545
594
mW
Power dissipation
Output buffer power with 10pF load on
digital output to ground
129
165
mW
Standby power
With clocks running
180
250
mW
MAX
UNIT
DIGITAL CHARACTERISTICS
Valid over full temperature range of TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
Digital Inputs
High-level input voltage, VIH
2.4
V
Low-level input voltage, VIL
0.8
V
High-level input current, IIH
10
µA
Low-level input current, IIL
10
µA
Input current for RESET
Input capacitance
−20
µA
4
pF
Digital Outputs
Low-level output voltage, VOL
CLOAD = 10pF
High-level output voltage, VOH
CLOAD = 10pF
Output capacitance
0.3
2.4
0.4
V
3.0
V
3
pF
5
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SBAS308A − MAY 2004 − REVISED MARCH 2005
TIMING CHARACTERISTICS
Analog
Input
Signal
Sample
N
N + 3
N + 2
N + 1
N + 4
N + 14
N + 15
N + 16
N + 17
tA
Input Clock
t START
tPDI = tSTART + t SETUP
Output Clock
tSETUP
Data Out
(D0−D13)
N − 17
N − 16
N − 15
N − 14
N − 13
N−3
N−2
N−1
N
Data Invalid
tEND
tHOLD
16.5 Clock Cycles
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS(1)(2)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 80MSPS, 50% clock duty cycle, AVDD =
DRVDD = 3.3V, and 3VPP differential clock, unless otherwise noted.(2)
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
Aperture delay, tA
Input CLK falling edge to data sampling point
Aperture jitter (uncertainty)
Uncertainty in sampling instant
valid(3)
1
ns
300
fs
Data setup time, tSETUP
Data
to 50% of CLKOUT rising edge
3.2
4.2
ns
Data hold time, tHOLD
50% of CLKOUT rising edge to data becoming invalid(3)
1.8
3
ns
Input clock to output data valid
start, tSTART(4)
Input clock to Data valid start delay
Input clock to output data valid end,
Input clock to Data valid end delay
tEND(4)
3.8
8.4
5
11
ns
ns
Data rise time, tRISE
Data rise time measured from 20% to 80% of DRVDD
5.6
6.1
ns
Data fall time, tFALL
Data fall time measured from 80% to 20% of DRVDD
4.4
5.1
ns
Output enable (OE) to data output
Time required for outputs to have stable timings with regard to Input
Clock
1000
delay
Clock(5) after OE is activated
Cycles
(1) Timing parameters are ensured by design and characterization, and not tested in production.
(2) See Table 5 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2.0V for LOGIC HIGH and 0.8V for LOGIC LOW.
(4) Refer to the Output Information section for details on using the input clock for data capture.
(5) Data outputs are available within a clock from assertion of OE; however it takes 1000 clock cycles to ensure stable timing with respect to input
clock.
6
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SBAS308A − MAY 2004 − REVISED MARCH 2005
RESET TIMING CHARACTERISTICS
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, and 3VPP differential clock, unless
otherwise noted.
DESCRIPTION
PARAMETER
MIN
TYP
MAX
UNIT
Switching Specification
Power-on delay, t1
Delay from power−on of AVDD and DRVDD to
RESET pulse active
10
ms
Reset pulse width, t2
Pulse width of active RESET signal
2
µs
Register write delay, t3
Delay from RESET disable to SEN active
2
µs
Power Supply
(AVDD, DRVDD)
t1 ≥ 10ms
t2 ≥ 2µs
t3 ≥ 2µs
SEN Active
RESET (Pin 35)
Figure 2. Reset Timing Diagram
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
D Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
D Minimum width of data stream for a valid loading is
D Data is loaded at every 16th SCLK falling edge
while SEN is low.
D In case the word length exceeds a multiple of 16
bits, the excess bits are ignored.
D Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
16 clocks.
A3
SDATA
A2
A1
ADDRESS
A0
D11
D10
D9
D0
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
7
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SBAS308A − MAY 2004 − REVISED MARCH 2005
tSLOADS
tSLOADH
SEN
tWSCLK
tWSCLK
tSCLK
SCLK
t OS
SDATA
t OH
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
SYMBOL
PARAMETER
MIN(1)
tSCLK
SCLK Period
50
TYP(1)
MAX(1)
UNIT
ns
tWSCLK
SCLK Duty Cycle
25
tSLOADS
SEN to SCLK setup time
8
50
75
ns
%
tSLOADH
SCLK to SEN hold time
6
ns
tDS
Data Setup Time
8
ns
tDH
Data Hold Time
6
ns
(1) Typ, min, and max values are characterized, but not production tested.
Table 2. Serial Register Table
A3
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
0
TP<1>
TP<0>
0
0
0
0
0
0
0
0
0
TP<1:0> − Test modes for output data capture
TP<1:0> = 00: Normal mode of operation
TP<1:0> = 01: All outputs forced to 0
TP<1:0> = 10: All outputs forced to 1
TP<1:0> = 11: Each output bit toggles between 0 and
1. There is no ensured relationship between the bits
DESCRIPTION
1
1
1
1
PDN
0
0
0
0
0
0
0
0
0
0
0
PDN = 0 : Normal mode of operation, PDN = 1 :
Device is put in power down (low current) mode
See Note 2
(1) All register contents default to zero on reset.
(2) The patterns given are applicable to the straight offset binary output format. If 2’s complement output format is selected, the test mode outputs
will be the 2’s complement equivalent of these patterns.
Table 3. DATA FORMAT SELECT (DFS TABLE)
DFS-PIN VOLTAGE (VDFS)
DATA FORMAT
CLOCK OUTPUT POLARITY
2
12
Straight Binary
Data valid on rising edge
V DFS t
4
12
5
AV DD t V DFS t
12
AV DD
2’s Complement
Data valid on rising edge
7
12
8
AV DD t V DFS t
12
AV DD
Straight Binary
Data valid on falling edge
2’s Complement
Data valid on falling edge
V DFS u
8
AV DD
10
12
AV DD
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SBAS308A − MAY 2004 − REVISED MARCH 2005
PIN CONFIGURATION
55
54
53
52
51
50
DRVDD
56
DRGND
D4
57
D5
58
D6
59
D7
60
D8
D10
61
D9
D11
62
DRGND
D12
63
DRVDD
D13 (MSB)
64
DRGND
OVR
PAP PACKAGE
(TOP VIEW)
49
DRGND
1
48 DRGND
SCLK
2
47 D3
SDATA
3
46 D2
SEN
4
45 D1
AVDD
5
44 D0 (LSB)
AGND
6
43 CLKOUT
AVDD
7
AGND
8
AVDD
9
42 DRGND
ADS5542
PowerPAD
41 OE
40 DFS
(Connected to Analog Ground)
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND
18
AGND
17
IREF
33 AVDD
REFM
AGND 16
REFP
34 AVDD
AVDD
AVDD 15
AGND
35 RESET
AVDD
AGND 14
AGND
36 AGND
AVDD
AGND 13
AGND
37 AVDD
AVDD
AGND 12
INM
38 AGND
INP
CLKM 11
AGND
39 AVDD
CM
CLKP 10
9
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SBAS308A − MAY 2004 − REVISED MARCH 2005
PIN ASSIGNMENTS
TERMINAL
NAME
NO.
NO.
OF PINS
I/O
AVDD
5, 7, 9, 15, 22, 24, 26,
28, 33, 34, 37, 39
12
I
Analog power supply
AGND
6, 8, 12, 13, 14, 16, 18,
21, 23, 25, 27, 32, 36, 38
14
I
Analog ground
DRVDD
49, 58
2
I
Output driver power supply
DRGND
1, 42, 48, 50, 57, 59
6
I
Output driver ground
INP
19
1
I
Differential analog input (positive)
INM
20
1
I
Differential analog input (negative)
REFP
29
1
O
Reference voltage (positive); 0.1µF capacitor in series with a 1Ω
resistor to GND
REFM
30
1
O
Reference voltage (negative); 0.1µF capacitor in series with a 1Ω
resistor to GND
IREF
31
1
I
Current set; 56kΩ resistor to GND; do not connect capacitors
CM
17
1
O
Common-mode output voltage
RESET
35
1
I
Reset (active high), 200kΩ resistor to AVDD
OE
41
1
I
Output enable (active high)
DFS
40
1
I
Data format and clock out polarity select(1)
CLKP
10
1
I
Data converter differential input clock (positive)
CLKM
11
1
I
Data converter differential input clock (negative)
SEN
4
1
I
Serial interface chip select
SDATA
3
1
I
Serial interface data
SCLK
2
1
I
Serial interface clock
44−47, 51−56, 60−63
14
O
Parallel data output
OVR
64
1
O
Over-range indicator bit
CLKOUT
43
1
O
CMOS clock out in sync with data
D0 (LSB)−D13 (MSB)
DESCRIPTION
NOTE: PowerPAD is connected to analog ground.
(1) Table 3 defines the voltage levels for each mode selectable via the DFS pin.
10
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SBAS308A − MAY 2004 − REVISED MARCH 2005
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3dB with respect to the low
frequency value.
Aperture Delay
The delay in time between the falling edge of the input
sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
width) to the period of the clock signal. Duty cycle is
typically expressed as a percentage. A perfect
differential sine wave clock results in a 50% duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1LSB apart. The DNL is the
deviation of any single step from this ideal value,
measured in units of LSBs.
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function
from a best fit line determined by a least squares curve
fit of that transfer function, measured in units of LSBs.
Gain Error
The gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Gain error does not account for variations in the internal
reference voltages (see the Electrical Specifications
section for limits on the variation of VREFP and VREFM).
Offset Error
The offset error is the difference, given in number of
LSBs, between the ADC’s actual average idle channel
output code and the ideal average idle channel output
code. This quantity is often mapped into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per degree
celcius of the parameter from TMIN to TMAX. It is
calcuated by dividing the maximum deviation of the
parameter across the TMIN to TMAX range by the
difference TMAX−TMIN.
Signal-to-Noise Ratio
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at DC
and the first eight harmonics.
SNR + 10Log 10
PS
PN
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to Full Scale) when the power
of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
DC.
SINAD + 10Log 10
PS
PN ) PD
SINAD is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to Full-Scale) when the power
of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Number of Bits (ENOB)
The ENOB is a measure of a converter’s performance
as compared to the theoretical limit based on
quantization noise.
ENOB + SINAD * 1.76
6.02
11
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SBAS308A − MAY 2004 − REVISED MARCH 2005
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the power of the first eight harmonics (PD).
THD + 10Log 10
PS
PD
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest
other spectral component (either spur or harmonic).
SFDR is typically given in units of dBc (dB to carrier).
12
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at
frequencies f1 and f2) to the power of the worst spectral
component at either frequency 2f1−f2 or 2f2−f1. IMD3 is
either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the
reference, or dBFS (dB to Full-Scale) when the power
of the fundamental is extrapolated to the converter’s
full-scale range.
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SBAS308A − MAY 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
SPECTRAL PERFORMANCE
(FFT for 4MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 16MHz Input Signal)
0
0
Magnitude − dB
−20
−40
−60
−80
−100
−60
−80
−120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
f − Frequency − MHz
f − Frequency − MHz
Figure 5
Figure 6
SPECTRAL PERFORMANCE
(FFT for 55MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 70MHz Input Signal)
0
35
40
0
−40
−60
−80
SFDR = 89.3dBc
SNR = 73.4dBFS
THD = 86.8dBc
SINAD = 73.2dBFS
−20
Magnitude − dB
SFDR = 87.5dBc
SNR = 73.6dBFS
THD = 83.4dBc
SINAD = 73.2dBFS
−20
Magnitude − dB
−40
−100
−120
−100
−40
−60
−80
−100
−120
−120
0
5
10
15
20
25
30
35
0
40
5
10
15
20
25
30
f − Frequency − MHz
f − Frequency − MHz
Figure 7
Figure 8
SPECTRAL PERFORMANCE
(FFT for 100MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 125MHz Input Signal)
0
35
40
35
40
0
−40
−60
−80
−100
SFDR = 83.9dBc
SNR = 72.7dBFS
THD = 81.5dBc
SINAD = 72.2dBFS
−20
Magnitude − dB
SFDR = 87.2dBc
SNR = 72.8dBFS
THD = 83.4dBc
SINAD = 72.5dBFS
−20
Magnitude − dB
SFDR = 92.0dBc
SNR = 73.6dBFS
THD = 88.2dBc
SINAD = 73.5dBFS
−20
Magnitude − dB
SFDR = 92.1dBc
SNR = 74.0dBFS
THD = 88.4dBc
SINAD = 73.9dBFS
−40
−60
−80
−100
−120
−120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
f − Frequency − MHz
f − Frequency − MHz
Figure 9
Figure 10
30
13
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SBAS308A − MAY 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
SPECTRAL PERFORMANCE
(FFT for 150MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 220MHz Input Signal)
0
0
Magnitude − dB
−20
−40
−60
−80
−100
5
10
15
20
25
30
35
−80
40
0
5
10
15
20
25
f − Frequency − MHz
f − Frequency − MHz
Figure 11
Figure 12
SPECTRAL PERFORMANCE
(FFT for 300MHz Input Signal)
TWO−TONE
INTERMODULATION
0
30
35
40
0
−40
−60
−80
f1 = 10.1MHz (−7dBFS)
f2 = 15.1MHz (−7dBFS)
2−Tone SFDR = 92.8dBc
−20
Magnitude − dB
SFDR = 68.4dBc
SNR = 68.5dBFS
THD = 68.2dBc
SINAD = 65.8dBFS
−20
Magnitude − dB
−60
−120
0
−100
−40
−60
−80
−100
−120
−120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
f − Frequency − MHz
f − Frequency − MHz
Figure 13
Figure 14
TWO−TONE
INTERMODULATION
TWO−TONE
INTERMODULATION
0
30
35
40
30
35
40
0
f1 = 45.1MHz (−7dBFS)
f2 = 50.1MHz (−7dBFS)
2−Tone SFDR = 91.6dBc
−20
f1 = 50.1MHz (−7dBFS)
f2 = 55.1MHz (−7dBFS)
2−Tone SFDR = 91.4dBc
−20
−40
Magnitude − dB
Magnitude − dB
−40
−100
−120
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
14
SFDR = 78.4dBc
SNR = 70.7dBFS
THD = 75.8dBc
SINAD = 69.8dBFS
−20
Magnitude − dB
SFDR = 88.6dBc
SNR = 71.9dBFS
THD = 81.2dBc
SINAD = 71.8dBFS
5
10
15
20
25
30
35
40
0
5
10
15
20
25
f − Frequency − MHz
f − Frequency − MHz
Figure 15
Figure 16
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SBAS308A − MAY 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
DIFFERENTIAL
NONLINEARITY
INTEGRAL
NONLINEARITY
1.0
2.0
f IN = 10MHz
AIN = −0.5dBFS
0.8
f IN = 10MHz
AIN = −0.5dBFS
1.5
0.6
1.0
INL − LSB
DNL − LSB
0.4
0.2
0
−0.2
−0.4
0.5
0
−0.5
−1.0
−0.6
−1.5
−0.8
−1.0
−2.0
0
2048
4096
6144
8192 10240 12288 14336 16384
0
8192 10240 12288 14336 16384
Code
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT FREQUENCY
SIGNAL−TO−NOISE RATIO
vs INPUT FREQUENCY
75
90
74
SNR − dBFS
95
SFDR − dBc
6144
Figure 18
76
85
80
75
70
73
72
71
70
69
65
68
60
67
0
50
100
150
200
250
0
300
50
100
150
200
250
Frequency − MHz
Frequency − MHz
Figure 19
Figure 20
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
100
300
98
fIN = 150MHz
SFDR − dBc
SFDR − dBc
4096
Figure 17
100
95
90
SFDR
85
fIN = 70MHz
94
SFDR
90
86
82
72
SNR − dBFS
80
SNR − dBFS
2048
Code
SNR
70
65
60
48
SNR
74
70
66
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
AVDD − Analog Supply Voltage − V
AVDD − Analog Supply Voltage − V
Figure 21
Figure 22
3.5
3.6
15
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SBAS308A − MAY 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
95
fIN = 150MHz
SFDR
SFDR − dBc
SFDR − dBc
95
90
85
90
85
80
75
SNR − dBFS
SNR − dBFS
80
fIN = 70MHz
SFDR
SNR
70
65
SNR
75
70
65
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
DVDD − Digital Supply Voltage − V
DVDD − Digital Supply Voltage − V
Figure 23
Figure 24
POWER DISSIPATION
vs SAMPLE RATE
POWER DISSIPATION
vs SAMPLE RATE
0.75
0.75
fIN = 70MHz
fIN = 150MHz
0.70
Power Dissipation − W
Power Dissipation − W
0.70
0.65
0.60
0.55
0.50
0.45
0.65
0.60
0.55
0.50
0.45
0.40
0.40
10
20
30
40
50
60
70
80
10
AC PERFORMANCE
vs TEMPERATURE
AC PERFORMANCE
vs INPUT AMPLITUDE
SFDR
90
AC Performance − dB
SFDR − dBc
50
Figure 26
85
80
SNR − dBFS
40
Figure 25
95
SNR
75
70
65
60
−15
30
Sample Rate − MSPS
fIN = 70MHz
−40
20
Sample Rate − MSPS
100
+10
+35
Temperature − _C
Figure 27
16
3.6
+60
+85
60
70
100
90
SNR (dBFS)
80
70
60
50
40
SFDR (dBc)
30
20
SNR (dBc)
10
0
−10
fIN = 70MHz
−20
−30
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
Input Amplitude − dBFS
Figure 28
80
0
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SBAS308A − MAY 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
AC PERFORMANCE
vs INPUT AMPLITUDE
100
90
SNR (dBFS)
80
70
60
50
40
SFDR (dBc)
30
20
SNR (dBc)
10
0
−10
−20
fIN = 150MHz
−30
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
90
50
40
SFDR (dBc)
30
20
10
SNR (dBc)
0
−10
−20
fIN = 220MHz
−30 −20
Input Amplitude − dBFS
Input Amplitude − dBFS
Figure 29
Figure 30
OUTPUT
NOISE HISTOGRAM
AC PERFORMANCE
vs CLOCK AMPLITUDE
−10
0
SFDR − dBc
95
35
30
25
20
fIN = 70MHz
90
SFDR
85
80
SNR − dBFS
Occurrence − %
70
60
−30
−100 −90 −80 −70 −60 −50 −40
40
15
10
75
SNR
70
65
8216
8215
8214
8213
8212
8211
8210
8209
8208
8207
8206
8205
8203
0
8204
5
0
0.5
1.0
1.5
2.0
2.5
Code
Differential Clock Amplitude − V
Figure 31
Figure 32
WCDMA
CARRIER
AC PERFORMANCE
vs CLOCK DUTY CYCLE
0
3.0
100
SFDR − dBc
f S = 76.8MSPS
f IN = 170MHz
−20
−40
−60
fIN = 20MHz
SFDR
95
90
85
−80
SNR − dBFS
Amplitude − dB
SNR (dBFS)
80
AC Performance − dB
AC Performance − dB
AC PERFORMANCE
vs INPUT AMPLITUDE
−100
−120
−140
80
75
SNR
70
65
0
5
10
15
20
25
30
35
40
40
45
50
f − Frequency − MHz
Clock Duty Cycle − %
Figure 33
Figure 34
55
60
17
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SBAS308A − MAY 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
SIGNAL−TO−NOISE RATIO (SNR)
74
100
70
74
69
90
72
73
80
71
72
60
70
74
69
50
68
71
73
72
66
70
40
69
68
66
65
67
30
66
74
71
20
72
73
68
70
64
65
67
69
66
63
10
50
100
150
200
Input Frequency (MHz)
Figure 35
18
64
250
300
62
SNR (dBFS)
Sampling Rate (MSPS)
70
70
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SBAS308A − MAY 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
SPURIOUS−FREE DYNAMIC RANGE (SFDR)
87
81
85
85
90
87
79
87
Sampling Rate (MSPS)
80
87
60
71
73
79
87
85
85
87
89
85
69
77
81
83
85
71
77
81
85
40
87
75
81
75
79
87
30
69
71
83
80
73
85
91
91
79
75
83
89 87
50
81
85
91
20
85
85
89
70
90
67
75
87
91
81
81
SFDR (dBc)
100
73
77
87
70
85
89
75
81
85
81
83
79
73
77
71
10
50
100
150
200
Input Frequency (MHz)
250
65
300
Figure 36
19
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SBAS308A − MAY 2004 − REVISED MARCH 2005
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5542 is a low-power, 14-bit, 80MSPS, CMOS,
switched capacitor, pipeline ADC that operates from a
single 3.3V supply. The conversion process is initiated
by a falling edge of the external input clock. Once the
signal is captured by the input S&H, the input sample is
sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction
logic block. Both the rising and the falling clock edges
are used to propagate the sample through the pipeline
every half clock cycle. This process results in a data
latency of 16.5 clock cycles, after which the output data
is available as a 14-bit parallel word, coded in either
straight offset binary or binary two’s complement
format.
INPUT CONFIGURATION
The analog input for the ADS5542 consists of a
differential sample-and-hold architecture implemented
using a switched capacitor technique, shown in
Figure 37.
S3a
L1
R1a
INP
C1a
S1a
CP1
CP3
L2
R3
S2
CA
R1b
S1b
C1b
VINCM
1V
INM
CP2
CP4
S3b
L1, L2 : 6nH − 10nH effective
R1a, R1b : 5Ω− 8Ω
C1a, C1b : 2.2pF − 2.6pF
CP1, CP2 : 2.5pF − 3.5pF
CP3, CP4, : 1.2pF − 1.8pF
CA : 0.8pF − 1.2pF
R3 : 80Ω to 120Ω
Switches: S1a, S1b : On Resistance: 35Ω− 50Ω
S2 : On Resistance: 7.5Ω− 15Ω
S3a, S3b : On Resistance: 40Ω− 60Ω
All switches Off Resistance: 10GΩ
NOTE: All switches are ON during sampling phase, which is approximately one half of a clock period.
Figure 37. Analog Input Stage
20
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SBAS308A − MAY 2004 − REVISED MARCH 2005
This differential input topology produces a high level of
AC performance for high sampling rates. It also results
in a very high usable input bandwidth, especially
important for high intermediate-frequency (IF) or
undersampling applications. The ADS5542 requires
each of the analog inputs (INP, INM) to be externally
biased around the common-mode level of the internal
circuitry (CM, pin 17). For a full-scale differential input,
each of the differential lines of the input signal (pins 19
and 20) swings symmetrically between CM + 0.575V
and CM – 0.575V. This means that each input is driven
with a signal of up to CM ± 0.575V, so that each input
has a maximum differential signal of 1.15VPP for a total
differential input signal swing of 2.3VPP. The maximum
swing is determined by the two reference voltages, the
top reference (REFP, pin 29), and the bottom reference
(REFM, pin 30).
The ADS5542 obtains optimum performance when the
analog inputs are driven differentially. The circuit shown
in Figure 38 shows one possible configuration using an
RF transformer.
R0
50Ω
Z0
50Ω
25Ω
INP
1:1
R
50Ω
25Ω
AC Signal
Source
ADS5542
INM
ADT1−1WT
CM
10Ω
1nF
0.1µF
Figure 38. Transformer Input to Convert
Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of
an RF transformer. Placing a 25Ω resistor in series with
INP and INM is recommended to dampen ringing due
to ADC kickback. Since the input signal must be biased
around the common-mode voltage of the internal
circuitry, the common-mode voltage (VCM) from the
ADS5542 is connected to the center-tap of the
secondary winding. To ensure a steady low-noise VCM
reference, best performance is attained when the CM
output (pin 17) is filtered to ground with a 10Ω series
resistor and parallel 0.1µF and 0.001µF low-inductance
capacitors, as illustrated in Figure 37.
Output VCM (pin 17) is designed to directly drive the
ADC input. When providing a custom CM level, be
aware that the input structure of the ADC sinks a
common-mode current in the order of 400µA (200µA
per input). Equation (1) describes the dependency of
the common-mode current and the sampling
frequency:
400mA f S (in MSPS)
80 MSPS
(1)
Where:
fS > 10MSPS.
This equation helps to design the output capability and
impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the
incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF
transformer, or to use a differential input/output
amplifier without a transformer, to drive the input of the
ADS5542. TI offers a wide selection of single-ended
operational amplifiers (including the THS3201,
THS3202, OPA847, and OPA695) that can be selected
depending on the application. An RF gain block
amplifier, such as TI’s THS9001, can also be used with
an RF transformer for very high input frequency
applications. The THS4503 is a recommended
differential input/output amplifier. Table 4 lists the
recommended amplifiers.
When using single-ended operational amplifiers (such
as the THS3201, THS3202, OPA847, or OPA695) to
provide gain, a three-amplifier circuit is recommended
with one amplifier driving the primary of an RF
transformer and one amplifier in each of the legs of the
secondary driving the two differential inputs of the
ADS5542. These three amplifier circuits minimize
even-order harmonics. For very high frequency inputs,
an RF gain block amplifier can be used to drive a
transformer primary; in this case, the transformer
secondary connections can drive the input of the
ADS5542 directly, as shown in Figure 38, or with the
addition of the filter circuit shown in Figure 39.
Figure 39 illustrates how RIN and CIN can be placed to
isolate the signal source from the switching inputs of the
ADC and to implement a low-pass RC filter to limit the
input noise in the ADC. It is recommended that these
components be included in the ADS5542 circuit layout
when any of the amplifier circuits discussed previously
are used. The components allow fine-tuning of the
circuit performance. Any mismatch between the
differential lines of the ADS5542 input produces a
degradation in performance at high input frequencies,
mainly characterized by an increase in the even-order
harmonics. In this case, special care should be taken to
keep as much electrical symmetry as possible between
both inputs.
21
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SBAS308A − MAY 2004 − REVISED MARCH 2005
Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that
can simplify the driver circuit for applications requiring
DC coupling of the input. Flexible in their configurations
(see Figure 40), such amplifiers can be used for singleended-to-differential conversion, signal amplification.
Table 4. Recommended Amplifiers to Drive the Input of the ADS5542
INPUT SIGNAL FREQUENCY
RECOMMENDED AMPLIFIER
TYPE OF AMPLIFIER
USE WITH TRANSFORMER?
DC to 20MHz
THS4503
Differential In/Out Amp
No
DC to 50MHz
OPA847
Operational Amp
Yes
OPA695
Operational Amp
Yes
10MHz to 120MHz
THS3201
Operational Amp
Yes
THS3202
Operational Amp
Yes
THS9001
RF Gain Block
Yes
Over 100MHz
+5V −5V
RS
100Ω
VIN
0.1µF
OPA695
1000pF
R1
400Ω
RIN
1:1
25Ω
INP
RT
100Ω
RIN
CIN
ADS5542
25Ω
INM
CM
R2
57.5Ω
AV = 8V/V
(18dB)
10Ω
0.1µF
Figure 39. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
22
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SBAS308A − MAY 2004 − REVISED MARCH 2005
RS
RG
RF
+5V
RT
+3.3V
10µF
0.1µF
R IN
INP
VOCM
R IN
ADS5542
14−Bit/80MSPS
INM
1µF
THS4503
10µF
CM
0.1µF
10Ω
RG
−5V
RF
0.1µF
Figure 40. Using the THS4503 with the ADS5542
INPUT VOLTAGE OVER-STRESS
POWER SUPPLY SEQUENCE
The ADS5542 can handle absolute maximum voltages
of 3.6V DC on the input pins INP and INM. For DC inputs
between 3.6V and 3.8V, a 25Ω resistor is required in
series with the input pins. For inputs above 3.8V, the
device can handle only transients, which need to have
less than 5% duty cycle of overstress. The input pins
connect internally to an ESD diode to AVDD, as well as
a switched capacitor circuit. The sampling capacitor of
the switched capacitor circuit connects to the input pins
through a switch in the sample phase. In this phase, an
input larger then 2.65V would cause the switched
capacitor circuit to present an equivalent load of a
forward biased diode to 2.65V, in series with a
60Ω impedance. Also, beyond the voltage on AVDD, the
ESD diode to AVDD starts to become forward biased.
The preferred mode of power supply sequencing is to
power-up AVDD first, followed by DRVDD. Raising both
supplies simultaneously is also a valid power supply
sequence. In the event that DRVDD powers up before
AVDD in the system, AVDD must power up within 10ms
of DRVDD.
In the phase where the sampling switch is off, the diode
loading from the input switched capacitor circuit is
disconnected from the pin, while the ESD loading to
AVDD is still present.
CAUTION:
A violation of any of the previously stated
conditions could damage the device (or reduce
its lifetime) either due to electromigration or
gate oxide integrity. Care should be taken not
to expose the device to input over-voltage for
extended periods of time as it may degrade
device reliability.
POWER DOWN
The device will enter power-down mode in one of two
ways: either by reducing the clock speed to between DC
and 1MHz, or by setting a bit through the serial
programming interface. If reducing the clock speed,
power-down may be initiated for any clock frequency
below 10MHz. The actual frequency at which the device
powers down varies from device to device.
The device can be powered down by programming the
internal register (see Serial Programming Interface
section). The outputs become tri-stated and only the
internal reference is powered up to shorten the
power-up time. The Power-Down mode reduces power
dissipation to a minimum of 180mW.
23
www.ti.com
SBAS308A − MAY 2004 − REVISED MARCH 2005
REFERENCE CIRCUIT
The ADS5542 has built-in internal reference
generation, requiring no external circuitry on the printed
circuit board (PCB). For optimum performance, it is best
to connect both REFP and REFM to ground with a 1µF
decoupling capacitor in series with a 1Ω resistor, as
shown in Figure 41. In addition, an external 56.2kΩ
resistor should be connected from IREF (pin 31) to
AGND to set the proper current for the operation of the
ADC, as shown in Figure 41. No capacitor should be
connected between pin 31 and ground; only the 56.2kΩ
resistor should be used.
CM
CM
5kΩ
5kΩ
CLKP
CLKM
6pF
3pF
3pF
1Ω
29
REFP
30
REFM
31
IREF
1µF
1Ω
1µF
Figure 42. Clock Inputs
When driven with a single-ended CMOS clock input, it
is best to connect CLKM (pin 11) to ground with a
0.01µF capacitor, while CLKP is AC-coupled with a
0.01µF capacitor to the clock source, as shown in
Figure 43.
56 kΩ
Figure 41. REFP, REFM, and IREF Connections
for Optimum Performance
CLOCK INPUT
The ADS5542 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
configurations. The common-mode voltage of the clock
inputs is set internally to CM (pin 17) using internal 5kΩ
resistors that connect CLKP (pin 10) and CLKM (pin 11)
to CM (pin 17), as shown in Figure 42.
24
Square Wave
or Sine Wave
(3VPP)
0.01µF
CLKP
ADS5542
CLKM
0.01µF
Figure 43. AC-Coupled, Single-Ended Clock Input
The ADS5542 clock input can also be driven
differentially, reducing susceptibility to common-mode
noise. In this case, it is best to connect both clock inputs
to the differential input clock signal with 0.01µF
capacitors, as shown in Figure 44.
www.ti.com
SBAS308A − MAY 2004 − REVISED MARCH 2005
95
0.01µF
Differential Square Wave
or Sine Wave
(3VPP)
SFDR − dBc
CLKP
ADS5542
0.01µF
fIN = 70MHz
90
SFDR
85
CLKM
Figure 44. AC-Coupled, Differential Clock Input
For high input frequency sampling, it is recommended
to use a clock source with very low jitter. Additionally,
the internal ADC core uses both edges of the clock for
the conversion process. This means that, ideally, a 50%
duty cycle should be provided. Figure 45 shows the
performance variation of the ADC versus clock duty
cycle.
SNR − dBFS
80
75
SNR
70
65
0
0.5
1.0
1.5
2.0
2.5
3.0
Differential Clock Amplitude − V
Figure 46. AC Performance vs Clock Amplitude
OUTPUT INFORMATION
The ADC provides 14 data outputs (D13 to D0, with D13
being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR,
pin 64) that equals 1 when the output reaches the
full-scale limits.
SFDR − dBc
100
fIN = 20MHz
SFDR
95
90
SNR − dBFS
85
80
75
SNR
70
65
40
45
50
55
60
Clock Duty Cycle − %
Figure 45. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter will further
improve as the amplitude is increased. In that sense,
using a differential clock allows for the use of larger
amplitudes without exceeding the supply rails and
absolute maximum ratings of the ADC clock input.
Figure 46 shows the performance variation of the
device versus input clock amplitude. For detailed
clocking schemes based on transformer or PECL-level
clocks, refer to the ADS55xxEVM User’s Guide
(SLWU010), available for download from www.ti.com.
Two different output formats (straight offset binary or
two’s complement) and two different output clock
polarities (latching output data on rising or falling edge
of the output clock) can be selected by setting DFS
(pin 40) to one of four different voltages. Table 3 details
the four modes. In addition, output enable control (OE,
pin 41, active high) is provided to put the outputs into a
high-impedance state.
In the event of an input voltage overdrive, the digital
outputs go to the appropriate full-scale level. For a
positive overdrive, the output code is 0xFFF in straight
offset binary output format, and 0x7FF in 2’s
complement output format. For a negative input
overdrive, the output code is 0x000 in straight offset
binary output format, and 0x800 in 2’s complement
output format. These outputs to an overdrive signal are
ensured through design and characterization
The output circuitry of the ADS5542, by design,
minimizes the noise produced by the data switching
transients, and, in particular, its coupling to the ADC
analog circuitry. Output D2 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output slew
25
www.ti.com
SBAS308A − MAY 2004 − REVISED MARCH 2005
rate described in the timing diagram of Figure 1. Care
should be taken to ensure that all output lines (including
CLKOUT) have nearly the same load as D2 (pin 51).
This circuit also reduces the sensitivity of the output
timing versus supply voltage or temperature. Placing
external resistors in series with the outputs is not
recommended.
The ADS5542 internal registers default to all zeros on
reset. The device is reset by applying a high pulse on
the RESET pin (pin 35) for a minimum of 2µs at least
10ms after both the AVDD and DRVDD power supplies
have come up (as illustrated in Figure 2) In reset, the
ADC outputs are forced low. Note that the RESET pin
has a 200kΩ pull-up resistor to AVDD.
The timing characteristics of the digital outputs change
for sampling rates below the 80MSPS maximum
sampling frequency. Table 5 shows the timing
parameters for sampling rates of 20MSPS, 40MSPS,
and 65MSPS.
If the ADS5542 is to be used solely in the default mode
set at reset, the serial interface pins can be tied to fixed
voltages. In this case, tie SCLK high, SEN low, and
SDATA to either a high or low voltage.
To use the input clock as the data capture clock, it is
necessary to delay the input clock by a delay, td, that
results in the desired setup or hold time. Use either of
the following equations to calculate the value of td.
PowerPAD Package
The PowerPAD package is a thermally-enhanced
standard size IC package designed to eliminate the use
of bulky heatsinks and slugs traditionally used in
thermal packages. This package can be easily mounted
using standard PCB assembly techniques, and can be
removed and replaced using standard repair
procedures.
Desired setup time = td − tSTART
Desired hold time = tEND − td
SERIAL PROGRAMMING INTERFACE
The PowerPAD package is designed so that the
leadframe die pad (or thermal pad) is exposed on the
bottom of the IC. This provides an extremely low
thermal resistance path between the die and the
exterior of the package. The thermal pad on the bottom
of the IC can then be soldered directly to the PCB, using
the PCB as a heatsink.
The ADS5542 has internal registers that enable the
programming of the device into modes as described in
previous sections. Programming is done through a
3-wire serial interface. The timing diagram and register
settings in the Serial Programming Interface section
describe the use of this interface.
Table 2 shows the different modes and the bit values to
be written to the register to enable them.
Table 5. Timing Characteristics at Additional Sampling Frequencies
fS
(MSPS)
65
26
tSETUP (ns)
MIN
TYP
4.3
MAX
tHOLD (ns)
MIN
TYP
5.7
2
3
tSTART (ns)
MAX
MIN
tEND (ns)
TYP
MAX
MIN
TYP
2.8
4.5
8.3
tRISE (ns)
MAX
MIN
tFALL (ns)
TYP
MAX
MIN
TYP
MAX
11.8
6.6
7.2
5.5
6.4
40
8.5
11.0
2.6
3.5
−1
1.5
8.9
14.5
7.5
8
7.3
7.8
20
17.0
25.7
2.5
4.7
−9.8
2
9.5
21.6
7.5
8
7.6
8
www.ti.com
SBAS308A − MAY 2004 − REVISED MARCH 2005
Assembly Process
1. Prepare the PCB top-side etch pattern including
etch for the leads as well as the thermal pad as
illustrated in the Mechanical Data section.
2. Place a 5-by-5 array of thermal vias in the thermal
pad area. These holes should be 13 mils in
diameter. The small size prevents wicking of the
solder through the holes.
3. It is recommended to place a small number of 25 mil
diameter holes under the package, but outside the
thermal pad area to provide an additional heat path.
4. Connect all holes (both those inside and outside the
thermal pad area) to an internal copper plane (such
as a ground plane).
5. Do not use the typical web or spoke via connection
pattern when connecting the thermal vias to the
ground plane. The spoke pattern increases the
thermal resistance to the ground plane.
6. The top−side solder mask should leave exposed
the terminals of the package and the thermal pad
area.
7. Cover the entire bottom side of the PowerPAD vias
to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area
and all of the package terminals.
For more detailed information regarding the PowerPAD
package and its thermal properties, please refer to
either Application Brief SLMA004B (PowerPAD Made
Easy), or Technical Brief SLMA002 (PowerPAD
Thermally Enhanced Package), both available for
download at www.ti.com.
27
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS5542IPAP
ACTIVE
HTQFP
PAP
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5542IPAPG4
ACTIVE
HTQFP
PAP
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5542IPAPR
ACTIVE
HTQFP
PAP
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5542IPAPRG4
ACTIVE
HTQFP
PAP
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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