ASAHI KASEI [AK4644] AK4644 Stereo CODEC with MIC/HP/RCV-AMP GENERAL DESCRIPTION The AK4644 is a stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Receiver-Amplifier. The AK4644 features analog mixing circuits and PLL that allows easy interfacing in mobile phone and portable A/V player designs. The AK4644 is available in a 32pin QFN, utilizing less board space than competitive offerings. FEATURES 1. Recording Function • 3 Stereo Input Selector • Stereo Mic Input (Full-differential or Single-ended) • Stereo Line Input • MIC Amplifier (+32dB/+26dB/+20dB or 0dB) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • ADC Performance: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB) S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB) • Wind-noise Reduction Filter • Stereo Separation Emphasis • Programmable EQ 2. Playback Function • Digital De-emphasis Filter (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz) • Bass Boost • Soft Mute • Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • Stereo Separation Emphasis • Stereo Line Output - Performance: S/(N+D): 88dB, S/N: 92dB • Mono Receiver-Amp - BTL Output - Output Power: 30mW@32Ω (AVDD=3.3V) • Stereo Headphone-Amp - S/(N+D): [email protected], S/N: 90dB - Output Power: 70mW@16Ω (HVDD=5V), 62mW@16Ω (HVDD=3.3V) - Pop Noise Free at Power ON/OFF • Analog Mixing: 3 Stereo Input 3. Power Management 4. Master Clock: (1) PLL Mode • Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 1fs (LRCK pin) 32fs or 64fs (BICK pin) (2) External Clock Mode • Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs MS0477-E-01 2006/10 -1- ASAHI KASEI [AK4644] 6. Sampling Rate: • PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • EXT Master/Slave Mode: 7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) 7. µP I/F: 3-wire Serial, I2C Bus (Ver 1.0, 400kHz High Speed Mode) 8. Master/Slave mode 9. Audio Interface Format: MSB First, 2’s complement • ADC : 16bit MSB justified, I2S, DSP Mode • DAC : 16bit MSB justified, 16bit LSB justified, 16-24bit I2S, DSP Mode 10. Ta = −30 ∼ 85°C 11. Power Supply: • AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V) • HVDD: 2.6 ∼ 5.25V (typ. 3.3V/5.0V) 12. Package: 32pin QFN (5mm x 5mm, 0.5mm pitch) 13. Pin/Register Compatible with AK4642EN Block Diagram AVDD AVSS VCOM DVDD DVSS PMMP MPWR CSN CCLK CDTI PMADL or PMADR RIN1 A/D MIC-Amp LIN2 External MIC Control Register PMADL or PMMICL LIN1 Internal MIC I2C MIC Power Supply Wind-Noise Reduction HPF Stereo Separation PDN ALC PMADR or PMMICR BICK RIN2 LRCK SDTO PMAINR2 LIN3/MIN Line In RIN3/VCOC Audio I/F PMAINL2 PMAINR3 SDTI PMAINL3 PMLO LOUT/RCP Stereo Line Out or Mono Receiver ROUT/RCN PMHPL PMDAC D/A HPL Headphone Stereo DATT Bass ALC Separation SMUTE Boost HPF PMHPR HPR MCKO PMPLL MUTET PLL MCKI VCOC HVDD HVSS Figure 1. Block Diagram MS0477-E-01 2006/10 -2- ASAHI KASEI [AK4644] Ordering Guide −30 ∼ +85°C 32pin QFN (0.5mm pitch) Evaluation board for AK4644 AK4644EN AKD4644 HPL HPR HVSS HVDD TEST2 TEST1 MCKO MCKI 23 22 21 20 19 18 17 AK4644EN 13 LRCK RIN2 / IN2− 29 Top View 12 SDTO LIN2 / IN2+ 30 11 SDTI LIN1 / IN1− 31 10 CDTI / SDA RIN1 / IN1+ 32 9 CCLK / SCL CSN / CAD0 MPWR 8 28 7 MIN / LIN3 PDN BICK 6 14 I2C 27 5 LOUT / RCP VCOC / RIN3 DVDD 4 15 AVDD 26 3 ROUT / RCN AVSS DVSS 2 16 VCOM 25 1 MUTET 24 Pin Layout Compatibility with AK4642EN 1. Function Function HP-Amp Max Output Power SPK-Amp Receiver-Amp Analog Mixing for Playback Input Selector for Recording Mono Recording Mode ALC Recovery Waiting Period ALC Fast Recovery Speed DSP Format EXT Master Mode DAC Group Delay AK4642EN [email protected] Yes No 1 Mono 2 Stereo No 128/fs ∼ 1024/fs 4 times No No 22/fs MS0477-E-01 AK4644 70mW@5V No Yes 3 Stereo 3 Stereo Yes 128/fs ∼ 16384/fs 4, 8 or 16 times Yes Yes 25/fs 2006/10 -3- ASAHI KASEI [AK4644] 2. Pin Pin# 5 19 20 26 27 28 AK4642EN VCOC SPN SPP ROUT LOUT MIN AK4644 VCOC/RIN3 TEST1 TEST2 ROUT/RCN LOUT/RCP MIN/LIN3 3. Register Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Power Management 4 Mode Control 5 Lineout Mixing Select HP Mixing Select Reserved D7 0 0 SPPSN LOVL PLL3 PS1 DVTM 0 REF7 IVL7 DVL7 RGAIN1 IVR7 DVR7 0 0 INR1 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 0 0 0 0 0 D6 PMVCM D5 PMMIN PMHPL DACS D4 PMSPK PMHPR DACL SPKG1 PLL0 MSBS ZTM0 ZELMN REF4 IVL4 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 D3 PMLO M/S 0 SPKG0 BCKO BCKP WTM1 LMAT1 REF3 IVL3 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 HPMTN MINS MGAIN1 LOPS PLL2 PLL1 PS0 FS3 WTM2 ZTM1 0 ALC REF6 REF5 IVL6 IVL5 DVL6 DVL5 LMTH1 0 IVR6 IVR5 DVR6 DVR5 LOOP SMUTE 0 0 INL1 HPG GN0 0 F3A6 F3A5 0 F3A13 F3B6 F3B5 0 F3B13 EQA6 EQA5 EQA14 EQA13 EQB6 EQB5 0 EQB13 EQC6 EQC5 EQC14 EQC13 F1A6 F1A5 0 F1A13 F1B6 F1B5 0 F1B13 PMAINR3 PMAINL3 PMAINR2 0 0 MICR3 MICL3 0 0 0 0 RINR3 0 0 0 RINH3 0 0 0 0 These bits are added in the AK4644. These bits are removed from the AK4644. MS0477-E-01 D2 PMDAC 0 PMMP MINL 0 FS2 WTM0 LMAT0 REF2 IVL2 DVL2 0 IVR2 DVR2 BST0 HPM INR0 FIL3 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 D1 0 MCKO 0 0 DIF1 FS1 RFST1 RGAIN0 REF1 IVL1 DVL1 VBAT IVR1 DVR1 DEM1 MINH INL0 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 D0 PMADL PMPLL 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL0 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 PMAINL2 PMMICR PMMICL MIX LINL3 LINH3 0 AIN3 RINR2 RINH2 0 RCV LINL2 LINH2 0 MGAIN0 2006/10 -4- ASAHI KASEI [AK4644] PIN/FUNCTION No. 1 Pin Name MPWR I/O O Function MIC Power Supply Pin Common Voltage Output Pin, 0.45 x AVDD 2 VCOM O Bias voltage of ADC inputs and DAC outputs. 3 AVSS Analog Ground Pin 4 AVDD Analog Power Supply Pin Output Pin for Loop Filter of PLL Circuit (AIN3 bit = “0”: PLL is available) VCOC O 5 This pin should be connected to AVSS with one resistor and capacitor in series. RIN3 I Rch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available) Control Mode Select Pin 6 I2C I “H”: I2C Bus, “L”: 3-wire Serial Power-Down Mode Pin 7 PDN I “H”: Power-up, “L”: Power-down, reset and initializes the control register. CSN I Chip Select Pin (I2C pin = “L”: 3-wire Serial Mode) 8 CAD0 I Chip Address 1 Select Pin (I2C pin = “H”: I2C Bus Mode) CCLK I Control Data Clock Pin (I2C pin = “L”: 3-wire Serial Mode) 9 SCL I Control Data Clock Pin (I2C pin = “H”: I2C Bus Mode) CDTI I Control Data Input Pin (I2C pin = “L”: 3-wire Serial Mode) 10 SDA I/O Control Data Input Pin (I2C pin = “H”: I2C Bus Mode) 11 SDTI I Audio Serial Data Input Pin 12 SDTO O Audio Serial Data Output Pin 13 LRCK I/O Input / Output Channel Clock Pin 14 BICK I/O Audio Serial Data Clock Pin 15 DVDD Digital Power Supply Pin 16 DVSS Digital Ground Pin 17 MCKI I External Master Clock Input Pin 18 MCKO O Master Clock Output Pin Test 1 Pin 19 TEST1 This pin should be left floating. Test 2 Pin 20 TEST2 This pin should be left floating. 21 HVDD Headphone-Amp Power Supply Pin 22 HVSS Headphone-Amp Ground Pin 23 HPR O Rch Headphone-Amp Output Pin 24 HPL O Lch Headphone-Amp Output Pin Mute Time Constant Control Pin 25 MUTET O Connected to HVSS pin with a capacitor for mute time constant. ROUT O Rch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output) 26 RCN O Receiver-Amp Negative Output Pin (RCV bit = “1”: BTL output) LOUT O Lch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output) 27 RCP O Receiver-Amp Positive Output Pin (RCV bit = “1”: BTL output) MIN I Mono Signal Input Pin (AIN3 bit = “0”: PLL is available) 28 LIN3 I Lch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available) RIN2 I Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) 29 I Microphone Negative Input 2 Pin (MDIF2 bit = “1”: Full-differential Input) IN2− LIN2 I Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) 30 IN2+ I Microphone Positive Input 2 Pin (MDIF2 bit = “1”: Full-differential Input) LIN1 I Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input) 31 I Microphone Negative Input 1 Pin (MDIF1 bit = “1”: Full-differential Input) IN1− RIN1 I Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input) 32 IN1+ I Microphone Positive Input 1 Pin (MDIF1 bit = “1”: Full-differential Input) Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3) should not be left floating. Note 2. AVDD or AVSS voltage should be input to I2C pin. MS0477-E-01 2006/10 -5- ASAHI KASEI [AK4644] Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name MPWR, VCOC/RIN3, HPR, HPL, MUTET, ROUT/RCN, LOUT/RCP, MIN/LIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ MCKO MCKI Setting These pins should be open. This pin should be open. This pin should be connected to DVSS. ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, HVSS=0V; Note 3) Parameter Symbol min Power Supplies: Analog AVDD −0.3 Digital DVDD −0.3 Headphone-Amp HVDD −0.3 |AVSS – DVSS| (Note 4) ∆GND1 |AVSS – HVSS| (Note 4) ∆GND2 Input Current, Any Pin Except Supplies IIN Analog Input Voltage (Note 5) VINA −0.3 Digital Input Voltage (Note 6) VIND −0.3 Ambient Temperature (powered applied) Ta −30 Storage Temperature Tstg −65 max 6.0 6.0 6.0 0.3 0.3 ±10 AVDD+0.3 DVDD+0.3 85 150 Units V V V V V mA V V °C °C Note 3. All voltages with respect to ground. Note 4. AVSS, DVSS and HVSS must be connected to the same analog ground plane. Note 5. I2C, MIN/LIN3, RIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins Pull-up resistors at SDA and SCL pins should be connected to (DVDD+0.3)V or less voltage. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, HVSS=0V; Note 3) Parameter Symbol min typ Power Supplies Analog AVDD 2.6 3.3 (Note 7) Digital DVDD 2.6 3.3 HP-Amp HVDD 2.6 3.3 / 5.0 Difference 0 AVDD−DVDD −0.3 max 3.6 3.6 5.25 +0.3 Units V V V V Note 3. All voltages with respect to ground. Note 7. The power-up sequence between AVDD, DVDD and HVDD is not critical. When only AVDD or HVDD is powered OFF, the power supply current of DVDD at power-down mode may be increased. DVDD should not be powered OFF while AVDD or HVDD is powered ON. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0477-E-01 2006/10 -6- ASAHI KASEI [AK4644] ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, HVDD=3.3V; AVSS=DVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) min typ max Parameter MIC Amplifier: LIN1/RIN1/LIN2/RIN2 pins & LIN3/RIN3 pins (AIN3 bit = “1”); MDIF1=MDIF2 bits = “0” (Single-ended inputs) Input MGAIN1-0 bits = “00” 40 60 80 Resistance MGAIN1-0 bits = “01”, “10”or “11” 20 30 40 MGAIN1-0 bits = “00” 0 MGAIN1-0 bits = “01” +20 Gain MGAIN1-0 bits = “10” +26 MGAIN1-0 bits = “11” +32 MIC Amplifier: IN1+/IN1−/IN2+/IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input) Maximum Input Voltage (Note 8) MGAIN1-0 bits = “01” 0.228 MGAIN1-0 bits = “10” 0.114 MGAIN1-0 bits = “11” 0.057 MIC Power Supply: MPWR pin Output Voltage (Note 9) 2.22 2.47 2.72 Load Resistance 0.5 Load Capacitance 30 ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins & LIN3/RIN3 pins (AIN3 bit = “1”) → ADC → IVOL, IVOL=0dB, ALC=OFF Resolution 16 (Note 11) 0.168 0.198 0.228 Input Voltage (Note 10) (Note 12) 1.68 1.98 2.28 (Note 11, LIN1/RIN1/LIN2/RIN2) 71 83 S/(N+D) (Note 11, LIN3/RIN3) 83 (−1dBFS) (Note 12, LIN1/RIN1/LIN2/RIN2) 88 (Note 12, LIN3/RIN3) 72 (Note 11) 76 86 D-Range (−60dBFS, A-weighted) (Note 12) 95 (Note 11) 76 86 S/N (A-weighted) (Note 12) 95 (Note 11) 75 90 Interchannel Isolation (Note 12) 100 (Note 11) 0.1 0.8 Interchannel Gain Mismatch (Note 12) 0.1 0.8 Units kΩ kΩ dB dB dB dB Vpp Vpp Vpp V kΩ pF Bits Vpp Vpp dBFS dBFS dBFS dBFS dB dB dB dB dB dB dB dB Note 8. The voltage difference between IN1/2+ and IN1/2− pins. AC coupling capacitor should be inserted in series at each input pin. Full-differential mic input is not available at MGAIN1-0 bits = “00”. Maximum input voltage of IN1+, IN1−, IN2+ and IN2− pins is proportional to AVDD voltage, respectively. Vin = 0.069 x AVDD (max)@MGAIN1-0 bits = “01”, 0.035 x AVDD (max)@MGAIN1-0 bits = “10”, 0.017 x AVDD (max)@MGAIN1-0 bits = “11”. When the signal larger than above value is input to IN1+, IN1−, IN2+ or IN2− pin, ADC does not operate normally. Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ) Note 10. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)@MGAIN1-0 bits = “01” (+20dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB) Note 11. MGAIN1-0 bits = “01” (+20dB) Note 12. MGAIN1-0 bits = “00” (0dB) MS0477-E-01 2006/10 -7- ASAHI KASEI [AK4644] min typ max Units Parameter DAC Characteristics: Resolution 16 Bits Stereo Line Output Characteristics: DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, RCV bit = “0”, RL=10kΩ Output Voltage (Note 13) LOVL bit = “0” 1.78 1.98 2.18 Vpp LOVL bit = “1” 2.25 2.50 2.75 Vpp 78 88 dBFS S/(N+D) (−3dBFS) S/N (A-weighted) 82 92 dB Interchannel Isolation PMAINL2/R2/L3/R3 bits = “1” 80 100 dB PMAINL2/R2/L3/R3 bits = “0” 100 dB Interchannel Gain Mismatch 0.1 0.5 dB Load Resistance 10 kΩ Load Capacitance 30 pF Mono Receiver Output Characteristics: DAC → RCP/RCN pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, RCV bit = “1”, RL=32Ω, BTL Output Voltage (Note 14) 1.57 1.96 2.35 Vpp LOVL bit = “0”, −6dBFS, RL=32Ω (Po=15mW) 2.77 Vpp LOVL bit = “0”, −3dBFS, RL=32Ω (Po=30mW) 1.57 1.96 2.35 Vpp LOVL bit = “1”, −8dBFS, RL=32Ω (Po=15mW) 2.77 Vpp LOVL bit = “1”, −5dBFS, RL=32Ω (Po=30mW) S/(N+D) 40 60 dB LOVL bit = “0”, −6dBFS, RL=32Ω (Po=15mW) 60 dB LOVL bit = “0”, −3dBFS, RL=32Ω (Po=30mW) S/N (A-weighted) 85 95 dBFS Load Resistance 32 Ω Load Capacitance 30 pF Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)@LOVL bit = “0”. Note 14. Output voltage is proportional to AVDD voltage. Vout = (RCP) − (RCN) = 0.59 x AVDD (typ)@LOVL bit = “0”, −6dBFS. MS0477-E-01 2006/10 -8- ASAHI KASEI [AK4644] min typ max Parameter Headphone-Amp Characteristics: DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB Output Voltage (Note 15) 1.58 1.98 2.38 HPG bit = “0”, 0dBFS, HVDD=3.3V, RL=22.8Ω 2.40 3.00 3.60 HPG bit = “1”, 0dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 1.0 HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW) 1.06 S/(N+D) 60 70 HPG bit = “0”, −3dBFS, HVDD=3.3V, RL=22.8Ω 80 HPG bit = “1”, −3dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 20 HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW) 70 (Note 16) 80 90 S/N (A-weighted) (Note 17) 90 Interchannel Isolation (Note 16), PMAINL2/R2/L3/R3 bits = “1” 65 75 (Note 16), PMAINL2/R2/L3/R3 bits = “0” 75 (Note 17) 80 (Note 16) 0.1 0.8 Interchannel Gain Mismatch (Note 17) 0.1 0.8 Load Resistance 16 C1 in Figure 2 30 Load Capacitance C2 in Figure 2 300 Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ) Maximum Input Voltage (Note 18) 1.98 Gain (Note 19) MIN Æ LOUT/ROUT LOVL bit = “0” 0 +4.5 −4.5 LOVL bit = “1” +2 MIN Æ HPL/HPR HPG bit = “0” −24.5 −20 −15.5 HPG bit = “1” −16.4 Units Vpp Vpp Vrms Vrms dBFS dBFS dBFS dBFS dB dB dB dB dB dB dB Ω pF pF Vpp dB dB dB dB Note 15. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”. Note 16. HPG bit = “0”, HVDD=3.3V, RL=22.8Ω. Note 17. HPG bit = “1”, HVDD=5V, RL=100Ω. Note 18. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin / 20kΩ (typ). Note 19. The gain is in inverse proportion to external input resistance. HP-Amp HPL/HPR pin Measurement Point 47µF 6.8Ω C1 0.22µF C2 16Ω 10Ω Figure 2. Headphone-Amp output circuit MS0477-E-01 2006/10 -9- ASAHI KASEI [AK4644] min Parameter Stereo Input: LIN2/RIN2 pins; LIN3/RIN3 pins (AIN3 bit = “1”) Maximum Input Voltage (Note 20) Gain LIN/RIN Æ LOUT/ROUT LOVL bit = “0” −4.5 LOVL bit = “1” LIN/RIN Æ HPL/HPR HPG bit = “0” −4.5 HPG bit = “1” Power Supplies: Power-Up (PDN pin = “H”) All Circuit Power-up: AVDD+DVDD (Note 21) HVDD: HP-Amp Normal Operation No Output (Note 22) Power-Down (PDN pin = “L”) (Note 23) AVDD+DVDD+HVDD - typ max Units 1.98 - Vpp 0 +2 0 +3.6 +4.5 +4.5 - dB dB dB dB 16 24 mA 5 8 mA 10 100 µA Note 20. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ). Note 21. PLL Master Mode (MCKI=12.288MHz) and PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = MCKO = PMMIN = PMMP = M/S bits = “1”. MPWR pin outputs 0mA. AVDD=12mA(typ), DVDD=4mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=11mA(typ), DVDD=3mA(typ). Note 22. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN bits = “1”. Note 23. All digital input pins are fixed to DVDD or DVSS. Power Consumption for each operation mode Condtions: Ta=25°C; AVDD=DVDD=HVDD=3.3V; AVSS=DVSS=HVSS=0V; fs=44.1kHz, External Slave Mode, BICK=64fs; 1kHz, 0dBFS input; Headphone = No output Power Management Bit 01H 10H PMAINR3 0 8.1 2.8 5 52.5 PMAINR2 0 24.4 34.7 22.8 10.9 24.4 16.8 PMAINL2 0 0.2 5 5 0.2 0.2 0.2 PMMICR 0 1.8 1.8 0 0 1.6 1.5 PMMICL 0 5.4 3.7 1.9 3.1 5.6 3.4 PMADR 0 0 0 0 0 0 0 PMHPR 0 0 0 0 0 0 0 PMHPL Total Power [mW] PMADL HVDD [mA] PMDAC DVDD [mA] PMLO AVDD [mA] Mode PMMIN PMAINL3 20H PMVCM 00H All Power-down DAC Æ Lineout DAC Æ HP LIN2/RIN2 Æ HP MIN Æ RCV LIN2/RIN2 Æ ADC LIN1 (Mono) Æ ADC LIN2/RIN2 Æ ADC & DAC Æ HP 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 Table 1. Power Consumption for each operation mode (typ) MS0477-E-01 2006/10 - 10 - ASAHI KASEI [AK4644] FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 24) PB 0 17.3 kHz ±0.16dB 19.4 kHz −0.66dB 19.9 kHz −1.1dB 22.1 kHz −6.9dB Stopband SB 26.1 kHz Passband Ripple PR dB ±0.1 Stopband Attenuation SA 73 dB Group Delay (Note 25) GD 19 1/fs Group Delay Distortion 0 ∆GD µs ADC Digital Filter (HPF): (Note 26) Frequency Response (Note 24) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB DAC Digital Filter (LPF): Passband (Note 24) PB 0 19.6 kHz ±0.1dB 20.0 kHz −0.7dB 22.05 kHz −6.0dB Stopband SB 25.2 kHz Passband Ripple PR dB ±0.01 Stopband Attenuation SA 59 dB Group Delay (Note 25) GD 25 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0 ∼ 20.0kHz ±1.0 DAC Digital Filter (HPF): (Note 26) Frequency Response (Note 24) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB BOOST Filter: (Note 27) Frequency Response MIN FR 20Hz dB 5.76 100Hz dB 2.92 1kHz dB 0.02 MID FR 20Hz dB 10.80 100Hz dB 6.84 1kHz dB 0.13 MAX 20Hz FR dB 16.06 100Hz dB 10.54 1kHz dB 0.37 Note 24. The passband and stopband frequencies scale with fs (system sampling rate). For example, DAC is PB=0.454*fs (@−0.7dB). Each response refers to that of 1kHz. Note 25. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. Group delay of DAC part is 25/fs(typ) at PMADL=PMADR bits = “0”. Note 26. When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is disabled. Note 27. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips to the full-scale. MS0477-E-01 2006/10 - 11 - ASAHI KASEI [AK4644] DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage VOH (Iout=−200µA) DVDD−0.2 Low-Level Output Voltage VOL (Except SDA pin: Iout=200µA) (SDA pin: Iout=3mA) VOL Input Leakage Current Iin - typ - max 30%DVDD - Units V V V - 0.2 0.4 ±10 V V µA SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; CL=20pF; unless otherwise specified) Parameter Symbol min typ max PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 27 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 12.288 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 256fs at fs=32kHz, 29.4kHz dMCK 33 LRCK Output Timing Frequency fs 7.35 48 DSP Mode: Pulse Width High tLRCKH tBCK Except DSP Mode: Duty Cycle Duty 50 BICK Output Timing Period BCKO bit = “0” tBCK 1/(32fs) BCKO bit = “1” tBCK 1/(64fs) Duty Cycle dBCK 50 PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 27 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 12.288 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 256fs at fs=32kHz, 29.4kHz dMCK 33 LRCK Input Timing Frequency fs 7.35 48 DSP Mode: Pulse Width High tLRCKH tBCK−60 1/fs − tBCK Except DSP Mode: Duty Cycle Duty 45 55 BICK Input Timing Period tBCK 1/(64fs) 1/(32fs) Pulse Width Low tBCKL 0.4 x tBCK Pulse Width High tBCKH 0.4 x tBCK - MS0477-E-01 Units MHz ns ns MHz % % kHz ns % ns ns % MHz ns ns MHz % % kHz ns % ns ns ns 2006/10 - 12 - ASAHI KASEI [AK4644] Parameter Symbol PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period PLL3-0 bits = “0010” tBCK PLL3-0 bits = “0011” tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Slave Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Input Timing Frequency 256fs fs 512fs fs 1024fs fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Master Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Output Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Output Timing Period BCKO bit = “0” tBCK BCKO bit = “1” tBCK Duty Cycle dBCK MS0477-E-01 min typ max Units 7.35 tBCK−60 45 - 48 1/fs − tBCK 55 kHz ns % 1/(64fs) 130 130 - 1/(32fs) - ns ns ns 7.35 tBCK−60 45 - 48 1/fs − tBCK 55 kHz ns % 0.4 x tBCK 0.4 x tBCK 1/(32fs) 1/(64fs) - - ns ns ns ns 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK - 12.288 13.312 13.312 - MHz MHz MHz ns ns 7.35 7.35 7.35 tBCK−60 45 - 48 26 13 1/fs − tBCK 55 kHz kHz kHz ns % 312.5 130 130 - - ns ns ns 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK - 12.288 13.312 13.312 - MHz MHz MHz ns ns 7.35 - tBCK 50 48 - kHz ns % - 1/(32fs) 1/(64fs) 50 - ns ns % 2006/10 - 13 - ASAHI KASEI [AK4644] Parameter Symbol min Audio Interface Timing (DSP Mode) Master Mode tDBF LRCK “↑” to BICK “↑” (Note 28) 0.5 x tBCK − 40 tDBF LRCK “↑” to BICK “↓” (Note 29) 0.5 x tBCK − 40 tBSD BICK “↑” to SDTO (BCKP bit = “0”) −70 tBSD BICK “↓” to SDTO (BCKP bit = “1”) −70 SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Slave Mode tLRB 0.4 x tBCK LRCK “↑” to BICK “↑” (Note 28) tLRB 0.4 x tBCK LRCK “↑” to BICK “↓” (Note 29) tBLR 0.4 x tBCK BICK “↑” to LRCK “↑” (Note 28) tBLR 0.4 x tBCK BICK “↓” to LRCK “↑” (Note 29) tBSD BICK “↑” to SDTO (BCKP bit = “0”) tBSD BICK “↓” to SDTO (BCKP bit = “1”) SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Audio Interface Timing (Right/Left justified & I2S) Master Mode tMBLR BICK “↓” to LRCK Edge (Note 28) −40 LRCK Edge to SDTO (MSB) tLRD −70 (Except I2S mode) tBSD BICK “↓” to SDTO −70 SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Slave Mode tLRB 50 LRCK Edge to BICK “↑” (Note 29) tBLR 50 BICK “↑” to LRCK Edge (Note 30) tLRD LRCK Edge to SDTO (MSB) (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Note 28. MSBS, BCKP bits = “00” or “11”. Note 29. MSBS, BCKP bits = “01” or “10”. Note 30. BICK rising edge must not occur at the same time as LRCK edge. MS0477-E-01 typ max Units 0.5 x tBCK 0.5 x tBCK - 0.5 x tBCK + 40 0.5 x tBCK + 40 70 70 - ns ns ns ns ns ns - 80 80 - ns ns ns ns ns ns ns ns - 40 70 ns ns - 70 - ns ns ns - 80 ns ns ns - 80 - ns ns ns 2006/10 - 14 - ASAHI KASEI [AK4644] Parameter Symbol min Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN “H” Time tCSW 150 tCSS 50 CSN “↓” to CCLK “↑” tCSH 50 CCLK “↑” to CSN “↑” Control Interface Timing (I2C Bus mode) SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 32) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Capacitive Load on Bus Cb Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Power-down & Reset Timing PDN Pulse Width (Note 33) tPD 150 tPDV PMADL or PMADR “↑” to SDTO valid (Note 34) 2 Note 31. I C is a registered trademark of Philips Semiconductors. Note 32. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 33. The AK4644 can be reset by the PDN pin = “L”. Note 34. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. MS0477-E-01 typ max Units - - ns ns ns ns ns ns ns ns - 400 0.3 0.3 400 50 kHz µs µs µs µs µs µs µs µs µs µs pF ns 1059 - ns 1/fs 2006/10 - 15 - ASAHI KASEI [AK4644] Timing Diagram 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs 50%DVDD LRCK tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 1/fMCK 50%DVDD MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 3. Clock Timing (PLL/EXT Master mode) Note 35. MCKO is not available at EXT Master mode. tLRCKH LRCK 50%DVDD tBCK tDBF dBCK BICK (BCKP = "0") 50%DVDD BICK (BCKP = "1") 50%DVDD tBSD SDTO MSB tSDS 50%DVDD tSDH VIH SDTI VIL Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”) MS0477-E-01 2006/10 - 16 - ASAHI KASEI [AK4644] tLRCKH LRCK 50%DVDD tBCK tDBF dBCK BICK (BCKP = "1") 50%DVDD BICK (BCKP = "0") 50%DVDD tBSD SDTO 50%DVDD MSB tSDS tSDH VIH SDTI VIL Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”) 50%DVDD LRCK tBLR tBCKL BICK 50%DVDD tLRD tBSD SDTO 50%DVDD tSDS tSDH VIH SDTI VIL Figure 6. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode) MS0477-E-01 2006/10 - 17 - ASAHI KASEI [AK4644] 1/fs VIH LRCK VIL tLRCKH tBLR tBCK VIH BICK (BCKP = "0") VIL tBCKH tBCKL VIH BICK (BCKP = "1") VIL Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “0”) 1/fs VIH LRCK VIL tLRCKH tBLR tBCK VIH BICK (BCKP = "1") VIL tBCKH tBCKL VIH BICK (BCKP = "0") VIL Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”) MS0477-E-01 2006/10 - 18 - ASAHI KASEI [AK4644] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRCKH tLRCKL tBCK Duty = tLRCKH x fs x 100 = tLRCKL x fs x 100 VIH BICK VIL tBCKH tBCKL fMCK 50%DVDD MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin, Except DSP mode) tLRCKH VIH LRCK VIL tLRB VIH BICK VIL (BCKP = "0") VIH BICK (BCKP = "1") VIL tBSD SDTO MSB tSDS 50%DVDD tSDH VIH SDTI MSB VIL Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”) MS0477-E-01 2006/10 - 19 - ASAHI KASEI [AK4644] tLRCKH VIH LRCK VIL tLRB VIH BICK VIL (BCKP = "1") VIH BICK (BCKP = "0") VIL tBSD SDTO 50%DVDD MSB tSDS tSDH VIH SDTI MSB VIL Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS = “1”) 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK VIH BICK VIL tBCKH tBCKL Figure 12. Clock Timing (EXT Slave mode) MS0477-E-01 2006/10 - 20 - ASAHI KASEI [AK4644] VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSD tLRD SDTO 50%DVDD MSB tSDH tSDS VIH SDTI VIL Figure 13. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode) VIH CSN VIL tCCKL tCSS tCCKH VIH CCLK VIL tCCK tCDH tCDS VIH CDTI C1 C0 R/W VIL Figure 14. WRITE Command Input Timing MS0477-E-01 2006/10 - 21 - ASAHI KASEI [AK4644] tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 15. WRITE Data Input Timing VIH SDA VIL tBUF tLOW tHIGH tR tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 16. I2C Bus Mode Timing PMADL bit or PMADR bit tPDV SDTO 50%DVDD Figure 17. Power Down & Reset Timing 1 tPD PDN VIL Figure 18. Power Down & Reset Timing 2 MS0477-E-01 2006/10 - 22 - ASAHI KASEI [AK4644] OPERATION OVERVIEW System Clock There are the following four clock modes to interface with external devices (see Table 2 and Table 3). Mode PMPLL bit M/S bit PLL3-0 bits Figure PLL Master Mode (Note 36) 1 1 See Table 5 Figure 19 PLL Slave Mode 1 1 0 See Table 5 Figure 20 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 Figure 21 1 0 See Table 5 (PLL Reference Clock: LRCK or BICK pin) Figure 22 EXT Slave Mode 0 0 x Figure 23 EXT Master Mode 0 1 x Figure 24 Note 36. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid clocks are output from MCKO pin when MCKO bit is “1”. Table 2. Clock Mode Setting (x: Don’t care) Mode MCKO bit 0 PLL Master Mode 1 0 PLL Slave Mode (PLL Reference Clock: MCKI pin) 1 MCKO pin “L” Selected by PS1-0 bits “L” Selected by PS1-0 bits MCKI pin Selected by PLL3-0 bits Selected by PLL3-0 bits PLL Slave Mode (PLL Reference Clock: LRCK or BICK pin) 0 “L” GND EXT Slave Mode 0 “L” Selected by FS1-0 bits EXT Master Mode 0 “L” Selected by FS1-0 bits BICK pin Output (Selected by BCKO bit) LRCK pin Input (≥ 32fs) Input (1fs) Input (Selected by PLL3-0 bits) Input (≥ 32fs) Output (Selected by BCKO bit) Output (1fs) Input (1fs) Input (1fs) Output (1fs) Table 3. Clock pins state in Clock Mode Master Mode/Slave Mode The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK4644 is power-down mode (PDN pin = “L”) and exits reset state, the AK4644 is slave mode. After exiting reset state, the AK4644 goes to master mode by changing M/S bit = “1”. When the AK4644 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK4644 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state. M/S bit Mode 0 Slave Mode 1 Master Mode Table 4. Select Master/Slave Mode MS0477-E-01 Default 2006/10 - 23 - ASAHI KASEI [AK4644] PLL Mode (AIN3 bit = “0”, PMPLL bit = “1”) When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 5, whenever the AK4644 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. When AIN3 bit = “1”, the PLL is not available. 1) Setting of PLL Mode Mode PLL3 bit PLL2 bit PLL1 bit PLL0 bit PLL Reference Clock Input Pin Input Frequency 0 1 2 0 0 0 0 0 0 0 0 1 0 1 0 LRCK pin N/A BICK pin 1fs 32fs 3 0 0 1 1 BICK pin 64fs 4 5 6 7 12 13 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Others Others R and C of VCOC pin C[F] R[Ω] 6.8k 220n 10k 4.7n 10k 10n 10k 4.7n 10k 10n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz N/A Table 5. Setting of PLL Mode (*fs: Sampling Frequency) PLL Lock Time (max) 160ms 2ms 4ms 2ms 4ms 40ms 40ms 40ms 40ms 40ms 40ms Default 2) Setting of sampling frequency in PLL Mode When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 6. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz Default 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 4 0 1 0 0 7.35kHz 5 0 1 0 1 11.025kHz 6 0 1 1 0 14.7kHz 7 0 1 1 1 22.05kHz 10 1 0 1 0 32kHz 11 1 0 1 1 48kHz 14 1 1 1 0 29.4kHz 15 1 1 1 1 44.1kHz Others Others N/A Table 6. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (Reference Clock = MCKI pin) When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3 and FS1-0 bits. (See Table 7) FS2 bit is “don’t care”. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 0 Don’t care 0 Default 0 0 7.35kHz ≤ fs ≤ 8kHz 0 Don’t care 1 1 0 8kHz < fs ≤ 12kHz 0 Don’t care 0 2 1 12kHz < fs ≤ 16kHz 0 Don’t care 1 3 1 16kHz < fs ≤ 24kHz 1 Don’t care 0 6 1 24kHz < fs ≤ 32kHz 1 Don’t care 1 7 1 32kHz < fs ≤ 48kHz Others Others N/A Table 7. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” (Reference Clock = LRCK or BICK pin) MS0477-E-01 2006/10 - 24 - ASAHI KASEI [AK4644] PLL Unlock State 1) PLL Master Mode (AIN3 bit = “0”; PMPLL bit = “1”, M/S bit = “1”) In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, MCKO pin goes to “L” (see Table 8). After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state after a period of 1/fs. When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by setting PMPLL bit to “0”. MCKO pin BICK pin MCKO bit = “0” MCKO bit = “1” After that PMPLL bit “0” Æ “1” “L” Output Invalid “L” Output PLL Unlock (except above case) “L” Output Invalid Invalid PLL Lock “L” Output See Table 10 See Table 11 Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) PLL State LRCK pin “L” Output Invalid 1fs Output 2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”) In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. After that, the clock selected by Table 10 is output from MCKO pin when PLL is locked. ADC and DAC output invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACH and DACS bits. MCKO pin MCKO bit = “0” MCKO bit = “1” After that PMPLL bit “0” Æ “1” “L” Output Invalid PLL Unlock “L” Output Invalid PLL Lock “L” Output Output Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”) PLL State MS0477-E-01 2006/10 - 25 - ASAHI KASEI [AK4644] PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (see Table 10) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (see Table 11). 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz DSP or µP AK4644 MCKI 256fs/128fs/64fs/32fs MCKO 32fs, 64fs BICK 1fs LRCK MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 19. PLL Master Mode Mode PS1 bit PS0 bit MCKO pin 0 0 0 256fs Default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs Table 10. MCKO Output Frequency (PLL Mode, MCKO bit = “1”) BICK Output Frequency 0 32fs Default 1 64fs Table 11. BICK Output Frequency at Master Mode BCKO bit MS0477-E-01 2006/10 - 26 - ASAHI KASEI [AK4644] PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4644 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 5). a) PLL reference clock: MCKI pin BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 10) and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits (see Table 6) 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz AK4644 DSP or µP MCKI MCKO BICK LRCK 256fs/128fs/64fs/32fs ≥ 32fs 1fs MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) MS0477-E-01 2006/10 - 27 - ASAHI KASEI [AK4644] b) PLL reference clock: BICK or LRCK pin Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (see Table 7) AK4644 DSP or µP MCKO MCKI BICK LRCK 32fs or 64fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 21. PLL Slave Mode 2 (PLL Reference Clock: BICK pin) AK4644 DSP or µP MCKO MCKI BICK LRCK ≥ 32fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 22. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin) The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4644 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). MS0477-E-01 2006/10 - 28 - ASAHI KASEI [AK4644] EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4644 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see Table 12). Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range Don’t care 0 0 256fs 7.35kHz ∼ 48kHz Don’t care 0 1 1024fs 7.35kHz ∼ 13kHz Don’t care 1 0 256fs 7.35kHz ∼ 48kHz Don’t care 1 1 512fs 7.35kHz ∼ 26kHz Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) FS3-2 bits FS1 bit FS0 bit Default The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output through LOUT/ROUT pins at fs=8kHz is shown in Table 13. S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 512fs 93dB 1024fs 93dB Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4644 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). AK4644 DSP or µP MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK MCLK ≥ 32fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 23. EXT Slave Mode MS0477-E-01 2006/10 - 29 - ASAHI KASEI [AK4644] EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4644 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits (see Table 14). Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range Don’t care 0 0 256fs 7.35kHz ∼ 48kHz Don’t care 0 1 1024fs 7.35kHz ∼ 13kHz Don’t care 1 0 256fs 7.35kHz ∼ 48kHz Don’t care 1 1 512fs 7.35kHz ∼ 26kHz Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) FS3-2 bits FS1 bit FS0 bit Default The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output through LOUT/ROUT pins at fs=8kHz is shown in Table 15. S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 512fs 93dB 1024fs 93dB Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If MCKI is not provided, the AK4644 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). AK4644 DSP or µP MCKO 256fs, 512fs or 1024fs MCKI MCLK 32fs or 64fs BICK 1fs LRCK BCLK LRCK SDTO SDTI SDTI SDTO Figure 24. EXT Master Mode BICK Output Frequency 0 32fs Default 1 64fs Table 16. BICK Output Frequency at Master Mode BCKO bit MS0477-E-01 2006/10 - 30 - ASAHI KASEI [AK4644] System Reset Upon power-up, the AK4644 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC bits is “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2’s compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete. When PMDAC bit is “1”, the ADC does not require an initialization cycle. The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2’s compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. Audio Interface Format Four types of data formats are available and are selected by setting the DIF1-0 bits (seeTable 17). In all modes, the serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK are output from the AK4644 in master mode, but must be input to the AK4644 in slave mode. Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO (ADC) SDTI (DAC) DSP Mode DSP Mode MSB justified LSB justified MSB justified MSB justified I2S compatible I2S compatible Table 17. Audio Interface Format BICK ≥ 32fs ≥ 32fs ≥ 32fs ≥ 32fs Figure Table 18 Figure 29 Figure 30 Figure 31 Default In modes 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”). In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 18). DIF1 0 DIF0 MSBS BCKP 0 0 0 1 1 0 1 1 0 Audio Interface Format MSB of SDTO is output by the rising edge (“↑”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the falling edge (“↓”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by the falling edge (“↓”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the rising edge (“↑”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by next rising edge (“↑”) of the falling edge (“↓”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the falling edge (“↓”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by next falling edge (“↓”) of the rising edge (“↑”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the rising edge (“↑”) of the BICK just after the output timing of SDTO’s MSB. Table 18. Audio Interface Format in Mode 0 Figure Figure 25 Default Figure 26 Figure 27 Figure 28 If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit data. MS0477-E-01 2006/10 - 31 - ASAHI KASEI [AK4644] LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 18 24 25 26 27 26 29 30 31 0 BICK(32fs) Lch SDTO(o) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 Lch SDTI(i) 0 15 15 14 0 1 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 8 7 14 2 6 15 5 16 4 17 3 2 18 1 30 0 31 15 14 32 33 46 34 47 48 49 50 26 27 26 62 63 30 31 BICK(64fs) Lch SDTO(o) Rch 15 14 2 1 0 15 14 SDTI(i) 2 1 0 2 1 0 Rch Lch 15 14 2 1 0 15 14 1/fs 15:MSB, 0:LSB Figure 25. Mode 0 Timing (BCKP = “0”, MSBS = “0”) LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 18 24 25 29 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 34 46 47 48 49 50 62 63 BICK(64fs) Lch SDTO(o) 15 14 Rch 2 1 0 SDTI(i) 15 14 15 14 2 1 0 2 1 0 Rch Lch 2 1 0 15 14 1/fs 15:MSB, 0:LSB Figure 26. Mode 0 Timing (BCKP = “1”, MSBS = “0”) MS0477-E-01 2006/10 - 32 - ASAHI KASEI [AK4644] LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 18 24 25 26 27 26 29 30 31 0 BICK(32fs) Lch SDTO(o) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 Lch SDTI(i) 0 15 15 14 0 1 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 8 7 14 2 6 15 5 16 4 17 3 2 18 1 30 0 31 15 14 32 33 46 34 47 48 49 50 26 27 26 62 63 30 31 BICK(64fs) Lch SDTO(o) Rch 15 14 2 1 0 15 14 Lch SDTI(i) 2 1 0 2 1 0 Rch 15 14 2 1 0 15 14 1/fs 15:MSB, 0:LSB Figure 27. Mode 0 Timing (BCKP = “0”, MSBS = “1”) LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 18 24 25 29 0 BICK(32fs) Lch SDTO(o) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 Lch SDTI(i) 0 15 15 14 0 1 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 8 7 14 2 6 15 5 16 4 17 3 2 18 1 30 0 31 15 14 32 33 34 46 47 48 49 50 62 63 BICK(64fs) Lch SDTO(o) 15 14 Rch 2 1 0 2 1 0 Lch SDTI(i) 15 14 15 14 2 1 0 2 1 0 Rch 15 14 1/fs 15:MSB, 0:LSB Figure 28. Mode 0 Timing (BCKP = “1”, MSBS = “1”) MS0477-E-01 2006/10 - 33 - ASAHI KASEI [AK4644] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 1 0 15 14 13 Don't Care 15 14 13 15 14 1 0 1 0 Don't Care 15 15 14 2 1 0 15:MSB, 0:LSB Lch Data Rch Data Figure 29. Mode 1 Timing LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 13 1 0 SDTI(i) 15 14 13 1 0 Don't Care 15 14 13 1 0 15 14 13 1 0 15 Don't Care 15 15:MSB, 0:LSB Lch Data Rch Data Figure 30. Mode 2 Timing MS0477-E-01 2006/10 - 34 - ASAHI KASEI [AK4644] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 SDTI(i) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don't Care 15 14 2 1 0 15 14 2 1 0 Don't Care 15:MSB, 0:LSB Lch Data Rch Data Figure 31. Mode 3 Timing Mono/Stereo Mode PMADL, PMADR and MIX bits set mono/stereo ADC operation. When MIX bit = “1”, EQ and FIL3 bits should be set to “0”. ALC operation (ALC bit = “1”) or digital volume operation (ALC bit = “0”) is applied to the data in Table 19. PMADL bit 0 0 1 1 PMADR bit 0 1 0 MIX bit ADC Lch data ADC Rch data x All “0” All “0” x Rch Input Signal Rch Input Signal x Lch Input Signal Lch Input Signal 0 Lch Input Signal Rch Input Signal 1 1 (L+R)/2 (L+R)/2 Table 19. Mono/Stereo ADC operation (x: Don’t care) Default Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz (@fs=44.1kHz) and scales with sampling rate (fs). When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is disabled. MS0477-E-01 2006/10 - 35 - ASAHI KASEI [AK4644] MIC/LINE Input Selector The AK4644 has input selector for MIC-Amp. When MDIF1 and MDIF2 bits are “0”, INL1-0 and INR1-0 bits select LIN1/LIN2/LIN3 and RIN1/RIN2/RIN3, respectively. When MDIF1 and MDIF2 bits are “1”, LIN1, RIN1, LIN2 and RIN2 pins become IN1−, IN1+, IN2+ and IN2− pins respectively. In this case, full-differential input is available (Figure 33). When full-differential input is used, the signal should not be input to the pins marked by “X” in Table 21. MDIF1 bit 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Others MDIF2 bit 0 0 0 0 0 0 0 0 0 1 1 0 0 1 INL1 bit 0 0 0 0 0 0 1 1 1 0 1 0 0 0 INL0 bit 0 0 0 1 1 1 0 0 0 0 0 0 0 0 INR1 bit 0 0 1 0 0 1 0 0 1 0 0 0 1 0 INR0 bit 0 1 0 0 1 0 0 1 0 0 0 1 0 0 Lch LIN1 LIN1 LIN1 LIN2 LIN2 LIN2 LIN3 LIN3 LIN3 LIN1 LIN3 IN1+/− IN1+/− IN1+/− N/A Rch RIN1 RIN2 RIN3 RIN1 RIN2 RIN3 RIN1 RIN2 RIN3 IN2+/− IN2+/− RIN2 RIN3 IN2+/− N/A Default Table 20. MIC/Line In Path Select Register Pin RIN2 LIN1 MIN VCOC RIN1 LIN2 AIN3 bit MDIF1 bit MDIF2 bit LIN3 RIN3 IN1+ IN2+ IN2− IN1− 0 0 0 O O O O O 0 0 1 O X O O O 0 1 0 O O X O O 0 1 1 O O O O O 1 0 0 O O O O O O 1 0 1 O X O O O X 1 1 0 O O X O X O 1 1 1 O O O O X X Table 21. Handling of MIC/Line Input Pins (“-“: N/A; “X”: Signal should not be input.) MS0477-E-01 2006/10 - 36 - ASAHI KASEI [AK4644] AK4644 INL1-0 bits LIN1/IN1− pin ADC Lch RIN1/IN1+ pin MIC-Amp MDIF1 bit INR1-0 bits RIN2/IN2− pin ADC Rch LIN2/IN2+ pin MIC-Amp MDIF2 bit These blocks are not available at PLL mode. PMAINR3 bit PMAINL3 bit PMAINL2 bit PMAINR2 bit MICL3 bit VCOC/RIN3 pin MICR3 bit MIN/LIN3 pin Lineout, Receiver-Amp, HP-Amp, SPK-Amp Figure 32. Mic/Line Input Selector AK4644 MPWR pin 1k IN1− pin MIC-Amp IN1+ pin A/D SDTO pin 1k Figure 33. Connection Example for Full-differential Mic Input (MDIF1/2 bits = “1”) <Input Selector Setting Example> In case that IN1+/− pins are used as full-differential mic input and LIN2/RIN2 pins are used as stereo line input, it is recommended that the following two modes are set by register setting according to each case. MDIF1 bit 1 0 MDIF2 bit 0 0 INL1 bit INL0 bit INR1 bit INR0 bit 0 0 0 1 0 1 0 1 Table 22. MIC/Line In Path Select Example MS0477-E-01 Lch IN1+/− LIN2 Rch RIN2 RIN2 2006/10 - 37 - ASAHI KASEI [AK4644] MIC Gain Amplifier The AK4644 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see Table 23). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01”, “10” or “11”. MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 23. Mic Input Gain Default MIC Power When PMMP bit = “1”, the MPWR pin supplies power for the microphone. This output voltage is typically 0.75 x AVDD and the load resistance is minimum 0.5kΩ. In case of using two sets of stereo mic, the load resistance is minimum 2kΩ for each channel. No capacitor must not be connected directly to MPWR pin (see Figure 34). PMMP bit MPWR pin 0 Hi-Z 1 Output Table 24. MIC Power Default MIC Power ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ MPWR pin Microphone LIN1 pin Microphone RIN1 pin Microphone LIN2 pin Microphone RIN2 pin Figure 34. MIC Block Circuit MS0477-E-01 2006/10 - 38 - ASAHI KASEI [AK4644] Digital EQ/HPF/LPF The AK4644 performs wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic Level Control) by digital domain for A/D converted data (Figure 35). FIL1, FIL3 and EQ blocks are IIR filters of 1st order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operation” about ALC. When only DAC is powered-up, digital EQ/HPF/LPF circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, digital EQ/HPF/LPF circuit operates at recording path. Even if the path is switched from recording to playback, the register setting of filter coefficient at recording remains. Therefore, FIL3, EQ, FIL1 and GN1-0 bits should be set to “0” if digital EQ/HPF/LPF is not used for playback path. PMADL bit, PMADR bit PMDAC bit 0 1 0 LOOP bit Status Digital EQ/HPF/LPF x Power-down Power-down “00” x Playback Playback path x Recording Recording path “01”, “10” or “11” 0 Recording & Playback Recording path 1 1 Recording Monitor Playback Recording path Note 37. Stereo separation emphasis circuit is effective only at stereo operation. Table 25. Digital EQ/HPF/LPF Cirtcuit Setting (x: Don’t care) Default FIL3 coefficient also sets the attenuation of the stereo separation emphasis. The combination of GN1-0 bit (Table 26) and EQ coefficient set the compensation gain. FIL1 and FIL3 blocks become HPF when F1AS and F3AS bits are “0” and become LPF when F1AS and F3AS bits are “1”, respectively. When EQ and FIL1 bits are “0”, EQ and FIL1 blocks become “through” (0dB). When FIL3 bit is “0”, FIL3 block become “MUTE”. When each filter coefficient is changed, each filter should be set to “through” (“MUTE” in case of FIL3). When MIX bit = “1”, only FIL1 is available. In this case, EQ and FIL3 bits should be set to “0”. Wind-noise reduction FIL1 An y coefficient F1A13-0 F1B13-0 F1AS Stereo separation emphasis FIL3 Gain compensation EQ An y coefficient 0dB ∼ -10dB F3A13-0 MUTE F3B13-0 (set by F3AS FIL3 coefficient) Gain ALC An y coefficient GN1-0 EQA15-0 +24/+12/0dB EQB13-0 EQC15-0 +12dB ∼ 0dB Figure 35. Digital EQ/HPF/LPF GN1 GN0 Gain 0 0 0dB Default 0 1 +12dB 1 x +24dB Table 26. Gain select of gain block (x: Don’t care) MS0477-E-01 2006/10 - 39 - ASAHI KASEI [AK4644] [Filter Coefficient Setting] 1) When FIL1 and FIL2 are set to “HPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of should be set to 0dB.) Register setting FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 / tan (πfc/fs) A = 10K/20 x , B= 1 + 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function 1−z H(z) = A Amplitude −1 2 − 2cos (2πf/fs) M(f) = A 1 + Bz −1 Phase θ(f) = tan −1 1 + B2 + 2Bcos (2πf/fs) (B+1)sin (2πf/fs) 1 - B + (B−1)cos (2πf/fs) 2) When FIL1 and FIL2 are set to “LPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of FIL1 should be set to 0dB.) Register setting FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 A = 10K/20 x , 1 + 1 / tan (πfc/fs) Transfer function 1+z H(z) = A 1 + 1 / tan (πfc/fs) Amplitude −1 1 + Bz −1 B= 2 + 2cos (2πf/fs) M(f) = A 1 + B2 + 2Bcos (2πf/fs) MS0477-E-01 Phase θ(f) = tan −1 (B−1)sin (2πf/fs) 1 + B + (B+1)cos (2πf/fs) 2006/10 - 40 - ASAHI KASEI [AK4644] 3) EQ fs: Sampling frequency fc1: Pole frequency fc2: Zero-point frequency f: Input signal frequency K: Filter gain [dB] (Maximum +12dB) Register setting EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C (MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0) A = 10K/20 x 1 − 1 / tan (πfc1/fs) 1 + 1 / tan (πfc2/fs) , B= 1 + 1 / tan (πfc1/fs) A + Cz Amplitude −1 1 + Bz −1 C =10K/20 x 1 + 1 / tan (πfc1/fs) Transfer function H(z) = , 2 1 − 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) Phase 2 A + C + 2ACcos (2πf/fs) M(f) = 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (AB−C)sin (2πf/fs) A + BC + (AB+C)cos (2πf/fs) [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 213 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit. [Filter Coefficient Setting Example] 1) FIL1 block Example: HPF, fs=44.1kHz, fc=100Hz F1AS bit = “0” F1A[13:0] bits = 01 1111 1100 0110 F1B[13:0] bits = 10 0000 0111 0100 2) EQ block Example: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB Gain[dB] +8dB fc1 fc2 Frequency EQA[15:0] bits = 0000 1001 0110 1110 EQB[13:0] bits = 10 0001 0101 1001 EQC[15:0] bits = 1111 1001 1110 1111 MS0477-E-01 2006/10 - 41 - ASAHI KASEI [AK4644] ALC Operation The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”. When only DAC is powered-up, ALC circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC circuit operates at recording path. PMADL bit, PMADR bit “00” PMDAC bit 0 1 0 “01”, “10” or “11” 1. 1 LOOP bit Status x Power-down x Playback x Recording 0 Recording & Playback 1 Recording Monitor Playback Table 27. ALC Setting (x: Don’t care) ALC Power-down Playback path Recording path Recording path Recording path Default ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 28), the IVL and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 29). When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both ALC limiter and recovery operation (Table 30). When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by ALC limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits. The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 28) or less. After completing the attenuation operation, unless ALC bit is changed to “0”, the operation repeats when the input signal level exceeds LMTH1-0 bits. LMTH1 0 0 1 1 LMTH0 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level 0 ALC Output ≥ −2.5dBFS −2.5dBFS > ALC Output ≥ −4.1dBFS 1 ALC Output ≥ −4.1dBFS −4.1dBFS > ALC Output ≥ −6.0dBFS 0 ALC Output ≥ −6.0dBFS −6.0dBFS > ALC Output ≥ −8.5dBFS 1 ALC Output ≥ −8.5dBFS −8.5dBFS > ALC Output ≥ −12dBFS Table 28. ALC Limiter Detection Level / Recovery Counter Reset Level ZELMN 0 1 ZTM1 ZTM0 0 0 1 1 0 1 0 1 LMAT1 LMAT0 ALC Limiter ATT Step 0 0 1 step 0.375dB 0 1 2 step 0.750dB 1 0 4 step 1.500dB 1 1 8 step 3.000dB x x 1step 0.375dB Table 29. ALC Limiter ATT Step (x: Don’t care) Default Zero Crossing Timeout Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 30. ALC Zero Crossing Timeout Period MS0477-E-01 Default Default 2006/10 - 42 - ASAHI KASEI 2. [AK4644] ALC Recovery Operation The ALC recovery operation waits for the WTM2-0 bits (Table 31) to be set after completing the ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 28) during the wait time, the ALC recovery operation is done. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 32) up to the set reference level (Table 33) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 30). Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation is done at a period set by WTM2-0 bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, the ALC recovery operation waits until WTM2-0 period and the next recovery operation is done. If ZTM1-0 is longer than WTM2-0 and no zero crossing occurs, the ALC recovery operation is done at a period set by ZTM1-0 bits. For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, IVOL is changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the reference level (REF7-0), the IVOL values are not increased. When “ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)” during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When “ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”, the waiting timer of ALC recovery operation starts. The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation (Fast Recovery Operation). When large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. The speed of fast recovery operation is set by RFST1-0 bits (Table 34). WTM2 WTM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 ALC Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 0 128/fs 16ms 8ms 2.9ms 1 256/fs 32ms 16ms 5.8ms 0 512/fs 64ms 32ms 11.6ms 1 1024/fs 128ms 64ms 23.2ms 0 2048/fs 256ms 128ms 46.4ms 1 4096/fs 512ms 256ms 92.9ms 0 8192/fs 1024ms 512ms 185.8ms 1 16384/fs 2048ms 1024ms 371.5ms Table 31. ALC Recovery Operation Waiting Period WTM0 RGAIN1 0 0 1 1 RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 32. ALC Recovery GAIN Step MS0477-E-01 Default Default 2006/10 - 43 - ASAHI KASEI [AK4644] REF7-0 GAIN(dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 0.375dB E1H +30.0 Default E0H +29.625 : : 03H −53.25 02H −53.625 01H −54.0 00H MUTE Table 33. Reference Level at ALC Recovery operation RFST1 bit 0 0 1 1 RFST0 bit Recovery Speed 0 4 times 1 8 times 0 16times 1 N/A Table 34. Fast Recovery Speed Setting MS0477-E-01 Default 2006/10 - 44 - ASAHI KASEI 3. [AK4644] Example of ALC Operation Table 35 shows the examples of the ALC setting for mic recording. Register Name Comment LMTH1-0 ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM2-0 bits should be the same or longer data as ZTM1-0 bits. Maximum gain at recovery operation WTM2-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 RFST1-0 ALC Gain of IVOL Limiter ATT step Recovery GAIN step Fast Recovery Speed ALC enable Data 01 0 01 fs=8kHz Operation −4.1dBFS Enable 32ms Data 01 0 11 fs=44.1kHz Operation −4.1dBFS Enable 23.2ms 001 32ms 011 23.2ms E1H +30dB E1H +30dB E1H +30dB E1H +30dB 00 00 00 1 1 step 1 step 4 times Enable 00 1 step 00 1 step 00 4 times 1 Enable Table 35. Example of the ALC setting The following registers should not be changed during the ALC operation. These bits should be changed after the ALC operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”. • LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0 Example: Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Zero Crossing Timeout Period = 32ms@8kHz Limiter and Recovery Step = 1 Fast Recovery Speed = 4 step Gain of IVOL = +30dB Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS ALC bit = “1” Manual Mode WR (ZTM1-0, WTM2-0, RFST1-0) (1) Addr=06H, Data=14H WR (REF7-0) (2) Addr=08H, Data=E1H WR (IVL/R7-0) * The value of IVOL should be (3) Addr=09H&0CH, Data=E1H the same or smaller than REF’s WR (RGAIN1, LMTH1) (4) Addr=0BH, Data=00H WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”) (5) Addr=07H, Data=21H ALC Operation Note : WR : Write Figure 36. Registers set-up sequence at ALC operation MS0477-E-01 2006/10 - 45 - ASAHI KASEI [AK4644] Input Digital Volume (Manual Mode) The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below. 1. 2. 3. After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH1-0 and etc) When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed. For example; when the change of the sampling frequency. When IVOL is used as a manual volume. IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 36). The IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or IVR7-0 bits are written during PMADL=PMADR bits = “0”, IVOL operation starts with the written values at the end of the ADC initialization cycle after PMADL or PMADR bit is changed to “1”. Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and IVR7-0 bits should be set to “91H” (0dB). IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H GAIN (dB) Step +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : −53.25 −53.625 −54 MUTE Table 36. Input Digital Volume Setting MS0477-E-01 Default 2006/10 - 46 - ASAHI KASEI [AK4644] When writing to the IVL7-0 and IVR7-0 bits continuouslly, the control register should be written by an interval more than zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write operation. If the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and zero crossing counter is not reset. Therefore, IVL and IVR can be written by an interval less than zero crossing timeout. ALC bit ALC Status Disable Enable IVL7-0 bits E1H(+30dB) IVR7-0 bits C6H(+20dB) Internal IVL E1H(+30dB) Internal IVR C6H(+20dB) E1(+30dB) --> F1(+36dB) (1) Disable E1(+30dB) (2) E1(+30dB) --> F1(+36dB) C6H(+20dB) Figure 37. IVOL value during ALC operation (1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. The wait time from ALC bit = “1” to ALC operation start by IVL7-0 bits is at most recovery time (WTM2-0 bits) plus zerocross timeout period (ZTM1-0 bits). (2) Writing to IVL and IVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the IVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1” by an interval more than zero crossing timeout period after ALC bit = “0”. MS0477-E-01 2006/10 - 47 - ASAHI KASEI [AK4644] De-emphasis Filter The AK4644 includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 37). DEM1 0 0 1 1 DEM0 Mode 0 44.1kHz 1 OFF Default 0 48kHz 1 32kHz Table 37. De-emphasis Control Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 38). If the BST1-0 bits are set to “01” (MIN Level), use a 47µF capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog output clips to the full scale. Figure 38 shows the boost frequency response at –20dB signal input. Boost Filter (fs=44.1kHz) 0 MAX Level [dB] -5 MID -10 MIN -15 -20 -25 10 100 1000 10000 Frequency [Hz] Figure 38. Bass Boost Frequency Response (fs=44.1kHz) BST1 0 0 1 1 BST0 Mode 0 OFF 1 MIN 0 MID 1 MAX Table 38. Bass Boost Control MS0477-E-01 Default 2006/10 - 48 - ASAHI KASEI [AK4644] Digital Output Volume The AK4644 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = “0”, the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has a soft transition function. The DVTM bit sets the transition time between set values of DVL/R7-0 bits as either 1061/fs or 256/fs (Table 40). When DVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs (=24ms@fs=44.1kHz) from 00H (+12dB) to FFH (MUTE). DVL/R7-0 Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB : : 18H 0dB Default : : FDH −114.5dB FEH −115.0dB FFH MUTE (−∞) Table 39. Digital Volume Code Table DVTM bit 0 1 Transition time between DVL/R7-0 bits = 00H and FFH Setting fs=8kHz fs=44.1kHz 1061/fs 133ms 24ms 256/fs 32ms 6ms Table 40. Transition Time Setting of Digital Output Volume MS0477-E-01 Default 2006/10 - 49 - ASAHI KASEI [AK4644] Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by −∞ (“0”) during the cycle set by the DVTM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the value set by the DVL/R7-0 bits during the cycle set of the DVTM bit. If the soft mute is cancelled within the cycle set by the DVTM bit after starting the operation, the attenuation is discontinued and returned to the value set by the DVL/R7-0 bits. The soft mute is effective for changing the signal source without stopping the signal transmission (Figure 39). SM U T E bit D VTM bit D V L/R 7-0 bits D V TM bit (1) (3) Attenuation -∞ GD (2) GD Analog O utput Figure 39. Soft Mute Function (1) The output signal is attenuated until −∞ (“0”) by the cycle set by the DVTM bit. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0477-E-01 2006/10 - 50 - ASAHI KASEI [AK4644] Analog Mixing: Stereo Input (LIN2/RIN2, AIN3 bit = “1”: LIN3/RIN3 pins) When PMAINL2=PMAINR2 bits = “1”, LIN2 and RIN2 pins can be used as stereo line input for analog mixing. When the LINH2 and RINH2 bits are set to “1”, the input signal from the LIN2/RIN2 pins is output to Headphone-Amp. When the LINL2/RINR2 bits are set to “1”, the input signal from the LIN2/RIN2 pins is output to the stereo line output amplifier. When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. In this case, the input resistance of LIN2/RIN2 pins becomes 30kΩ (typ) at MGAIN1-0 bits = “00” and 20kΩ (typ) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. When AIN3 bit = “1”, MIN and VCOC pins becomes LIN3 and RIN3 pins, respectively. In this case, PLL is not available. When PMAINL3=PMAINR3 bits = “1”, LIN2 and RIN2 pins can be used as stereo line input for analog mixing. When PMMICL=PMMICR=MICL3=MICR3 bits = “1”, analog mixing source is changed from LIN3/RIN3 input to MIC-Amp output signal. When the LINH3 and RINH3 bits are set to “1”, the input signal from the LIN3/RIN3 pins is output to Headphone-Amp. When the LINL3/RINR3 bits are set to “1”, the input signal from the LIN3/RIN3 pins is output to the stereo line output amplifier. When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. When the analog mixing is used at MICL3=MICR3 bits = “0”, the input resistance of LIN3/RIN3 pins becomes 30kΩ (typ) at MGAIN1-0 bits = “00” and 20kΩ (typ) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. When the analog mixing is used at MICL3=MICR3 bits = “1”, the input resistance of LIN3/RIN3 pins becomes 60kΩ (typ) at MGAIN1-0 bits = “00” and 30kΩ (typ) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. Table 41, Table 42 and Table 43 show the typical gain. AK4644 INL1-0 bits LIN1/IN1− pin ADC Lch RIN1/IN1+ pin MIC-Amp MDIF1 bit INR1-0 bits RIN2/IN2− pin ADC Rch LIN2/IN2+ pin MIC-Amp MDIF2 bit These blocks are not available at PLL mode. MIN/LIN3 pin MICL3 bit MICR3 bit PMAINL3 bit PMAINR3 bit PMAINR2 bit PMAINL2 bit VCOC/RIN3 pin Lineout, Receiver-Amp, HP-Amp Figure 40. Analog Mixing Circuit MS0477-E-01 2006/10 - 51 - ASAHI KASEI [AK4644] PMAINL2 bit PMAINR2 bit LINL2/RINR2 LOUT/RCP pin, ROUT/RCN pin LIN2/RIN2 LINH2/RINH2 HPL, HPR pin Figure 41. Analog Mixing Circuit (LIN2/RIN2) PMAINL3 bit PMAINR3 bit LINL3/RINR3 LOUT/RCP pin, ROUT/RCN pin LIN3/RIN3 LINH3/RINH3 HPL, HPR pin Figure 42. Analog Mixing Circuit (LIN3/RIN3; PLL is not available) LOVL bit LIN2/RIN2/LIN3/RIN3 Æ LOUT/ROUT 0 0dB Default 1 +2dB Table 41. LIN2/RIN2/LIN3/RIN3 Input Æ LOUT/ROUT Output Gain (typ) LOVL bit LIN2/RIN2/LIN3/RIN3 Æ RCP/RCN 0 0dB Default 1 +2dB Table 42. LIN2/RIN2/LIN3/RIN3 Input Æ RCP/RCN Output Gain (typ) HPG bit LIN2/RIN2/LIN3/RIN3 Æ HPL/HPR 0 0dB Default 1 +3.6dB Table 43. LIN2/RIN2/LIN3/RIN3 Input Æ Headphone-Amp Output Gain (typ) MS0477-E-01 2006/10 - 52 - ASAHI KASEI [AK4644] Analog Mixing: Mono Input (MIN pin) When AIN3 bit = “0”, MIN pin is used as mono input for analog mixing. When the PMMIN bit is set to “1”, the mono input is powered-up. When the MINH bit is set to “1”, the input signal from the MIN pin is output to Headphone-Amp. When the MINL bit is set to “1”, the input signal from the MIN pin is output to the stereo line output amplifier. The external resister Ri adjusts the signal level of MIN input. Table 44, Table 45 and Table 46 show the typical gain example at Ri = 20kΩ. This gain is in inverse proportion to Ri . Ri MINL MIN LOUT/RCP pin, ROUT/RCN pin MINH HPL, HPR pin Figure 43. Block Diagram of MIN pin LOVL bit MIN Æ LOUT/ROUT 0 0dB Default 1 +2dB Table 44. MIN Input Æ LOUT/ROUT Output Gain (typ) at Ri = 20kΩ LOVL bit MIN Æ RCP/RCN 0 +0dB Default 1 +2dB Table 45. MIN Input Æ RCP/RCN Output Gain (typ) at Ri = 20kΩ HPG bit MIN Æ HPL/HPR 0 Default −20dB 1 −16.4dB Table 46. MIN Input Æ Headphone-Amp Output Gain (typ) at Ri = 20kΩ MS0477-E-01 2006/10 - 53 - ASAHI KASEI [AK4644] Stereo Line Output (LOUT/ROUT pins) When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ (min.). When the PMLO=LOPS bits = “0”, the stereo line output enters power-down mode and the output is pulled-down to AVSS by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to AVSS by 20kΩ after AC coupled as Figure 45. Rise/Fall time is 300ms(max) at C=1µF and AVDD=3.3V. When PMLO=LOPS bits = “1”, stereo line output is in normal operation. LOVL bit set the gain of stereo line output. “DACL” “LOVL” LOUT pin DAC ROUT pin Figure 44. Stereo Line Output LOPS 0 1 PMLO Mode LOUT/ROUT pin 0 Power-down Pull-down to AVSS 1 Normal Operation Normal Operation 0 Power-save Fall down to AVSS 1 Power-save Rise up to VCOM Table 47. Stereo Line Output Mode Select (x: Don’t care) Default LOVL Gain Output Voltage (typ) 0 0dB 0.6 x AVDD Default 1 +2dB 0.757 x AVDD Table 48. Stereo Line Output Volume Setting LOUT ROUT 1µF 220Ω 20kΩ Figure 45. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit) MS0477-E-01 2006/10 - 54 - ASAHI KASEI [AK4644] <Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)> (2 ) (5 ) P M L O b it (1 ) (3 ) (4 ) (6 ) L O P S b it L O U T , R O U T p in s N o r m a l O u tp u t ≥ 300 m s ≥ 300 m s Figure 46. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit) (1) Set LOPS bit = “1”. Stereo line output enters the power-save mode. (2) Set PMLO bit = “1”. Stereo line output exits the power-down mode. LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1µF and AVDD=3.3V. (3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode. Stereo line output is enabled. (4) Set LOPS bit = “1”. Stereo line output enters power-save mode. (5) Set PMLO bit = “0”. Stereo line output enters power-down mode. LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1µF and AVDD=3.3V. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0477-E-01 2006/10 - 55 - ASAHI KASEI [AK4644] <Analog Mixing Circuit for Stereo Line Output> When AIN3 bit = “0”, DACL, MINL, LINL2 and RINR2 bits controls each path switch. MIN path mixing gain is 0dB(typ)@LOVL bit = “0” when the external input resistance is 20kΩ. LIN2, RIN2 and DAC pathes mixing gain is 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB MINL bit MIN pin 0dB M LOUT pin I DACL bit X 0dB DAC Lch Figure 47. LOUT Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) RINR2 bit RIN2 pin 0dB MINL bit MIN pin 0dB M ROUT pin I DACL bit X 0dB DAC Rch Figure 48. ROUT Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) When AIN3 bit = “1”, DACL, LINL2, RINR2, LINL3, RINR3, MICL3 and MICR3 bits controls each path switch. All pathes mixing gain is 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB MICL3 bit LINL3 bit LIN3 pin LIN1 pin I 0dB MIC-Amp Lch M *These blocks are not available at PLL mode. LOUT pin X DACL bit 0dB DAC Lch Figure 49. LOUT Mixing Circuit (AIN3 bit = “1”, LOVL bit = “0”) RINR2 bit RIN2 pin 0dB MICR3 bit RINR3 bit RIN3 pin RIN1 pin I 0dB MIC-Amp Rch M *These blocks are not available at PLL mode. ROUT pin X DACL bit 0dB DAC Lch Figure 50. ROUT Mixing Circuit (AIN3 bit = “1”, LOVL bit = “0”) MS0477-E-01 2006/10 - 56 - ASAHI KASEI [AK4644] Mono Reveiver Output (RCP/RCN pins) When RCV bit = “1”, LOUT/ROUT pins become RCP/RCN pins, respectively. Lch/Rch signal of DAC or LIN2/RIN2/LIN3/RIN3 is output from the RCP/RCN pins which is BTL as (L+R)/2 signal. The load impedance is 32Ω (min). When the PMLO bit = “0”, the mono receiver output enters power-down mode and the output is Hi-Z. When the PMLO bit is “1” and LOPS bit is “1”, mono receiver output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “0”. When PMLO bit = “1” and LOPS bit = “0”, mono receiver output enters in normal operation. LOVL bit set the gain of mono receiver output. “DACL” “LOVL” RCP pin DAC RCN pin Figure 51. Mono Receiver Output LOVL 0 1 PMLO 0 1 LOPS x 1 0 Gain Output Voltage (typ) +6dB Default 0.59 x AVDD @−6dBFS +8dB 0.59 x AVDD @−8dBFS Table 49. Mono Receiver Output Volume Setting Mode RCP RCN Power-down Hi-Z Hi-Z Power-save Hi-Z VCOM/2 Normal Operation Normal Operation Normal Operation Table 50. Receiver-Amp Mode Setting (x: Don’t care) Default PMLO bit LOPS bit RCP pin RCN pin Hi-Z Hi-Z Hi-Z VCOM VCOM >1ms >0 Hi-Z Figure 52. Power-up/Power-down Timing for Receiver-Amp MS0477-E-01 2006/10 - 57 - ASAHI KASEI [AK4644] <Analog Mixing Circuit for Receiver Output> When AIN3 bit = “0”, DACL, MINL, LINL2 and RINR2 bits controls each path switch. MIN path mixing gain is +6dB(typ)@LOVL bit = “0” when the external input resistance is 20kΩ. LIN2, RIN2 and DAC pathes mixing gain is 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB RINR2 bit RIN2 pin 0dB MINL bit MIN pin +6dB M RCP/N pin I DACL bit X 0dB DAC Lch DACL bit DAC Rch 0dB Figure 53. Receiver Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) When AIN3 bit = “1”, DACL, LINL2, RINR2, LINL3, RINR3, MICL3 and MICR3 bits controls each path switch. All pathes mixing gain is 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINL3 bit 0dB MIC-Amp Lch RIN2 pin *These blocks are not available at PLL mode. 0dB MICR3 bit RIN3 pin RIN1 pin RINR2 bit M RINR3 bit 0dB MIC-Amp Rch I RCP/N pin X *These blocks are not available at PLL mode. DACL bit DAC Lch 0dB DACL bit DAC Rch 0dB Figure 54. Receiver Mixing Circuit (AIN3 bit = “1”, LOVL bit = “0”) MS0477-E-01 2006/10 - 58 - ASAHI KASEI [AK4644] Headphone Output Power supply voltage for the Headphone-Amp is supplied from the HVDD pin and centered on the HVDD/2 voltage at VBAT bit = “0”. The load resistance is 16Ω (min). HPG bit selects the output voltage (see Table 51). HPG bit 0 1 Output Voltage [Vpp] 0.6 x AVDD 0.91 x AVDD Table 51. Headphone-Amp Output Voltage When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) go to “L” (HVSS). When the HPMTN bit is “1”, the common voltage rises to HVDD/2 at VBAT bit = “0”. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to HVDD voltage and the capacitor at MUTET pin. [Example]: A capacitor between the MUTET pin and ground = 1.0µF, HVDD=3.3V: Rise/fall time constant: τ = 100ms(typ), 250ms(max) Time until the common goes to HVSS when HPMTN bit = “1” Æ “0”: 500ms(max) When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) go to “L” (HVSS). PMHPL bit, PMHPR bit HPMTN bit HPL pin, HPR pin (1) (2) (3) (4) Figure 55. Power-up/Power-down Timing for Headphone-Amp (1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still HVSS. (2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising. (3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling. (4) Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are HVSS. If the power supply is switched off or Headphone-Amp is powered-down before the common voltage goes to HVSS, some POP noise occurs. MS0477-E-01 2006/10 - 59 - ASAHI KASEI [AK4644] When BOOST=OFF, the cut-off frequency (fc) of Headphone-Amp depends on the external resistor and capacitor. This fc can be shifted to lower frequency by using bass boost function. Table 52 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω. Output powers are shown at HVDD = 2.7, 3.0 and 3.3V. The output voltage of headphone is 0.6 x AVDD (Vpp). When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22µF±20% capacitor and 10Ω±20% resistor) because it has the possibility that Headphone-Amp oscillates. HP-AMP C AK4644 0.22µ R Headphone 16Ω 10Ω Figure 56. External Circuit Example of Headphone HPG bit R [Ω] 0 0 6.8 16 0 1 100 Output Power [mW]@0dBFS fc [Hz] BOOST C [µF] HVDD=3.0V HVDD=3.3V HVDD=5V =MIN AVDD=3.0V AVDD=3.3V AVDD=3.3V fs=44.1kHz 220 45 17 25.3 30.6 30.6 100 100 43 100 70 28 12.5 15.1 15.1 47 149 78 100 50 19 6.3 7.7 7.7 47 106 47 51 62 220 45 17 70 (Note 39) (Note 39) 100 100 43 22 62 25 1.1 1.3 1.3 10 137 69 Table 52. External Circuit Example Note 38. Output power at 16Ω load. Note 39. Output signal is clipped. fc [Hz] BOOST =OFF <Headphone-Amp PSRR> When HVDD is directly supplied from the battery in the mobile phone system, RF noise may influences headphone output performance. When VBAT bit is set to “1”, HP-Amp PSRR for the noise applied to HVDD is improved. In this case, HP-Amp common voltage is 0.64 x AVDD (typ). When AVDD is 3.3V, common voltage is 2.1V. Therefore, when HVDD voltage becomes lower than 4.2V, the output signal will be clipped easily. VBAT bit Common Voltage [V] 0 0.5 x HVDD Table 53. HP-Amp Common Voltage MS0477-E-01 1 0.64 x AVDD 2006/10 - 60 - ASAHI KASEI [AK4644] <Analog Mixing Circuit for Headphone Output> When AIN3 bit = “0”, DACH, MINH, LINH2 and RINH2 bits controls each path switch. MIN path mixing gain is −20dB(typ)@HPG bit = “0” when the external input resistance is 20kΩ. LIN2, RIN2 and DAC pathes mixing gain is 0dB(typ)@HPG bit = “0”. LINH2 bit LIN2 pin 0dB MINH bit −20dB MIN pin M HPL pin I DACH bit X 0dB DAC Lch Figure 57. HPL Mixing Circuit (AIN3 bit = “0”, HPG bit = “0”) RINH2 bit RIN2 pin 0dB MINH bit −20dB MIN pin M HPR pin I DACH bit X 0dB DAC Rch Figure 58. HPR Mixing Circuit (AIN3 bit = “0”, HPG bit = “0”) When AIN3 bit = “1”, DACH, LINH2, RINH2, LINH3, RINH3, MICL3 and MICR3 bits controls each path switch. All pathes mixing gain is 0dB(typ)@HPG bit = “0”. LINH2 bit LIN2 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINH3 bit M 0dB MIC-Amp Lch *These blocks are not available at PLL mode. I HPL pin X DACH bit DAC Lch 0dB Figure 59. HPL Mixing Circuit (AIN3 bit = “1”, HPG bit = “0”) RINH2 bit RIN2 pin 0dB MICR3 bit RIN3 pin RIN1 pin RINH3 bit M 0dB MIC-Amp Rch *These blocks are not available at PLL mode. I HPR pin X DACH bit DAC Rch 0dB Figure 60. HPR Mixing Circuit (AIN3 bit = “1”, HPG bit = “0”) MS0477-E-01 2006/10 - 61 - ASAHI KASEI [AK4644] Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 1-bit Chip address (Fixed to “1”), Read/Write (Fixed to “1”), Register address (MSB first, 6bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“↑”) of CCLK. Address and data are latched on the 16th CCLK rising edge (“↑”) after CSN falling edge(“↓”). Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by PDN pin = “L”. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “1” “1” C1: R/W: A5-A0: D7-D0: Chip Address; Fixed to “1” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 61. Serial Control I/F Timing MS0477-E-01 2006/10 - 62 - ASAHI KASEI [AK4644] (2) I2C-bus Control Mode (I2C pin = “H”) The AK4644 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected to (DVDD+0.3)V or less voltage. (2)-1. WRITE Operations Figure 62 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 68). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits (Figure 63). If the slave address matches that of the AK4644, the AK4644 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 69). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4644. The format is MSB first, and those most significant 2-bits are fixed to zeros (Figure 64). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 65). The AK4644 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 68). The AK4644 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4644 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 70) except for the START and STOP conditions. S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) Data(n) A C K A C K Data(n+1) A C K Data(n+x) A C K P A C K A C K Figure 62. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 1 CAD0 R/W (Those CAD1/0 should match with CAD1/0 pins) Figure 63. The First Byte 0 0 A5 A4 A3 A2 A1 A0 D2 D1 D0 Figure 64. The Second Byte D7 D6 D5 D4 D3 Figure 65. Byte Structure after the second byte MS0477-E-01 2006/10 - 63 - ASAHI KASEI [AK4644] (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4644. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to generating a stop condition, the address counter will “roll over” to 00H and the data of 00H will be read out. The AK4644 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. (2)-2-1. CURRENT ADDRESS READ The AK4644 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4644 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4644 ceases transmission. S T A R T SDA S T O P R/W="1" Slave S Address Data(n) A C K Data(n+1) Data(n+2) A C K A C K Data(n+x) A C K P A C K A C K Figure 66. CURRENT ADDRESS READ (2)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4644 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4644 ceases transmission. S T A R T SDA S T A R T R/W="0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W="1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 67. RANDOM ADDRESS READ MS0477-E-01 2006/10 - 64 - ASAHI KASEI [AK4644] SDA SCL S P start condition stop condition Figure 68. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 69. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 70. Bit Transfer on the I2C-Bus MS0477-E-01 2006/10 - 65 - ASAHI KASEI [AK4644] Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Power Management 4 Mode Control 5 Lineout Mixing Select HP Mixing Select Reserved D7 0 0 0 LOVL PLL3 PS1 DVTM 0 REF7 IVL7 DVL7 RGAIN1 IVR7 DVR7 0 0 INR1 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 0 0 0 0 0 D6 PMVCM HPMTN 0 LOPS PLL2 PS0 WTM2 0 REF6 IVL6 DVL6 LMTH1 IVR6 DVR6 LOOP 0 INL1 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 0 0 0 0 0 D5 PMMIN PMHPL 0 PLL1 FS3 ZTM1 ALC REF5 IVL5 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 D4 0 PMHPR DACL 0 PLL0 MSBS ZTM0 ZELMN REF4 IVL4 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 D3 PMLO M/S 0 0 BCKO BCKP WTM1 LMAT1 REF3 IVL3 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 D2 PMDAC 0 PMMP MINL 0 FS2 WTM0 LMAT0 REF2 IVL2 DVL2 0 IVR2 DVR2 BST0 HPM INR0 FIL3 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 D1 0 MCKO 0 0 DIF1 FS1 RFST1 RGAIN0 REF1 IVL1 DVL1 VBAT IVR1 DVR1 DEM1 MINH INL0 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL0 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL MICR3 0 0 0 MICL3 0 0 0 0 RINR3 RINH3 0 MIX LINL3 LINH3 0 AIN3 RINR2 RINH2 0 RCV LINL2 LINH2 0 MGAIN1 D0 PMADL PMPLL MGAIN0 Note 40. PDN pin = “L” resets the registers to their default values. Note 41. Unused bits must contain a “0” value. MS0477-E-01 2006/10 - 66 - ASAHI KASEI [AK4644] Register Definitions Addr 00H Register Name Power Management 1 Default D7 0 0 D6 PMVCM 0 D5 PMMIN 0 D4 0 0 D3 PMLO 0 D2 PMDAC 0 D1 0 0 D0 PMADL 0 PMADL: MIC-Amp Lch and ADC Lch Power Management 0: Power-down (Default) 1: Power-up When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms @44.1kHz) starts. After initializing, digital data of the ADC is output. PMDAC: DAC Power Management 0: Power-down (Default) 1: Power-up PMLO: Stereo Line Out Power Management 0: Power-down (Default) 1: Power-up PMMIN: MIN Input Power Management 0: Power-down (Default) 1: Power-up PMMIN or PMAINL3 bit should be set to “1” for playback. PMVCM: VCOM Power Management 0: Power-down (Default) 1: Power-up When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only when all power management bits of 00H, 01H, 02H, 10H, 20H and MCKO bits are “0”. Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value. When all power management bits are “0” in the 00H, 01H, 02H, 10H and 20H addresses and MCKO bit is “0”, all blocks are powered-down. The register values remain unchanged. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0477-E-01 2006/10 - 67 - ASAHI KASEI Addr 01H Register Name Power Management 2 Default [AK4644] D7 0 0 D6 HPMTN 0 D5 PMHPL 0 D4 PMHPR 0 D3 M/S 0 D2 0 0 D1 MCKO 0 D0 PMPLL 0 PMPLL: PLL Power Management 0: EXT Mode and Power-Down (Default) 1: PLL Mode and Power-up MCKO: Master Clock Output Enable 0: Disable: MCKO pin = “L” (Default) 1: Enable: Output frequency is selected by PS1-0 bits. M/S: Master / Slave Mode Select 0: Slave Mode (Default) 1: Master Mode PMHPR: Headphone-Amp Rch Power Management 0: Power-down (Default) 1: Power-up PMHPL: Headphone-Amp Lch Power Management 0: Power-down (Default) 1: Power-up HPMTN: Headphone-Amp Mute Control 0: Mute (Default) 1: Normal operation MS0477-E-01 2006/10 - 68 - ASAHI KASEI Addr 02H Register Name Signal Select 1 Default [AK4644] D7 0 0 D6 0 0 D5 0 0 D4 DACL 0 D3 0 0 D2 PMMP 0 D1 0 0 D0 MGAIN0 1 MGAIN1-0: MIC-Amp Gain Control (See Table 23) MGAIN1 bit is D5 bit of 03H. PMMP: MPWR pin Power Management 0: Power-down: Hi-Z (Default) 1: Power-up DACL: Switch Control from DAC to Stereo Line Output or Receiver Output 0: OFF (Default) 1: ON When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS. MS0477-E-01 2006/10 - 69 - ASAHI KASEI Addr 03H Register Name Signal Select 2 Default [AK4644] D7 LOVL 0 D6 LOPS 0 D5 MGAIN1 0 D4 0 0 D3 0 0 D2 MINL 0 D1 0 0 D0 0 0 MINL: Switch Control from MIN pin to Stereo Line Output or Receiver Output 0: OFF (Default) 1: ON When PMLO bit is “1”, MINL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS. MGAIN1: MIC-Amp Gain Control (See Table 23) LOPS: Stereo Line Output Power-Save Mode 0: Normal Operation (Default) 1: Power-Save Mode LOVL: Stereo Line Output / Receiver Output Gain Select (See Table 48, Table 49) 0: 0dB/+6dB (Default) 1: +2dB/+8dB Addr 04H Register Name Mode Control 1 Default D7 PLL3 0 D6 PLL2 0 D5 PLL1 0 D4 PLL0 0 D3 BCKO 0 D2 0 0 D1 DIF1 1 D0 DIF0 0 D3 BCKP 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 DIF1-0: Audio Interface Format (See Table 17) Default: “10” (Left jutified) BCKO: BICK Output Frequency Select at Master Mode (See Table 11) PLL3-0: PLL Reference Clock Select (See Table 5) Default: “0000”(LRCK pin) Addr 05H Register Name Mode Control 2 Default D7 PS1 0 D6 PS0 0 D5 FS3 0 D4 MSBS 0 FS3-0: Sampling Frequency Select (See Table 6 and Table 7) and MCKI Frequency Select (See Table 12.) FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. BCKP: BICK Polarity at DSP Mode (See Table 18) “0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (Default) “1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”). MSBS: LRCK Polarity at DSP Mode (See Table 18) “0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (Default) “1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change. PS1-0: MCKO Output Frequency Select (See Table 10) Default: “00”(256fs) MS0477-E-01 2006/10 - 70 - ASAHI KASEI Addr 06H Register Name Timer Select Default [AK4644] D7 DVTM 0 D6 WTM2 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 D1 RFST1 0 D0 RFST0 0 D1 0 D0 LMTH0 0 D1 REF1 0 D0 REF0 1 RFST1-0: ALC First recovery Speed (See Table 34) Default: “00”(4times) WTM2-0: ALC Recovery Waiting Period (See Table 31.) Default: “000” (128/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (See Table 30.) Default: “00” (128/fs) DVTM: Digital Volume Transition Time Setting (See Table 40.) 0: 1061/fs (Default) 1: 256/fs This is the transition time between DVL/R7-0 bits = 00H and FFH. Addr 07H Register Name ALC Mode Control 1 Default D7 0 0 D6 0 0 D5 ALC 0 D4 ZELMN 0 D3 LMAT1 0 D2 LMAT0 0 RGAIN0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (See Table 28.) Default: “00” LMTH1 bit is D6 bit of 0BH. RGAIN1-0: ALC Recovery GAIN Step (See Table 32.) Default: “00” RGAIN1 bit is D7 bit of 0BH. LMAT1-0: ALC Limiter ATT Step (See Table 29.) Default: “00” ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (Default) 1: Disable ALC: ALC Enable 0: ALC Disable (Default) 1: ALC Enable Addr 08H Register Name ALC Mode Control 2 Default D7 REF7 1 D6 REF6 1 D5 REF5 1 D4 REF4 0 D3 REF3 0 D2 REF2 0 REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (See Table 33.) Default: “E1H” (+30.0dB) MS0477-E-01 2006/10 - 71 - ASAHI KASEI Addr 09H 0CH Register Name Lch Input Volume Control Rch Input Volume Control Default [AK4644] D7 IVL7 IVR7 1 D6 IVL6 IVR6 1 D5 IVL5 IVR5 1 D4 IVL4 IVR4 0 D3 IVL3 IVR3 0 D2 IVL2 IVR2 0 D1 IVL1 IVR1 0 D0 IVL0 IVR0 1 IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (See Table 36.) Default: “E1H” (+30.0dB) Addr 0AH 0DH Register Name Lch Digital Volume Control Rch Digital Volume Control Default D7 DVL7 DVR7 0 D6 DVL6 DVR6 0 D5 DVL5 DVR5 0 D4 DVL4 DVR4 1 D3 DVL3 DVR3 1 D2 DVL2 DVR2 0 D1 DVL1 DVR1 0 D0 DVL0 DVR0 0 D4 0 0 D3 0 0 D2 0 0 D1 VBAT 0 D0 0 0 D2 BST0 0 D1 DEM1 0 D0 DEM0 1 DVL7-0, DVR7-0: Output Digital Volume (See Table 39.) Default: “18H” (0dB) Addr 0BH Register Name ALC Mode Control 3 Default D7 RGAIN1 0 D6 LMTH1 0 D5 0 0 VBAT: HP-Amp Common Voltage (See Table 53.) 0: 0.5 x HVDD (Default) 1: 0.64 x AVDD LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (See Table 28.) RGAIN1: ALC Recovery GAIN Step (See Table 32.) Addr 0EH Register Name Mode Control 3 Default D7 0 0 D6 LOOP 0 D5 SMUTE 0 D4 DVOLC 1 D3 BST1 0 DEM1-0: De-emphasis Frequency Select (See Table 37) Default: “01” (OFF) BST1-0: Bass Boost Function Select (See Table 38) Default: “00” (OFF) DVOLC: Output Digital Volume Control Mode Select 0: Independent 1: Dependent (Default) When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume level, while register values of DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = “0”, DVL7-0 bits control Lch level and DVR7-0 bits control Rch level, respectively. SMUTE: Soft Mute Control 0: Normal Operation (Default) 1: DAC outputs soft-muted LOOP: Digital Loopback Mode 0: SDTI → DAC (Default) 1: SDTO → DAC MS0477-E-01 2006/10 - 72 - ASAHI KASEI Addr 0FH Register Name Mode Control 4 Default [AK4644] D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 IVOLC 1 D2 HPM 0 D1 MINH 0 D0 DACH 0 DACH: Switch Control from DAC to Headphone-Amp 0: OFF (Default) 1: ON MINH: Switch Control from MIN pin to Headphone-Amp 0: OFF (Default) 1: ON HPM: Headphone-Amp Mono Output Select 0: Stereo (Default) 1: Mono When the HPM bit = “1”, DAC output signal is output to Lch and Rch of the Headphone-Amp as (L+R)/2. IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (Default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively. MS0477-E-01 2006/10 - 73 - ASAHI KASEI Addr 10H Register Name Power Management 3 Default [AK4644] D7 INR1 0 D6 INL1 0 D5 HPG 0 D4 MDIF2 0 D3 MDIF1 0 D2 INR0 0 D1 INL0 0 D0 PMADR 0 PMADR: MIC-Amp Lch and ADC Rch Power Management 0: Power-down (Default) 1: Power-up INL1-0: ADC Lch Input Source Select Default: 00 (LIN1 pin) INR1-0: ADC Rch Input Source Select Default: 00 (RIN1 pin) MDIF1: Single-ended / Full-differential Input Select 1 0: Single-ended input (LIN1/RIN1 pins: Default) 1: Full-differential input (IN1+/IN1− pins) MDIF1 bit selects the input type of pins #32 and #31. MDIF2: Single-ended / Full-differential Input Select 2 0: Single-ended input (LIN2/RIN2 pins: Default) 1: Full-differential input (IN2+/IN2− pins) MDIF2 bit selects the input type of pins #30 and #29. HPG: Headphone-Amp Gain Select (See Table 51.) 0: 0dB (Default) 1: +3.6dB MS0477-E-01 2006/10 - 74 - ASAHI KASEI Addr 11H Register Name Digital Filter Select Default [AK4644] D7 GN1 0 D6 GN0 0 D5 0 0 D4 FIL1 0 D3 EQ 0 D2 FIL3 0 D1 0 0 D0 0 0 GN1-0: Gain Select at GAIN block (See Table 26.) Default: “00” FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (Default) 1: Enable When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block is OFF (MUTE). EQ: EQ (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (Default) 1: Enable When EQ bit is “1”, the settings of EQA15-0, EQB13-0 and EQC15-0 bits are enabled. When EQ bit is “0”, EQ block is through (0dB). FIL1: FIL1 (Wind-noise Reduction Filter) Coefficient Setting Enable 0: Disable (Default) 1: Enable When FIL1 bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When FIL1 bit is “0”, FIL1 block is through (0dB). MS0477-E-01 2006/10 - 75 - ASAHI KASEI Addr 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Default [AK4644] D7 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 0 D6 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 0 D5 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 0 D4 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 0 D3 F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 0 D2 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 0 D1 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 D0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 0 F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3AS: FIL3 (Stereo Separation Emphasis Filter) Select 0: HPF (Default) 1: LPF EQA15-0, EQB13-0, EQC15-C0: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1) Default: “0000H” F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: “0000H” F1AS: FIL1 (Wind-noise Reduction Filter) Select 0: HPF (Default) 1: LPF MS0477-E-01 2006/10 - 76 - ASAHI KASEI Addr 20H Register Name Power Management 4 Default [AK4644] D7 0 0 D6 0 0 D5 D4 PMAINR3 PMAINL3 0 0 D3 D2 PMAINR2 PMAINL2 0 0 D1 D0 PMMICR PMMICL 0 0 D1 AIN3 0 D0 RCV 0 PMMICL: MIC-Amp Lch Power Management 0: Power down (Default) 1: Power up PMMICR: MIC-Amp Rch Power Management 0: Power down (Default) 1: Power up PMAINL2: LIN2 Mixing Circuit Power Management 0: Power down (Default) 1: Power up PMAINR2: RIN2 Mixing Circuit Power Management 0: Power down (Default) 1: Power up PMAINL3: LIN3 Mixing Circuit Power Management 0: Power down (Default) 1: Power up PMMIN or PMAINL3 bit should be set to “1” for playback. PMAINR3: RIN3 Mixing Circuit Power Management 0: Power down (Default) 1: Power up Addr 21H Register Name Mode Control 5 Default D7 0 0 D6 0 0 D5 MICR3 0 D4 MICL3 0 D3 0 0 D2 MIX 0 RCV: Receiver Select 0: Stereo Line Output (LOUT/ROUT pins) (Default) 1: Mono Receiver Output (RCP/RCN pins) AIN3: Analog Mixing Select 0: Mono Input (MIN pin) (Default) 1: Stereo Input (LIN3/RIN3 pins): PLL is not available. MIX: Mono Recording 0: Stereo 1: Mono: (L+R)/2 MICL3: Switch Control from MIC-Amp Lch to Analog Output 0: LIN3 input signal is selected. (Default) 1: MIC-Amp Lch output signal is selected. MICR3: Switch Control from MIC-Amp Rch to Analog Output 0: RIN3 input signal is selected. (Default) 1: MIC-Amp Rch output signal is selected. MS0477-E-01 2006/10 - 77 - ASAHI KASEI Addr 22H Register Name Lineout Mixing Select Default [AK4644] D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 RINR3 0 D2 LINL3 0 D1 RINR2 0 D0 LINL2 0 D2 LINH3 0 D1 RINH2 0 D0 LINH2 0 LINL2: Switch Control from LIN2 pin to Stereo Line Output (without MIC-Amp) 0: OFF (Default) 1: ON RINR2: Switch Control from RIN2 pin to Stereo Line Output (without MIC-Amp) 0: OFF (Default) 1: ON LINL3: Switch Control from LIN3 pin (or MIC-Amp Lch) to Stereo Line Output 0: OFF (Default) 1: ON RINR3: Switch Control from RIN3 pin (or MIC-Amp Rch) to Stereo Line Output 0: OFF (Default) 1: ON Addr 23H Register Name HP Mixing Select Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 RINH3 0 LINH2: Switch Control from LIN2 pin to Headphone Output (without MIC-Amp) 0: OFF (Default) 1: ON RINH2: Switch Control from RIN2 pin to Headphone Output (without MIC-Amp) 0: OFF (Default) 1: ON LINH3: Switch Control from LIN3 pin (or MIC-Amp Lch) to Headphone Output 0: OFF (Default) 1: ON RINH3: Switch Control from RIN3 pin (or MIC-Amp Rch) to Headphone Output 0: OFF (Default) 1: ON MS0477-E-01 2006/10 - 78 - ASAHI KASEI [AK4644] SYSTEM DESIGN Figure 71, Figure 72 and Figure 73 shows the system connection diagram for the AK4644. An evaluation board [AKD4644] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Headphone Line Out 1u 200 1u Mono In External MIC 10 47u 22 21 20 19 18 17 HVSS HVDD TEST2 TEST1 MCKO MCKI 0.1u 23 HPR 0.22u 24 10 HPL 0.22u 20k 20k 10 1u 200 6.8 47u 10u 6.8 Power Supply 2.6 ∼ 3.6V 25 MUTET DVSS 16 26 ROUT DVDD 15 27 LOUT BICK 14 13 0.1u DSP 28 MIN AK4644EN LRCK 29 RIN2 Top View SDTO 12 30 LIN2 SDTI 11 31 LIN1 CDTI 10 32 RIN1 CCLK 9 I2C PDN CSN 6 7 8 µP Rp AVDD VCOC 4 5 AVSS 3 0.1u VCOM 2.2u 0.1u 2 MPWR 1 2.2k 2.2k 2.2k 2.2k Internal MIC Cp Analog Ground Digital Ground Notes: - AVSS, DVSS and HVSS of the AK4644 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK4644 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK4644 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 5. - When the AK4644 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4644. Figure 71. Typical Connection Diagram (AIN3 bit = “0”, MIC Input) MS0477-E-01 2006/10 - 79 - ASAHI KASEI [AK4644] Headphone Mono In 200 1u 200 1u 10 47u 23 22 21 20 19 18 17 HPR HVSS HVDD TEST2 TEST1 MCKO MCKI 0.1u 24 0.22u HPL 0.22u 10 20k 20k 10 1u Line Out 6.8 47u 10u 6.8 Power Supply 2.6 ∼ 3.6V 25 MUTET DVSS 16 26 ROUT DVDD 15 27 LOUT BICK 14 0.1u DSP 28 MIN AK4644EN LRCK 13 29 RIN2 Top View SDTO 12 30 LIN2 SDTI 11 31 LIN1 CDTI 10 32 RIN1 CCLK 9 I2C PDN CSN 6 7 8 µP Rp AVDD VCOC 4 5 AVSS 3 0.1u VCOM 2 2.2u 0.1u 1 MPWR Line In Cp Analog Ground Digital Ground Notes: - AVSS, DVSS and HVSS of the AK4644 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK4644 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK4644 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 5. - When the AK4644 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4644. Figure 72. Typical Connection Diagram (AIN3 bit = “0”, Line Input) MS0477-E-01 2006/10 - 80 - ASAHI KASEI [AK4644] Headphone 22 21 20 19 18 17 HVSS HVDD TEST2 TEST1 MCKO MCKI 0.1u 23 HPR 0.22u 24 0.22u 10 HPL 10 1u 10 47u 6.8 47u 10u 6.8 Power Supply 2.6 ∼ 3.6V 25 MUTET DVSS 16 26 RCN DVDD 15 27 RCP BICK 14 0.1u Receiver 0.1u µP 2.2u 0.1u 1 CSN 9 PDN 10 CCLK 8 CDTI 32 RIN1 7 31 LIN1 I2C 11 6 SDTI AVDD 30 LIN2 RIN3 12 5 SDTO 4 Top View AVSS 29 RIN2 3 13 VCOM LRCK 2 AK4644EN MPWR Line In DSP 28 LIN3 Analog Ground Digital Ground Notes: - AVSS, DVSS and HVSS of the AK4644 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When AIN3 bit = “1”, PLL is not available. Figure 73. Typical Connection Diagram (AIN3 bit = “1”: PLL is not available, RCV bit = “1”, Line Input) MS0477-E-01 2006/10 - 81 - ASAHI KASEI [AK4644] 1. Grounding and Power Supply Decoupling The AK4644 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and HVDD are usually supplied from the system’s analog supply. If AVDD, DVDD and HVDD are supplied separately, the power-up sequence is not critical. AVSS, DVSS and HVSS of the AK4644 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4644 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4644. 3. Analog Inputs The Mic, Line and MIN inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp(typ) @MGAIN1-0 bits = “01”, 0.03 x AVDD Vpp(typ) @MGAIN1-0 bits = “10”, 0.015 x AVDD Vpp(typ) @MGAIN1-0 bits = “11” or 0.6 x AVDD Vpp(typ) @MGAIN1-0 bits = “00” for the Mic/Line input and 0.6 x AVDD Vpp (typ) for the MIN input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4645 can accept input voltages from AVSS to AVDD. 4. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Stereo Line Output and Receiver Output are centered at 0.45 x AVDD. The Headphone-Amp output is centered at HVDD/2. MS0477-E-01 2006/10 - 82 - ASAHI KASEI [AK4644] CONTROL SEQUENCE Clock Set up When ADC or DAC is powered-up, the clocks must be supplied. 1. PLL Master Mode. Example: Power Supply Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (4) (1) Power Supply & PDN pin = “L” Æ “H” MCKO bit (Addr:01H, D1) PMPLL bit (2)Addr:01H, Data:08H Addr:04H, Data:4AH Addr:05H, Data:27H (Addr:01H, D0) (5) MCKI pin Input M/S bit (3)Addr:00H, Data:40H (Addr:01H, D3) 40msec(max) (6) BICK pin LRCK pin Output (4)Addr:01H, Data:0BH Output MCKO, BICK and LRCK output 40msec(max) (8) MCKO pin (7) Figure 74. Clock Set Up Sequence (1) <Example> (1) After Power Up, PDN pin = “L” Æ “H” “L” time of 150ns or more is needed to reset the AK4644. (2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period. (3) Power UpVCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered-up before the other block operates. (4) In case of using MCKO output: MCKO bit = “1” In case of not using MCKO output: MCKO bit = “0” (5) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. (6) The AK4644 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation starts. (7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”. (8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”. MS0477-E-01 2006/10 - 83 - ASAHI KASEI [AK4644] 2. PLL Slave Mode (LRCK or BICK pin) Example: Power Supply Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 44.1kHz (1) PDN pin (2) 4fs (1)ofPower Supply & PDN pin = “L” Æ “H” (3) PMVCM bit (Addr:00H, D6) PMPLL bit (2) Addr:04H, Data:32H Addr:05H, Data:27H (Addr:01H, D0) LRCK pin BICK pin Input (3) Addr:00H, Data:40H (4) Internal Clock (5) (4) Addr:01H, Data:01H Figure 75. Clock Set Up Sequence (2) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time of 150ns or more is needed to reset the AK4644. (2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is supplied. PLL lock time is 160ms(max) when LRCK is a PLL reference clock. And PLL lock time is 2ms(max) when BICK is a PLL reference clock. (5) Normal operation stats after that the PLL is locked. MS0477-E-01 2006/10 - 84 - ASAHI KASEI [AK4644] 3. PLL Slave Mode (MCKI pin) Example: Audio I/F Format: MSB justified (ADC & DAC) Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz Power Supply (1) Power Supply & PDN pin = “L” Æ “H” (1) PDN pin (2) (3) (2)Addr:04H, Data:4AH Addr:05H, Data:27H PMVCM bit (Addr:00H, D6) (4) MCKO bit (Addr:01H, D1) (3)Addr:00H, Data:40H PMPLL bit (Addr:01H, D0) (5) MCKI pin (4)Addr:01H, Data:03H Input 40msec(max) (6) MCKO pin MCKO output start Output (7) (8) BICK pin LRCK pin Input BICK and LRCK input start Figure 76. Clock Set Up Sequence (3) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time of 150ns or more is needed to reset the AK4644. (2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Enable MCKO output: MCKO bit = “1” (5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied. PLL lock time is 40ms(max). (6) The normal clock is output from MCKO after PLL is locked. (7) The invalid frequency is output from MCKO during this period. (8) BICK and LRCK clocks should be synchronized with MCKO clock. MS0477-E-01 2006/10 - 85 - ASAHI KASEI [AK4644] 4. EXT Slave Mode Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable Power Supply (1) Power Supply & PDN pin = “L” Æ “H” (1) PDN pin (2) (2) Addr:04H, Data:02H Addr:05H, Data:00H (3) PMVCM bit (Addr:00H, D6) (4) MCKI pin Input (3) Addr:00H, Data:40H (4) LRCK pin BICK pin Input MCKI, BICK and LRCK input Figure 77. Clock Set Up Sequence (4) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time of 150ns or more is needed to reset the AK4644. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Normal operation starts after the MCKI, LRCK and BICK are supplied. MS0477-E-01 2006/10 - 86 - ASAHI KASEI [AK4644] 5. EXT Master Mode Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable (1) Power Supply & PDN pin = “L” Æ “H” Power Supply (1) PDN pin (2) MCKI input (4) PMVCM bit (Addr:00H, D6) (3) Addr:04H, Data:02H Addr:05H, Data:00H Addr:01H, Data:08H (2) MCKI pin Input (3) M/S bit BICK and LRCK output (Addr:01H, D3) LRCK pin BICK pin Output (4) Addr:00H, Data:40H Figure 78. Clock Set Up Sequence (5) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time of 150ns or more is needed to reset the AK4644. (2) MCKI should be input. (3) After DIF1-0 and FS1-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output. (4) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. MS0477-E-01 2006/10 - 87 - ASAHI KASEI [AK4644] MIC Input Recording (Stereo) Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 PLL Master Mode Audio I/F Format:MSB justified (ADC & DAC) Sampling Frequency:44.1kHz Pre MIC AMP:+20dB MIC Power On ALC setting:Refer to Table 35 ALC bit=“1” 1,111 (1) MIC Control (Addr:02H, D2-0) ALC Control 1 (Addr:06H) ALC Control 2 (Addr:08H) (1) Addr:05H, Data:27H 001 101 (2) Addr:02H, Data:05H (2) 00H 3CH (3) Addr:06H, Data:3CH E1H (4) Addr:08H, Data:E1H (3) E1H (4) (5) Addr:0BH, Data:00H ALC Control 3 (Addr:0BH) 00H 00H (6) Addr:07H, Data:21H (5) ALC Control 4 (Addr:07H) 07H 21H 01H (6) ALC State (9) ALC Disable ALC Enable (7) Addr:00H, Data:41H Addr:10H, Data:01H ALC Disable Recording PMADL/R bit (Addr:00H&10H, D0) 1059 / fs (8) (7) ADC Internal State Power Down (8) Addr:00H, Data:40H Addr:10H, Data:00H Initialize Normal State Power Down (9) Addr:07H, Data:01H Figure 79. MIC Input Recording Sequence <Example> This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to “Figure 36. Registers set-up sequence at ALC operation” At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK4644 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 02H) (3) Set up Timer Select for ALC (Addr: 06H) (4) Set up REF value for ALC (Addr: 08H) (5) Set up LMTH1 and RGAIN1 bits (Addr: 0BH) (6) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H) (7) Power Up MIC and ADC: PMADL = PMADR bits = “0” → “1” The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz. After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL default value (+30dB). The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog input pin going to the common voltage and the time constant of the offset cancel digital HPF. This time can be shorter by using the following sequence: At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to power-up the ADC should be longer than 4 times of the time constant that is determined by the AC coupling capacitor at analog input pin and the internal input resistance 60k(typ). (8) Power Down MIC and ADC: PMADL = PMADR bits = “1” → “0” When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed when the sampling frequency is changed, it should be done after the AK4644 goes to the manual mode (ALC bit = “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADL or PMADR bit is changed to “1”. (9) ALC Disable: ALC bit = “1” → “0” MS0477-E-01 2006/10 - 88 - ASAHI KASEI [AK4644] Headphone-amp Output Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 (1) DACH bit (2) (Addr:0FH, D0) BST1-0 bits (Addr:0EH, D3-2) IVL/R7-0 bits (Addr:09H&0CH, D7-0) PLL, Master Mode Audio I/F Format :MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: −8dB Bass Boost Level :Middle 1,111 (13) 00 10 00 (3) (12) E1H 91H (1) Addr:05H, Data:27H (2) Addr:0FH, Data:09H (3) Addr:0EH, Data:19H (4) Addr:09H&0CH, Data:91H (4) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (5) Addr:0AH&0DH, Data:28H 18H 28H (6) Addr:00H, Data:64H (5) PMDAC bit (7) Addr:01H, Data:39H (Addr:00H, D2) (6) (11) (8) Addr:01H, Data:79H PMMIN bit (Addr:00H, D5) PMHPL/R bits Playback (7) (10) (9) Addr:01H, Data:39H (Addr:01H, D5-4) (10) Addr:01H, Data:09H HPMTN bit (8) (9) (11) Addr:00H, Data:40H (Addr:01H, D6) HPL/R pins Normal Output (12) Addr:0EH, Data:11H (13) Addr:0FH, Data:08H Figure 80. Headphone-Amp Output Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4644 is PLL mode, DAC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1” (3) Set up the low frequency boost level (BST1-0 bits) (4) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB). (5) Set up the output digital volume (Addr: 0AH and 0DH) When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits. (7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1” Output voltage of headphone-amp is still HVSS. (8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1” The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V and the capacitor value is 1.0µF, the time constant is τr = 100ms(typ), 250ms(max). (9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0” The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V and the capacitor value is 1.0µF, the time constant is τ f = 100ms(typ), 250ms(max). If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to GND, the pop noise occurs. It takes twice of τf that the common voltage goes to GND. (10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0” (11) Power down DAC and MIN-Amp: PMDAC = PMMIN bits = “1” → “0” (12) Off the bass boost: BST1-0 bits = “00” (13) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0” MS0477-E-01 2006/10 - 89 - ASAHI KASEI [AK4644] Stereo Line Output Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 PLL, Master Mode Audio I/F Format :MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: −8dB LOVL=MINL bits = “0” 1,111 (1) (1) Addr:05H, Data:27H (10) DACL bit (2) (2) Addr:02H, Data:10H (Addr:02H, D4) IVL/R7-0 bits (Addr:09H&0CH, D7-0) E1H (3) Addr:09H&0CH, Data:91H 91H (3) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (4) Addr:0AH&0DH, Data:28H 18H 28H (5) Addr:03H, Data:40H (4) LOPS bit (6) Addr:00H, Data:6CH (Addr:03H, D6) (7) (5) (8) (11) PMDAC bit (Addr:00H, D2) Playback PMMIN bit (8) Addr:03H, Data:40H (Addr:00H, D5) (6) (9) (9) Addr:00H, Data:40H PMLO bit (Addr:00H, D3) LOUT pin ROUT pin (7) Addr:03H, Data:00H >300 ms (10) Addr:02H, Data:00H >300 ms Normal Output (11) Addr:03H, Data:00H Figure 81. Stereo Lineout Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up the sampling frequency (FS3-0 bits). When the AK4644 is PLL mode, DAC and Stereo Line-Amp should be powered-up in consideration of PLL lock time after the sampling frequency is changed. (2) Set up the path of “DAC Æ Stereo Line Amp”: DACL bit = “0” Æ “1” (3) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB). (4) Set up the output digital volume (Addr: 0AH and 0DH) When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0” Æ “1” (6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits. LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time is 300ms(max) at C=1µF and AVDD=3.3V. (7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0” LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation by setting LOPS bit to “0”. (8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1” (9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “1” → “0” LOUT and ROUT pins fall down to AVSS. Fall time is 300ms(max) at C=1µF and AVDD=3.3V. (10) Disable the path of “DAC Æ Stereo Line-Amp”: DACL bit = “1” Æ “0” (11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0” LOPS bit should be set to “0” after LOUT and ROUT pins fall down. MS0477-E-01 2006/10 - 90 - ASAHI KASEI [AK4644] Receiver-amp Output Example: PLL Master Mode Audio I/F Format: MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: −8dB LOVL = MINL bits = “0” (1) Addr:05H, Data:27H FS3-0 bits (Addr:05H, D5&D2-0) 0,000 1,111 (2) Addr:21H, Data:01H (1) RCV bit (3) Addr:02H, Data:10H (2) (Addr:21H, D0) (10) DACL bit (4) Addr:03H, Data:40H (Addr:02H, D4) (3) IVL/R7-0 bits (Addr:09H&0CH, D7-0) E1H (5) Addr:09H & 0CH, Data:91H 91H (5) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) 18H (6) Addr:0AH & 0DH, Data:28H 28H (6) (11) (7) Addr:00H, Data:6CH PMDAC bit (Addr:00H, D2) PMMIN bit (8) Addr:03H, Data:00H (Addr:00H, D5) (7) PMLO bit Playback (Addr:00H, D3) LOPS bit (8) (4) (9) Addr:03H, Data:40H (Addr:03H, D6) (9) RCP pin RCN pin Hi-Z Hi-Z Normal Output (10) Addr:02H, Data:00H Hi-Z VCOM Normal Output VCOM Hi-Z (11) Addr:00H, Data:40H Figure 82. Receiver-Amp Output Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4644 is PLL mode, DAC and Receiver-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC Æ RCV-Amp and Power-save mode”: DACL=LOPS bit = “0” Æ “1” (3) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB). (4) Set up the output digital volume (Addr: 0AH and 0DH). When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (5) Power Up of DAC, MIN-Amp and Receiver-Amp: PMDAC = PMMIN = PMLO bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2’s compliment, “0”. The DAC output reflects the digital input data after the initialization cycle (1059/fs=24ms@fs=44.1kHz) is complete. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. (6) Exit the power-save-mode of Receiver-Amp: LOPS bit = “1” → “0” (7) Enter the power-save-mode of Receiver-Amp: LOPS bit = “0” → “1” (8) Disable the path of “DAC Æ RCV-Amp”: DACL bit = “1” Æ “0” (9) Power Down DAC, MIN-Amp and Receiver-Amp: PMDAC = PMMIN = PMLO bits = “1” → “0” MS0477-E-01 2006/10 - 91 - ASAHI KASEI [AK4644] Stop of Clock Master clock can be stopped when ADC and DAC are not used. 1. PLL Master Mode Example: Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz (1) PMPLL bit (Addr:01H, D0) (2) MCKO bit "1" or "0" (1) (2) Addr:01H, Data:08H (Addr:01H, D1) (3) External MCKI Input (3) Stop an external MCKI Figure 83. Clock Stopping Sequence (1) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop MCKO clock: MCKO bit = “1” → “0” (3) Stop an external master clock. 2. PLL Slave Mode (LRCK or BICK pin) Example Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs (1) PMPLL bit (Addr:01H, D0) (2) External BICK Input (1) Addr:01H, Data:00H (2) External LRCK Input (2) Stop the external clocks Figure 84. Clock Stopping Sequence (2) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop the external BICK and LRCK clocks 3. PLL Slave (MCKI pin) Example (1) Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: MCKI BICK frequency: 64fs PMPLL bit (Addr:01H, D0) (1) MCKO bit (1) Addr:01H, Data:00H (Addr:01H, D1) (2) External MCKI Input (2) Stop the external clocks Figure 85. Clock Stopping Sequence (3) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” Stop MCKO output: MCKO bit = “1” → “0” (2) Stop the external master clock. MS0477-E-01 2006/10 - 92 - ASAHI KASEI [AK4644] 4. EXT Slave Mode (1) External MCKI Input Example (1) External BICK Input External LRCK Input Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs (1) (1) Stop the external clocks Figure 86. Clock Stopping Sequence (4) <Example> (1) Stop the external MCKI, BICK and LRCK clocks. 5. EXT Master Mode (1) External MCKI Input Example BICK Output "H" or "L" LRCK Output "H" or "L" Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs (1) Stop the external MCKI Figure 87. Clock Stopping Sequence (5) <Example> (1) Stop MCKI clock. BICK and LRCK are fixed to “H” or “L”. Power down Power supply current can be shut down (typ. 10µA) by stopping clocks and setting PMVCM bit = “0” after all blocks except for VCOM are powered-down. Power supply current can be also shut down (typ. 10µA) by stopping clocks and setting PDN pin = “L”. When PDN pin = “L”, the registers are initialized. MS0477-E-01 2006/10 - 93 - ASAHI KASEI [AK4644] PACKAGE 32pin QFN (Unit: mm) 5.00 ± 0.10 0.40 ± 0.10 4.75 ± 0.10 24 17 16 4.75 ± 0.10 B 3.5 5.00 ± 0.10 25 32 1 1 3.5 0.50 +0.07 -0.05 32 C0.42 8 A 0.23 Exposed Pad 9 0.85 ± 0.05 0.10 M AB 0.08 C 0.04 0.01+- 0.01 0.20 C Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0477-E-01 2006/10 - 94 - ASAHI KASEI [AK4644] MARKING AKM AK4644 XXXXX 1 XXXXX : Date code identifier (5 digits) Revision History Date (YY/MM/DD) 06/04/04 06/10/24 Revision 00 01 Reason First Edition Spec change Page Contents 36 Error correct 55 MIC/LINE Input Selector “When full-differential input is used, the signal should not be input to the pins marked by “X” in Table 21.” was added. Table 21 (Handling of MIC/Line Input Pins) was added. Stereo Line Output Control Sequence Power-down mode: PMLO bit = “1” Æ PMLO bit = “0” 63 73 86 87 88 I2C Bus Control Mode “those most significant 3-bits are fixed to zeros” Æ “those most significant 2-bits are fixed to zeros” Register Definitions (Addr=0FH) HPM bit: “When the HPM bit = “1”, (L+R)/2 signals are output to Lch and Rch of the Headphone-Amp. Both PMHPL and PMHPR bits should be “1” when HPM bit is “1”. Æ “When the HPM bit = “1”, DAC output signal is output to Lch and Rch of the Headphone-Amp as (L+R)/2.” Control Sequence (Clock Setup: Ext Slave Mode) MCLK Frequency: 1024fs Æ 256fs Addr=05H: Data=01H Æ 00H Control Sequence (Clock Setup: Ext Master Mode) MCLK Frequency: 1024fs Æ 256fs Addr=05H: Data=01H Æ 00H Control Sequence (Mic Recording) ALC Setting: “Refer to Figure 23” Æ “Refer to Figure 36” MS0477-E-01 2006/10 - 95 - ASAHI KASEI Date (YY/MM/DD) 06/10/24 [AK4644] Revision 01 Reason Error correct Page 89 92 Contents Control Sequence (Headphone Playback) Digital Volume Level: 0dB Æ −8dB Addr=0EH: Data=14H Æ 19H Figure 80: (12) Addr=0EH: Data=00H Æ 11H Control Sequence (Stop of Clock: PLL Master Mode) MCKO bits = “H” or “L” Æ “1” or “0” IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0477-E-01 2006/10 - 96 -