Intersil ISL80101IR08Z-T High performance 1a ldo Datasheet

ISL80101
Features
The ISL80101 ia a low-voltage, high-current, single
output LDO specified for 1A output current. This part
operates from input voltages of 2.2V to 6V and is capable
of providing output voltages of 0.8V to 5V on the
adjustable VOUT versions. Fixed output voltage options
available in 0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5V.
Other custom voltage options available upon request.
• 0.2% initial VOUT Accuracy
For applications that demand in-rush current less than
current limit or a longer delay for a valid VOUT, an
external capacitor on the soft-start pin provides
adjustment. A supply independent ENABLE signal allows
the part to be placed into a low quiescent current
shutdown mode. Sub-micron CMOS process is utilized for
this product family to deliver best in class analog
performance and overall value.
This CMOS LDO will consume significantly lower
quiescent current as a function of load over bipolar LDOs,
which translates into higher efficiency and the ability to
consider packages with smaller footprints. Quiescent
current is modestly compromised to enable leading class
fast load transient response and hence total AC
regulation band for an LDO in this category.
Applications*(see page 14)
• Designed for 2.2V to 6V Input Supply
• Dropout Typically 130mV at 1A
• Fast Load Transient Response
• Rated Output Current Options of 1A
• Adjustable In-Rush Current Limiting
• Fixed and Adjustable VOUT Options Available
• 58dB Typical PSRR
• Output Noise of 100µVRMS between 300Hz to
300kHz
• PG Feature
• 1V Enable Input Threshold
• Short-Circuit Current Protection
• 1A Peak Reverse Current
• Over-Temperature Shutdown
• Any Cap Stable with Minimum 10µF Ceramic
• ±1.8% Guaranteed VOUT Accuracy for Junction
Temperature Range from -40°C to +125°C
• Available in a 10 Ld DFN Package and soon to follow
TO220-5, TO263-5 and SOT223-5
• Pb-Free (RoHS Compliant)
• DSP, FPGA and µP Core Power Supplies
• Noise-Sensitive Instrumentation Systems
• Post Regulation of Switched Mode Power Supplies
• Industrial Systems
• Medical Equipment
• Telecommunications and Networking Equipment
• Servers
• Hard Disk Drives (HD/HDD)
Pin Configuration
ISL80101
(10 LD 3X3 DFN)
TOP VIEW
December 21, 2009
FN6931.0
1
VOUT
1
10 VIN
VOUT
2
9 VIN
SENSE/ADJ
3
8 NC
PG
4
7 ENABLE
GND
5
6 SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL80101
High Performance 1A LDO
ISL80101
Pin Descriptions
PIN
NUMBER
PIN NAME
1, 2
VOUT
3
SENSE/ADJ
4
PG
5
GND
6
SS
7
ENABLE
8
DNC
Do not connect this pin to ground or supply. Leave floating.
9, 10
VIN
Input supply pin.
DESCRIPTION
Output voltage pin.
Remote voltage sense for internally fixed VOUT options. ADJ pin for externally set VOUT.
VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Pin should be grounded
if not used.
GND pin.
External cap controls the rate of the VOUT ramp.
VIN independent chip enable. TTL and CMOS compatible.
Ordering Information
PART NUMBER
(Notes 4, 5)
PART MARKING
VOUT
VOLTAGE
(Note 3)
TEMP RANGE (°C)
PACKAGE
(Pb-Free)
PKG DWG. #
ISL80101IRAJZ
(Note 1)
DZAB
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR08Z
DZBB
0.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR08Z-T
(Note 2)
DZBB
0.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR12Z
DZCB
1.2V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR12Z-T
(Note 2)
DZCB
1.2V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR15Z
DZDB
1.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR15Z-T
(Note 2)
DZDB
1.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR18Z
(Note 1)
DZEB
1.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR25Z
(Note 1)
DZFB
2.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR33Z
DZGB
3.3V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR33Z-T
(Note 2)
DZGB
3.3V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR50Z
DZHB
5.0V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101IR50Z-T
(Note 2)
DZHB
5.0V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
NOTES:
1. Add “-T” or “TK” for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. For other output voltages, contact Intersil Marketing.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL80101. For more information on MSL please
see techbrief TB363.
2
FN6931.0
December 21, 2009
ISL80101
Absolute Maximum Ratings
Thermal Information
VIN relative to GND (Note 6) . . . . . . . . . . . . -0.3V to +6.5V
VOUT relative to GND (Note 6) . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, SENSE/ADJ, SS
Relative to GND (Note 6) . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance . . . . . . . . . . . . . . . . . . .θJA (°C/W)θJC (°C/W)
10 Ld DFN Package (Notes 7, 8) . .
45
4
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
(Notes 9, 10)
Junction Temperature Range (TJ) (Note 9) . -40°C to +125°C
VIN relative to GND . . . . . . . . . . . . . . . . . . . . . 2.2V to 6V
VOUT range . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V
PG, ENABLE, SENSE/ADJ, SS relative to GND . . . . 0V to +6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
9. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage.
Recommended operating conditions define limits where specifications are guaranteed.
10. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current =
lifetime average current.
Electrical Specifications
PARAMETER
Unless otherwise noted, VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C.
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to Applications section of the datasheet and Tech Brief TB379.
Boldface limits apply over the operating temperature range,
-40°C to +125°C.
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 11) TYP (Note 11) UNITS
DC CHARACTERISTICS
DC Ouput Voltage Accuracy
VOUT
VOUT Options: 0.8V, 1.2V, 1.5V and 1.8V
2.2V ≤ VIN < 3.6V; 0A < ILOAD ≤ 1A
-1.8
0.2
1.8
%
-1.8
0.2
1.8
%
491
500
509
mV
1
%
VOUT Options: 2.5V, 3.3V and 5.0V
VOUT + 0.4V ≤ VIN ≤ 6V; 0A < ILOAD < 1A
Feedback Pin
(ADJ Option Only)
VADJ
2.2V ≤VIN ≤ 6V, 0A < ILOAD < 1A
DC Input Line Regulation
ΔVOUT/
ΔVIN
VOUT + 0.5V < VIN < 5V
DC Output Load Regulation
ΔVOUT/
ΔIOUT
0A < ILOAD < 1A, All voltage options
Feedback Input Current
VADJ = 0.5V
Ground Pin Current
IQ
Ground Pin Current in
Shutdown
ISHDN
-1
%
0.01
1
µA
ILOAD = 0A, 2.2V < VIN < 6V
3
5
mA
ILOAD = 1A, 2.2V < VIN < 6V
5
7
mA
ENABLE Pin = 0.2V, VIN = 6V
0.2
12
µA
212
mV
Dropout Voltage (Note 12)
VDO
ILOAD = 1A, VOUT = 2.5V
130
Output Short Circuit Current
(1A Version)
OCP
VOUT = 0V, 2.2V < VIN < 6V
1.75
A
Thermal Shutdown
Temperature
TSD
2.2V < VIN < 6V
160
°C
3
FN6931.0
December 21, 2009
ISL80101
Electrical Specifications
Unless otherwise noted, VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C.
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to Applications section of the datasheet and Tech Brief TB379.
Boldface limits apply over the operating temperature range,
-40°C to +125°C. (Continued)
TEST CONDITIONS
MIN
MAX
(Note 11) TYP (Note 11) UNITS
PARAMETER
SYMBOL
Thermal Shutdown
Hysteresis (Rising Threshold)
TSDn
2.2V < VIN < 6V
30
°C
PSRR
f = 1kHz, ILOAD = 1A; VIN = 2.2V
58
dB
AC CHARACTERISTICS
Input Supply Ripple
Rejection
f = 120Hz, ILOAD = 1A; VIN = 2.2V
ILOAD = 10mA, BW = 300Hz < f < 300kHz
Output Noise Voltage
72
dB
100
µVRMS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
2.2V < VIN < 6V
0.3
0.8
1
V
Hysteresis
(Rising Threshold)
2.2V < VOUT + 0.4V < 6V
10
80
200
mV
Enable Pin Turn-on Delay
COUT = 10µF, ILOAD = 1A
Enable Pin Leakage Current
VIN = 6V, EN = 3V
100
µs
1
µA
ADJUSTABLE INRUSH CURRENT LIMIT CHARACTERISTICS
Current limit adjust
IPD
VIN = 3.5V, EN = 0V, SS = 1V
ICHG
0.5
1
1.3
mA
-3.3
-2
-0.8
µA
75
85
92
%VOUT
PG PIN CHARACTERISTICS
VOUT PG Flag Threshold
VOUT PG Flag Hysteresis
4
PG Flag Low Voltage
VIN = 2.5V, ISINK = 500µA
PG Flag Leakage Current
VIN = 6V, PG = 6V
%
100
mV
1
µA
NOTES:
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
12. Dropout is defined by the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal
value.
4
FN6931.0
December 21, 2009
ISL80101
Typical Application Diagrams
9
2.5V ± 10%
10µF
10
V OUT
VIN
V OUT
VIN
SENSE/ADJ
1
2
3
1.8V ± 1.8%
10µF
100k
10k
ISL80101
7
6
ENABLE
PG
4
SS
(*NOTE 13)
GND
5
FIXED
FIGURE 1. FIXED TYPICAL APPLICATION DIAGRAM
9
2.5V ± 10%
10µF
10
VIN
VOUT
VIN
ISL80101
VOUT
1
2
1.8V ± 1.8%
10µF
2.6k
10k
100k
SE NSE/ADJ
1k
7
6
(*NOTE 13)
ENABLE
PG
4
SS
GND
5
ADJUSTABLE
FIGURE 2. ADJUSTABLE TYPICAL APPLICATION DIAGRAM
NOTE:
13. Used when large bulk capacitance required on VOUT for application.
5
FN6931.0
December 21, 2009
ISL80101
ISL80101 Schematic Block Diagram
VIN
SS
THERMAL
SHUTDOWN
SS
REFERENCE
BIAS
OCL
-
POWER
PMOS
+
VOUT
SENSE
ENABLE
LEVEL
SHIFT
ADJ
PGOOD
+
GND
Application Section
Input Voltage Requirements
Despite other output voltages offered, this family of LDOs
is optimized for a true 2.5V to 1.8V conversion where the
input supply can have a tolerance of as much as ±10%
for conditions noted in the “Electrical Specifications” table
on page 3. Minimum guaranteed input voltage is 2.2V.
However, due to the nature of an LDO, VIN must be some
margin higher than the output voltage plus dropout at
the maximum rated current of the application if active
filtering (PSRR) is expected from VIN to VOUT. The
Dropout spec of this family of LDOs has been generously
specified in order to allow applications to design for a
level of efficiency that can accommodate the smaller
outline package for those applications that cannot
accommodate the profile of the TO220/263.
External Capacitor Requirements
GENERAL GUIDELINE
External capacitors are required for proper operation.
Careful attention must be paid to layout guidelines and
selection of capacitor type and value to ensure optimal
performance.
OUTPUT CAPACITOR
The required minimum output capacitor is 10µF X5R/X7R
to ensure stable operation. Additional capacitors of any
value in Ceramic, POSCAP or Alum/Tantalum Electrolytic
types may be placed in parallel to improve PSRR at
higher frequencies and/or load transient AC output
voltage tolerances. This minimum capacitor must be
connected to VOUT and Ground pins of the LDO with PCB
traces no longer than 0.5cm.
6
INPUT CAPACITOR
The minimum input capacitor required for proper
operation is 10µF having a ceramic dielectric. This
minimum capacitor must be connected to VOUT and
Ground pins of the LDO with PCB traces no longer than
0.5cm.
Thermal Fault Protection
In the event the die temperature exceeds typically
+160°C, then the output of the LDO will shut down until
the die temperature can cool down to typically +130°C.
The level of power combined with the thermal resistance
of the package (+45°C/W for DFN) will determine if the
junction temperature exceeds the thermal shutdown
temperature specified in the “Electrical Specifications”
table on page 3 (see thermal packaging guidelines).
Current Limit Protection
The ISL80101 LDO incorporates protection against
overcurrent due to any short or overload condition
applied to the output pin. The current limit circuit
performs as a constant current source when the output
current exceeds the current limit threshold noted in the
“Electrical Specifications” table on page 3. If the short or
overload condition is removed from VOUT, then the
output returns to normal voltage mode regulation. In the
event of an overload condition on the DFN package the
LDO will begin to cycle on and off due to the die
temperature exceeding thermal fault condition. The
TO220/263 package will tolerate higher levels of power
dissipation on the die which may never thermal cycle if
the heatsink of this larger package can keep the die
temperature below the specified typical thermal
shutdown temperature.
FN6931.0
December 21, 2009
ISL80101
Functional Description
Enable Operation
The Enable turn-on threshold is typically 0.8V with a
hysteresis of 80mV. The Enable pin doesn't have an
internal pull-up or pull-down resistor. As a result, this pin
must not be left floating. This pin must be tied to VIN if it
is not used. A pull-up resistor (typically 1kΩ to 10kΩ) will
be required for applications that use open collector or
open drain outputs to control the Enable pin. The Enable
pin may be connected directly to VIN for applications that
are always on.
Soft-Start Operation
The soft-start circuit controls the rate at which the output
voltage comes up to regulation at power-up or coming
out of a chip disable. A constant current charges an
external soft-start capacitor. The external capacitor
always gets discharged to 0V at start-up of after coming
out of a chip disable. The discharge rate is the RC time
constant of an internal resistance and CSS. The soft-start
function effectively limits the amount of in-rush current
below the programmed current limit during start-up or
an enable sequence to avoid an overcurrent fault
condition. This can be an issue for applications that
require large, external bulk capacitances on VOUT where
high levels of charging current can be seen for a
significant period of time. High in-rush currents can
cause VIN to drop below minimum which could cause
VOUT to shutdown. Equation 3 can be used to calculate
CSS for a desired in-rush current. Where VOUT is the
output voltage, COUT is the total capacitance on the
output and IINRUSH is the desired in-rush current.
( V OUT xC OUT x2μA ) )
C SS = ----------------------------------------------------------I INRUSH x0.5V
(EQ. 1)
The following scope in Figure 3 captures the response for
the soft-start function.The output voltage is set to 1.8V.
FIGURE 4. IN-RUSH CURRENT WITH CSS = 15nF,
COUT = 1000µF, IN-RUSH CURRENT = 0.5A
FIGURE 5. IN-RUSH CURRENT WITH CSS = 33nF,
COUT = 1000µF, IN-RUSH CURRENT = 0.2A
The rise time of the regulator output voltage for a given
CSS value can be calculated using Equation 2.
Also
C SS x0.5V
t RAMP = ---------------------------2μA
(EQ. 2)
Power-Good Operation
The PGOOD circuit monitors VOUT and signals a fault
condition when VOUT is below 85% of the nominal output
voltage. The PGOOD flag is an open-drain NMOS that can
sink 10mA during a fault condition. The PGOOD pin
requires an external pull up resistor which is typically
connected to the VOUT pin. The PGOOD pin should not
be pulled up to a voltage source greater than VIN. During
a fault condition, the PGOOD output is pulled low. The
PGOOD fault can be caused by the current limit fault or
low input voltage. The PGOOD does not function during
thermal shutdown and when the part is disabled.
FIGURE 3. IN-RUSH CURRENT WITH NO CSS,
COUT = 1000µF, IN-RUSH CURRENT = 1.8A
7
FN6931.0
December 21, 2009
ISL80101
Output Voltage Selection
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage. This
voltage is then fed back to the error amplifier. The output
voltage can be programmed to any level between 0.8V
and 5V. An external resistor divider, R1 and R2, is used to
set the output voltage as shown in Equation 3. The
recommended value for R2 is 500Ω to 1kΩ. R1 is then
chosen according to Equation 4:
⎛ R1
⎞
V OUT = 0.5V × ⎜ ------- + 1⎟
R
⎝ 2
⎠
(EQ. 3)
V OUT
R 1 = R 2 × ⎛ ---------------- – 1⎞
⎝ 0.5V
⎠
(EQ. 4)
Power Dissipation
The junction temperature must not exceed the range
specified in the Recommended Operating Conditions. The
power dissipation can be calculated by using Equation 5:
To calculate the maximum ambient operating
temperature, use the junction-to-ambient thermal
resistance (θJA) for the DFN package with Equation 5:
P D ( MAX ) = ( T J ( MAX ) – T A ) ⁄ θ JA
(EQ. 7)
Substitute PD for PD(MAX) and the maximum ambient
operating temperature can be found by solving for TA
using Equation 8:
T A = T JMAX – P D ( MAX ) × θ JA
(EQ. 8)
Heatsinking The DFN Package
The DFN package uses the copper area on the PCB as a
heat-sink. The EPAD of this package must be soldered to
the copper plane (GND plane) for heat sinking. Figure 6
shows a curve for the θJA of the DFN package for
different copper area sizes.
46
(EQ. 5)
The maximum allowed junction temperature, TJ(MAX)
and the maximum expected ambient temperature,
TA(MAX) will determine the maximum allowed junction
temperature rise (ΔTJ) as shown in Equation 6:
(EQ. 6)
ΔT J = T J ( MAX ) – T A ( MAX )
8
44
θJA, C/W
P D = ( V IN – V OUT ) × I OUT + V IN × I GND
42
40
38
36
34
2
4
6
8
10 12 14 16 18 20 22
2
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
24
FIGURE 6. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB
WITH THERMAL VIAS θJA vs EPAD-MOUNT
COPPER LAND AREA ON PCB
FN6931.0
December 21, 2009
ISL80101
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A.
2.0
1.8
1.8
OUTPUT VOLTAGE (V)
ΔVOUT (%)
1.2
0.6
0
-0.6
-1.2
1.6
1.4
1.2
+125°C
1.0
0.8
-40°C
+25°C
0.6
0.4
0.2
-1.8
-50
-25
0
25
50
75
100
125
0
150
0
1
3
2
4
SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
FIGURE 7. OUTPUT VOLTAGE vs TEMPERATURE
5
0.6
GROUND CURRENT (mA)
DVOUT (%)
1.2
+25°C
0
-0.6
-40°C
+125°C
-1.2
0
0.25
0.50
0.75
4
3
2
1
0
1.00
2
FIGURE 9. OUTPUT VOLTAGE vs OUTPUT CURRENT
6
5.0
4.5
GROUND CURRENT (µA)
+125°C
3.00
2.75
-40°C
+25°C
2.50
2.25
2.00
1.75
1.50
0
5
FIGURE 10. GROUND CURRENT vs SUPPLY VOLTAGE
3.50
3.25
4
3
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
GROUND CURRENT (mA)
6
FIGURE 8. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
1.8
-1.8
5
4.0
3.5
3.0
VIN = 6V
2.5
2.0
1.5
1.0
0.5
0.25
0.50
0.75
1.00
OUTPUT CURRENT (A)
FIGURE 11. GROUND CURRENT vs OUTPUT CURRENT
9
0
-40 -25 -10 5
20 35 50 65 80
TEMPERATURE (°C)
95 110 125
FIGURE 12. SHUTDOWN CURRENT vs TEMPERATURE
FN6931.0
December 21, 2009
ISL80101
Typical Operating Performance
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-40 -25 -10
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
VOUT = 2.5
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0
VOUT = 2.5
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
FIGURE 13. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 14. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
0.80
VOLTAGE (V)
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
-40 -25 -10
5
20
35
50
65
80
95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 15. ENABLE THRESHOLD VOLTAGE vs
TEMPERATURE
FIGURE 17. POWER-DOWN (VIN = 2.2V)
10
FIGURE 16. POWER-UP (VIN = 2.2V)
FIGURE 18. ENABLE START-UP
FN6931.0
December 21, 2009
ISL80101
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
300
START-UP TIME (µs)
250
200
150
100
50
0
2.0
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
6.0
FIGURE 20. START-UP TIME vs SUPPLY VOLTAGE
300
3.5
250
2.5
CURRENT (A)
START-UP (µs)
FIGURE 19. ENABLE SHUTDOWN
2.5
200
150
100
2.0
6V
2.2V
1.5
1.0
0.5
50
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
JUNCTION TEMPERATURE (°C)
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 21. START-UP TIME vs TEMPERATURE
FIGURE 22. CURRENT LIMIT vs TEMPERATURE
3.0
CURRENT LIMIT (A)
2.5
2.0
1.5
1.0
0.5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
6.0
FIGURE 23. CURRENT LIMIT vs SUPPLY VOLTAGE
11
FIGURE 24. CURRENT LIMIT RESPONSE
FN6931.0
December 21, 2009
ISL80101
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
FIGURE 25. LOAD TRANSIENT 0A TO 1A,
COUT = 10µF CERAMIC
FIGURE 26. LOAD TRANSIENT 0A TO 1A,
COUT = 100µF CERAMIC
FIGURE 27. LOAD TRANSIENT 10mA TO 1A,
COUT = 10µF CERAMIC
FIGURE 28. LOAD TRANSIENT 10mA TO 1A,
COUT = 100µF CERAMIC
90
80
70
dB
60
2.2V
50
2V
40
2.5V
30
20
10
0
FIGURE 29. ILINE TRANSIENT
12
IOUT = 1A
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 30. PSRR vs VIN
FN6931.0
December 21, 2009
ISL80101
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
90
90
80
80
70
70
60
100µF
50
dB
47µF
40
50
40
30
30
20
20
10µF
10
0
10
100
1k
10k
100k
100mA
10
IOUT = 1A
1M
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 32. PSRR vs LOAD
FIGURE 31. PSRR vs COUT
10
1
NOISE µV/⎟Hz
dB
60
1A
0.1
0.01
ILOAD
0.001
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 33. SPECTRAL NOISE DENSITY vs FREQUENCY
13
FN6931.0
December 21, 2009
ISL80101
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
12/21/09
FN6931.0
CHANGE
Initial Release to web
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL80101
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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patent or patent rights of Intersil or its subsidiaries.
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14
FN6931.0
December 21, 2009
ISL80101
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
3.00
6
PIN #1 INDEX AREA
A
B
1
6
PIN 1
INDEX AREA
(4X)
3.00
2.00
8x 0.50
2
10 x 0.23
4
0.10
1.60
TOP VIEW
10x 0.35
BOTTOM VIEW
4
(4X)
0.10 M C A B
0.415
PACKAGE
OUTLINE
0.200
0.23
0.35
(10 x 0.55)
SEE DETAIL "X"
(10x 0.23)
1.00
MAX
0.10 C
BASE PLANE
2.00
0.20
C
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
C
0.20 REF
5
1.60
0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
15
FN6931.0
December 21, 2009