Cypress CY7C016A-12AC 32k/16k x8, 32k/16k x9 dual-port static ram Datasheet

CY7C006A
CY7C007A
CY7C017A32K/16K x 8, 32K x 9
Dual-Port Static RAM
CY7C006A/CY7C007A
CY7C016A/CY7C017A
32K/16K x8, 32K/16K x9
Dual-Port Static RAM
Features
• Automatic power-down
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• On-chip arbitration logic
• 16K x 9 organization (CY7C016A)
• Semaphores included to permit software handshaking
between ports
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• INT flags for port-to-port communication
• High-speed access: 12[1]/15/20 ns
• Pin select for Master or Slave
• Low operating power
• Commercial temperature range
— Active: ICC = 180 mA (typical)
— Standby: ISB3 = 0.05 mA (typical)
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
• Fully asynchronous operation
Logic Block Diagram
R/WL
R/WR
CEL
CER
OEL
OER
[2]
8/9
8/9
I/O0L–I/O7/8L
[4]
A0L–A13/14L
[4]
A0L–A13/14L
CEL
OEL
R/WL
SEML
BUSYL
INTL
I/O
Control
14/15
Address
Decode
I/O
Control
Address
Decode
True Dual-Ported
RAM Array
[2]
I/O0R–I/O7/8R
14/15
14/15
[4]
A0R–A13/14R
14/15
[4]
A0R–A13/14R
CER
OER
R/WR
SEMR
Interrupt
Semaphore
Arbitration
[3]
[3]
BUSYR
INTR
M/S
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
1. See page 7 for Load Conditions.
2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
3. BUSY is an output in master mode and an input in slave mode.
4. A0–A13 for 16K; A0–A14 for 32K devices.
Cypress Semiconductor Corporation
Document #: 38-06045 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised April 11, 2005
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Configurations
I/O2L
I/O3L
I/O4L
10
I/O5L
GND
I/O6L
I/O7L
13
A11L
A10L
A9L
A8L
A7L
A6L
64
63
62
61
65
A12L
66
VCC
68
67
CEL
3
A14L[6]
A13L
SEML
4
2
1
R/WL
5
I/O0L
NC(I/O8L[5])
OEL
8
58
12
57
56
55
14
15
CY7C006A (16K x 8)
CY7C007A (32K x 8)
CY7C017A (32K x 9)
16
17
GND
I/O0R
I/O1R
18
I/O2R
VCC
21
22
23
24
19
BUSYL
GND
M/S
51
50
42
43
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A6R
A5R
41
A8R
A7R
A9R
40
38
39
36
37
A11R
A10R
A12R
35
GND
A 14R
A13R
33
34
32
[6
31
44
CER
26
30
46
45
SEMR
25
29
A0L
53
47
OER
R/WR
A3L
A2L
A1L
INTL
49
48
27
28
A5L
A4L
54
52
20
I/O7R
I/O3R
I/O4R
I/O5R
I/O6R
7
6
I/O1L
9
60
59
11
NC(I/O8R[5] )
VCC
68-Pin PLCC
Top View
CE L
NC
A14L
A13L[6]
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
74
72
71
70
69
68
67
66
65
64
63
62
61
NC
NC
SEM L
75
73
R/W L
76
NC
OE L
78
77
1
79
NC
I/O 2L
I/O 3L
80
I/O1L
I/O0L
80-Pin TQFP
Top View
60
NC
A5L
A4L
2
59
I/O 4L
3
4
58
57
I/O 5L
5
56
A3L
A2L
GND
I/O 6L
6
55
A1L
7
54
A0L
I/O 7L
8
53
V CC
9
10
52
51
50
INTL
BUSYL
GND
M/S
49
BUSYR
NC
GND
I/O0R
I/O1R
CY7C007A (32K x 8)
CY7C016A (16K X 9)
11
12
37
38
39
40
A6R
A5R
NC
NC
A7R
34
A9R
35
36
33
A8R
32
A11R
A10R
GND
OER
NC
I/O7R
31
NC
A12R
41
29
30
20
A13R
NC
28
A4R
A 14R[6]
43
42
27
18
19
26
I/O 5R
I/O 6R
NC
44
25
17
CER
46
45
V CC
I/O 3R
I/O 4R
SEMR
15
16
A0R
A1R
23
24
47
R/WR
INTR
14
I/O2R
22
48
21
13
A2R
A3R
NC
Notes:
5. This pin is I/O for CY7C017A only.
6. A14 is a no connect pin for 16K devices.
Document #: 38-06045 Rev. *C
Page 2 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Configurations (continued)
A6L
A5L
49
54
A7L
A12L
56
55
A8L
VCC
57
51
50
CEL
A13L
A9L
SEML
59
52
R/WL
60
53
OEL
62
61
A11L
A10L
I/O0L
63
58
I/O1L
64
64-Pin TQFP
Top View
I/O2L
1
48
A4L
I/O3L
I/O4L
2
47
3
4
46
45
A3L
A2L
5
44
A0L
I/O6L
I/O7L
6
43
7
42
INTL
BUSYL
GND
M/S
I/O5L
GND
CY7C006A (16K x 8)
A1L
A2R
I/O5R
16
33
A4R
30
31
A7R
32
29
BUSYR
A3R
A6R
A5R
28
A8R
41
A9R
A11R
A10R
R/WR
27
35
34
25
26
14
15
24
I/O3R
I/O4R
A12R
A0R
A1R
GND
36
23
13
22
VCC
CER
A13R
37
21
12
SEMR
INTR
I/O2R
19
20
38
OER
11
18
40
39
17
9
10
I/O6R
8
I/O7R
VCC
GND
I/O0R
I/O1R
Selection Guide
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-12[1]
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-15
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-20
Maximum Access Time (ns)
12
15
20
Typical Operating Current (mA)
195
190
180
Typical Standby Current for ISB1 (mA) (Both Ports TTL Level)
Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level)
Document #: 38-06045 Rev. *C
55
50
45
0.05
0.05
0.05
Page 3 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L–A14L
A0R–A14R
Address
I/O0L–I/O8L
I/O0R–I/O8R
Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O0–I/O8 for x9)
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
NC
No Connect
Architecture
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
consist of an array of 32K/16K words of 8 bits and 32K words
of 9 bits each of dual-port RAM cells, I/O and address lines,
and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin
is provided on each port. Two Interrupt (INT) pins can be utilized for
port-to-port communication. Two Semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the devices
can function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The devices also have an automatic
power-down feature controlled by CE. Each port is provided with its
own Output Enable control (OE), which allows data to be read from
the device.
Functional Description
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
low-power CMOS 32K x 8/9 and 16K x 8/9 dual-port static
RAMs. Various arbitration schemes are included on the
devices to handle situations when multiple processors access
the same piece of data. Two ports are provided, permitting
independent, asynchronous access for reads and writes to
any location in memory. The devices can be utilized as
standalone 8/9-bit dual-port static RAMs or multiple devices
can be combined in order to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and
dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
Document #: 38-06045 Rev. *C
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
The CY7C006A, CY7C007A, and CY7C017A are available in
68-pin PLCC packages, the CY7C006A is also available in
64-pin TQFP, and the CY7C007A and CY7C016A are also
available in 80-pin TQFP packages.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF) is the mailbox
for the right port and the second-highest memory location
(7FFE) is the mailbox for the left port. When one port writes to
Page 4 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
the other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. The operation of the interrupts and their interaction
with Busy are summarized in Table 2.
Busy
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
provide on-chip arbitration to resolve simultaneous memory
location access (contention). If both ports’ CEs are asserted
and an address match occurs within tPS of each other, the busy
logic will determine which port has access. If tPS is violated,
one port will definitely gain permission to the location, but it is
not predictable which port will get that permission. BUSY will
be asserted tBLA after an address match or tBLC after CE is
taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Semaphore Operation
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
provide eight semaphore latches, which are separate from the
dual-port memory locations. Semaphores are used to reserve
Document #: 38-06045 Rev. *C
resources that are shared between the two ports. The state of
the semaphore indicates that a resource is in use. For
example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore.
The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was
successful (reads a zero), it assumes control of the shared
resource, otherwise (reads a one) it assumes the right port has
control and continues to poll the semaphore. When the right
side has relinquished control of the semaphore (by writing a
one), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore,
a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
When reading a semaphore, all data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore.
Page 5 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
DC Input Voltage[8] .........................................–0.5V to +7.0V
Maximum Ratings[7]
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage............................................ >2001V
Storage Temperature .................................–65°C to +150°C
Latch-Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.3V to +7.0V
Range
Ambient
Temperature
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
VCC
Commercial
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-12[1]
Parameter
Description
Min.
VOH
Output HIGH Voltage
(VCC = Min., IOH = –4.0 mA)
VOL
Output LOW Voltage
(VCC = Min., IOH = +4.0 mA)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZ
Output Leakage Current
ICC
Operating Current
(VCC = Max., IOUT = 0 mA)
Outputs Disabled
Com’l.
Standby Current
(Both Ports TTL Level)
CEL & CER ≥ VIH, f = fMAX
Com’l.
Standby Current
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
Com’l.
Standby Current
(Both Ports CMOS Level)
CEL & CER ≥ VCC − 0.2V,
f=0
Com’l.
ISB1
ISB2
ISB3
ISB4
Typ.
-15
Max.
2.4
Min.
Typ.
Max.
2.4
2.2
195
–10
325
55
75
Ind.
125
205
Ind.
0.05
0.5
Ind.
115
185
Unit
V
0.4
V
V
0.8
Ind.
Max.
2.2
0.8
10
Typ.
0.4
2.2
–10
Min.
2.4
0.4
Standby Current
Com’l.
(One Port CMOS Level)
Ind.
CEL | CER ≥ VIH, f = fMAX[8, 9]
-20
10
190
280
215
305
50
70
65
95
120
180
135
205
0.05
0.5
0.05
0.5
110
160
125
175
–10
180
0.8
V
10
µA
275
mA
mA
45
65
mA
mA
110
160
mA
mA
0.05
0.5
mA
mA
100
140
mA
mA
Capacitance Table[10]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
10
pF
Notes:
7. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
8. Pulse width < 20 ns.
9. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06045 Rev. *C
Page 6 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
AC Test Loads and Waveforms
5V
5V
R1 = 893Ω
OUTPUT
OUTPUT
C = 30 pF
RTH = 250Ω
R1 = 893Ω
OUTPUT
C = 30 pF
R2 = 347Ω
C = 5 pF
R2 = 347Ω
VTH = 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
AC Test Loads (Applicable to -12 only)[11]
OUTPUT
Z0 = 50Ω
ALL INPUT PULSES
R = 50Ω
3.0V
C
10%
GND
90%
10%
90%
≤ 3 ns
≤ 3 ns
VTH = 1.4V
(a) Load 1 (-12 only)
1 . 00
0. 90
∆ (ns) for all -12 access times
0. 80
0. 70
0. 60
0. 50
0. 40
0. 30
0. 20
0. 1 0
0. 00
10
15
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note:
11. Test Conditions: C = 10 pF.
Document #: 38-06045 Rev. *C
Page 7 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Characteristics Over the Operating Range[12]
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–12[1]
Parameter
Description
Min.
–15
Max.
Min.
–20
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE[13]
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE[14, 15, 16]
OE LOW to Low Z
tHZOE[14, 15, 16]
tLZCE[14, 15, 16]
tHZCE[14, 15, 16]
tPU[16]
tPD[16]
OE HIGH to High Z
CE LOW to Low Z
12
3
3
3
10
3
10
3
10
10
ns
12
ns
ns
12
10
12
20
3
0
ns
ns
12
0
15
ns
ns
3
3
0
ns
20
15
8
3
CE HIGH to Power-Down
20
15
12
CE HIGH to High Z
CE LOW to Power-Up
15
12
ns
ns
20
ns
WRITE CYCLE
tWC
Write Cycle Time
12
15
20
ns
tSCE[13]
CE LOW to Write End
10
12
15
ns
tAW
Address Valid to Write End
10
12
15
ns
tHA
Address Hold From Write End
0
0
0
ns
tSA[13]
Address Set-Up to Write Start
0
0
0
ns
tPWE
Write Pulse Width
10
12
15
ns
tSD
Data Set-Up to Write End
10
10
15
ns
tHD[19]
tHZWE[15, 16]
tLZWE[15, 16]
tWDD[17]
tDDD[17]
Data Hold From Write End
0
0
0
ns
BUSY TIMING
R/W LOW to High Z
R/W HIGH to Low Z
10
3
10
3
12
3
ns
ns
Write Pulse to Data Delay
25
30
45
ns
Write Data Valid to Read Data Valid
20
25
30
ns
[18]
tBLA
BUSY LOW from Address Match
12
15
20
ns
tBHA
BUSY HIGH from Address Mismatch
12
15
20
ns
tBLC
BUSY LOW from CE LOW
12
15
20
ns
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-Up for Priority
12
5
15
5
17
5
ns
ns
Notes:
12. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
13. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
14. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
15. Test conditions used are Load 3.
16. This parameter is guaranteed but not tested.
17. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
18. Test conditions used are Load 2.
19. For 15 ns industrial parts tHD Min. is 0.5 ns.
Document #: 38-06045 Rev. *C
Page 8 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Characteristics Over the Operating Range[12] (continued)
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–12[1]
Parameter
Description
Min.
–15
Max.
Min.
–20
Max.
Min.
Max.
Unit
tWB
R/W HIGH after BUSY (Slave)
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
11
13
15
ns
tBDD[20]
BUSY HIGH to Data Valid
INTERRUPT TIMING
12
15
20
ns
[18]
tINS
INT Set Time
12
15
20
ns
tINR
INT Reset Time
12
15
20
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE or SEM)
10
10
10
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
ns
tSPS
SEM Flag Contention Window
5
5
5
ns
tSAA
SEM Address Access Time
12
15
20
ns
Timing
Data Retention Mode
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The
following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
Data Retention Mode
VCC
4.5V
VCC > 2.0V
4.5V
VCC to VCC – 0.2V
CE
tRC
V
IH
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 volts).
Parameter
ICCDR1
Test Conditions[21]
@ VCCDR = 2V
Max.
Unit
1.5
mA
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[22, 23, 24]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
tOHA
DATA VALID
Notes:
20. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
21. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
22. R/W is HIGH for read cycles.
23. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
24. OE = VIL.
Document #: 38-06045 Rev. *C
Page 9 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Read Cycle No. 2 (Either Port CE/OE Access)[22, 25, 26]
tACE
CE
tDOE
OE
tHZCE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Read Cycle No. 3 (Either Port)[22, 24, 25, 26]
tRC
ADDRESS
tAA
tOHA
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes:
25. Address valid prior to or coincident with CE transition LOW.
26. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document #: 38-06045 Rev. *C
Page 10 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing [27, 28, 29, 30]
tWC
ADDRESS
tHZOE [32]
OE
CE
tAW
[31]
tPWE[30]
tSA
tHA
R/W
tHZWE[32]
DATA OUT
tLZWE
NOTE 33
NOTE 33
tSD
tHD
DATA IN
Write Cycle No. 2: CE Controlled Timing [27, 28, 29, 34]
tWC
ADDRESS
tAW
CE
[31]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes:
27. R/W or CE must be HIGH during all address transitions.
28. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
29. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
30. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified tPWE.
31. To access RAM, CE = VIL, SEM = VIH.
32. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
33. During this period, the I/O pins are in the output state, and input signals must not be applied.
34. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06045 Rev. *C
Page 11 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[35]
tOHA
tAA
A 0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tSCE
tSOP
tSD
I/O0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[36, 37, 38]
A0L –A2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes:
35. CE = HIGH for the duration of the above timing (both write and read cycle).
36. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
37. Semaphores are reset (available to both ports) at cycle start.
38. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 38-06045 Rev. *C
Page 12 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[39]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tHD
tSD
DATA INR
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Write Timing with Busy Input (M/S=LOW)
tPWE
R/W
BUSY
tWB
tWH
Note:
39. CEL = CER = LOW.
Document #: 38-06045 Rev. *C
Page 13 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[40]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSYL
Busy Timing Diagram No. 2 (Address Arbitration)[40]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note:
40. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document #: 38-06045 Rev. *C
Page 14 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
tWC
ADDRESSL
WRITE 7FFF
tHA[41]
CE L
R/W L
INT R
tINS [42]
Right Side Clears INTR:
tRC
READ 7FFF
ADDRESSR
CE R
tINR [42]
R/WR
OE R
INTR
Right Side Sets INTL:
tWC
ADDRESSR
WRITE 7FFE
tHA[41]
CE R
R/W R
INT L
[42]
tINS
Left Side Clears INTL:
tRC
ADDRESSR
READ 7FFE
CE L
tINR[42]
R/W L
OE L
INT L
Notes:
41. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
42. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 38-06045 Rev. *C
Page 15 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
R/W
OE
SEM
H
X
X
H
High Z
Deselected: Power-Down
H
H
L
L
Data Out
Read Data in Semaphore Flag
X
X
H
X
High Z
I/O Lines Disabled
X
L
Data In
Write into Semaphore Flag
H
I/O0–I/O8
Operation
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
L
X
X
L
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Left Port
Right Port
R/WL
CEL
OEL
A0L–14L
INTL
R/WR
CER
OER
A0R–14R
INTR
Set Right INTR Flag
L
L
X
7FFF
X
X
X
X
X
L[44]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
7FFF
H[43]
Set Left INTL Flag
X
X
X
X
L[43]
L
L
X
7FFE
X
Reset Left INTL Flag
X
L
L
7FFE
H[44]
X
X
X
X
X
Function
Table 3. Semaphore Operation Example
Function
I/O0–I/O8 Left
I/O0–I/O8Right
No action
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left Port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Status
Notes:
43. If BUSYR = L, then no change.
44. If BUSYL= L, then no change.
Document #: 38-06045 Rev. *C
Page 16 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Ordering Information
16K x8 Asynchronous Dual-Port SRAM
Speed
(ns)
12[1]
15
20
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C006A-12AC
A65
64-Pin Thin Quad Flat Pack
Commercial
CY7C006A-12JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
CY7C006A-15AC
A65
64-Pin Thin Quad Flat Pack
Commercial
CY7C006A-15JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
CY7C006A-20AC
A65
64-Pin Thin Quad Flat Pack
Commercial
CY7C006A-20JC
J81
68-Pin Plastic Leaded Chip CarrieR
Commercial
32K x8 Asynchronous Dual-Port SRAM
Speed
(ns)
12[1]
15
20
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C007A-12AC
A80
80-Pin Thin Quad Flat Pack
Commercial
CY7C007A-12JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
CY7C007A-15AC
A80
80-Pin Thin Quad Flat Pack
Commercial
CY7C007A-15JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
CY7C007A-20AC
A80
80-Pin Thin Quad Flat Pack
Commercial
CY7C007A-20JC
J81
68-Pin Plastic Leaded Chip CarrieR
Commercial
16K x9 Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
12[1]
CY7C016A-12AC
A80
80-Pin Plastic Leaded Chip Carrier
Commercial
15
CY7C016A-15AC
A80
80-Pin Plastic Leaded Chip Carrier
Commercial
20
CY7C016A-20AC
A80
80-Pin Plastic Leaded Chip Carrier
Commercial
32K x9 Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
12[1]
CY7C017A-12JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
15
CY7C017A-15JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
20
CY7C017A-20JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
Document #: 38-06045 Rev. *C
Page 17 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-*B
Document #: 38-06045 Rev. *C
Page 18 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Package Diagrams (continued)
80-Pin Thin Plastic Quad Flat Pack A80
51-85065-*B
68-Lead Plastic Leaded Chip Carrier J81
51-85005-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06045 Rev. *C
Page 19 of 20
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Document History Page
Document Title: CY7C006A/CY7C007A/CY7C016A/CY7C017A 32K/16K x 8, 32K/16K x 9 Dual Port Static RAM
Document Number: 38-06045
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
110197
09/29/01
SZV
Change from Spec number: 38-00831 to 38-06045
*A
122295
12/27/02
RBI
Power up requirements added to Maximum Ratings Information
*B
237620
See ECN
YDT
Removed cross information from features section
*C
345376
See ECN
AEQ
Removed I-Temp versions for both packages, since they are not valid part
numbers.
Document #: 38-06045 Rev. *C
Description of Change
Page 20 of 20