AD ADP3607 50 ma switched capacitor voltage boost with regulated output Datasheet

a
50 mA Switched Capacitor
Voltage Boost with Regulated Output
ADP3607
FEATURES
Fully Regulated Output Voltage (5 V and Adjustable)
Input Voltage Range From 3 V to 5 V
50 mA Output Current
Output Accuracy: ⴞ5%
High Switching Frequency: 250 kHz
SO-8 and TSSOP-8 Packages
–40ⴗC to +85ⴗC Ambient Temperature Range
APPLICATIONS
Computer Peripherals and Add-On Cards
Portable Instruments
Battery Powered Devices
Pagers and Radio Control Receivers
Disk Drives
Mobile Phones
FUNCTIONAL BLOCK DIAGRAM
CP–
CP+
V
S1
S3
IN
S4
S2
V
OUT
SD
OSC
CLOCK
GEN
FB
GENERAL DESCRIPTION
The ADP3607 provides an accuracy of ± 5% with a typical shutdown current of 150 µA. It can also operate from a single positive input voltage as low as 3 V. The ADP3607 is offered with
the regulation fixed at 5 V, or adjustable via external resistors
over a 3 V to 9 V range.
SENSE
GND
The ADP3607 is a 50 mA regulated output switched capacitor
voltage doubler. It provides a regulated output voltage with
minimum voltage loss and requires a minimum number of external components. In addition, the ADP3607 does not require
the use of an inductor.
The internal oscillator of the ADP3607 runs at 500 kHz nominal frequency, which produces an output switching frequency of
250 kHz. This allows for the use of smaller charge pump and
filter capacitors.
V
1.5 V
VREF
SD103
D1
VIN
3.3V
VOUT
VIN
*CIN+
4.7mF
CP+
*CP
4.7mF
+
+
VOUT
5.0V
*CO
4.7mF
ADP3607-5
CP –
SD
OFF
GND
VSENSE
ON
0
*FOR BEST PERFORMANCE, 10mF IS RECOMMENDED
CP : SPRAGUE, 293D475X0010B2W
CIN, CO: TOKIN, 1E475ZY5UC205F
Figure 1. Typical Application Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADP3607–SPECIFICATIONS1, 2, 3(V
IN
= 3.3 V @ TA = +25ⴗC, CP = CO = 4.7 ␮F unless otherwise noted.)
Parameter
Symbol
Condition
OPERATING SUPPLY RANGE
VS
SUPPLY CURRENT
Shutdown Mode
IS
–40°C < TA < +85°C
VSD = VIN, –40°C < TA < +85°C
VO
VO
IO = 25 mA
IO = 10 mA to 50 mA
–40°C ≤ TA ≤ +85°C
3.0 V ≤ VS ≤ 3.6 V
LOAD REGULATION
∆VO/IO
IO = 10 mA–25 mA
IO = 10 mA–50 mA
OUTPUT RESISTANCE (Open Loop)
RO
OUTPUT RIPPLE VOLTAGE
VRIPPLE
Min
Typ
Max
Units
3.0
3.3
5
V
3.5
150
6
200
mA
µA
5
5
5.15
5.25
V
V
OUTPUT VOLTAGE4
SWITCHING FREQUENCY
SHUTDOWN
Logic Input High
Input Current
Logic Input Low
Input Current
fS
4.85
4.75
CIN = CO = 4.7 µF
ILOAD = 25 mA
ILOAD = 50 mA
VIN = 3.3 V
–40°C < TA < +85°C
212
0.3
0.25
mV/mA
mV/mA
11
Ω
16
31
mV
mV
250
288
2.4
VIH
IIH
VIL
IIL
1
0.4
1
kHz
V
µA
V
µA
NOTES
1
Capacitors CIN, CO and CP in the test circuit are 4.7 µF with 0.1 Ω ESR. Capacitors with higher ESR may reduce output voltage and efficiency.
2
See Figure 1 conditions.
3
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
4
For the adjustable version, a 1% resistor should be used to maintain output voltage tolerance. For both device types, tolerances can be improved by >1% using larger
value and lower ESR capacitors for C O and C P.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
(TA = +25°C unless otherwise noted)
Input Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . +7.5 V
Output Voltage (VOUT to GND) . . . . . . . . . . . . . . . . . . +12 V
Output Short Circuit Protection . . . . . . . . . . . . . . . . . . . 1 sec
θJA, SO-8 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
θJA, TSSOP-8 Package2 . . . . . . . . . . . . . . . . . . . . . . 208°C/W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Model
Output Voltage
Package Option*
ADP3607AR-5
ADP3607AR
ADP3607ARU-5
ADP3607ARU
5 V, 50 mA
Adjustable, 50 mA
5 V, 50 mA
Adjustable, 50 mA
SO-8
SO-8
RU-8
RU-8
*SO = Small Outline Package; RU = Thin Small Outline Package.
Contact the factory for the availability of other output voltage options.
NOTES
1
This is a stress rating only, operation beyond these limits can cause the device to be
permanently damaged.
2
θJA is specified for worst case conditions with device soldered on a circuit board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3607 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–2–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
ADP3607
Table I. Other Members of ADP360x Family 1
PIN FUNCTION DESCRIPTIONS
Model
Output
Current
Package
Option2
Comments
ADP3603AR
ADP3604AR
ADP3605AR-3
ADP3605AR
50 mA
120 mA
120 mA
120 mA
SO-8
SO-8
SO-8
SO-8
Nom. –3 V ± 3% Inverter
Nom. –3 V ± 3% Inverter
Nom. –3 V ± 5% Inverter
Adj. Output Inverter
Pin Mnemonic
NOTES
1
See individual data sheets for detailed ordering information.
2
SO = Small Outline package.
1
2
CP+
VIN
3
4
CP –
SD
5
VSENSE
6
7
8
NC
GND
VOUT
Table II. Alternative Capacitor Technologies
Type
Life
High
Freq
Temp
Size
Cost
Aluminum
Electrolytic
Capacitor
Fair
Fair
Fair
Small
Low
Multilayer
Ceramic
Capacitor
Long
Good
Poor
Fair
High
Solid
Tantalum
Capacitor
Above Avg
Avg
Avg
Avg
Avg
OS-CON
Capacitor
Above Avg
Good
Good
Good
Avg
Function
Positive Terminal for the Pump Capacitor.
Input Voltage. Connect a low ESR bypass
capacitor between this pin and device
ground to minimize supply transients.
Negative Terminal for the Pump Capacitor.
Logic Level Shutdown. Apply a logic Hi or
connect to VIN to shut down the device. In
Shutdown mode, the charge pump is turned
off and quiescent current is reduced. Apply
a logic low or connect to ground for normal
operation.
Output Voltage Sense Line. This is used to
improve load regulation by eliminating IR
drops on the high current carrying output
traces. For normal operation, connect
VSENSE to VOUT. See Application Information section for more detail.
No Connection.
Ground.
Regulated Output Voltage. Connect a low
ESR, 4.7 µF or larger capacitor between
this pin and device GND.
PIN CONFIGURATION
Table III. Recommended Capacitor Manufacturers
8 VOUT
CP+ 1
Manufacturer
Capacitor
Sprague
672D, 673D,
674D, 678D
675D, 173D,
199D
PF and PL
TDC and TDL
MLCC
GRM
Sprague
Nichicon
Mallory
TOKIN
MuRata
REV. 0
Capacitor Type
ADP3607
7 GND
TOP VIEW
CP– 3 (Not to Scale) 6 NC
VIN 2
SD 4
Aluminum Electrolytic
5 VSENSE
NC = NO CONNECT
Tantalum
Aluminum Electrolytic
Tantalum
Multilayer Ceramic
Multilayer Ceramic
–3–
270
4.00
265
3.75
SUPPLY CURRENT – mA
OSCILLATOR FREQUENCY – kHz
ADP3607 –Typical Performance Characteristics
260
255
3.5
4.0
4.5
SUPPLY VOLTAGE – Volts
VIN = +3.3V
3.25
3.00
–40
5.0
Figure 2. Oscillator Frequency vs. Supply Voltage
–15
10
35
TEMPERATURE – 8C
60
85
Figure 5. Supply Current vs. Temperature in Normal Mode
300
OSCILLATOR FREQUENCY – kHz
5.05
5.03
OUTPUT VOLTAGE – Volts
VIN = +4.0V
3.50
VIN = +3.0V
250
3.0
IL = 10mA
IL = 25mA
5.01
4.99
IL = 50mA
4.97
4.95
–40
–15
10
35
TEMPERATURE – 8C
60
280
260
240
220
200
–40
85
Figure 3. Output Voltage vs. Temperature
–15
10
35
TEMPERATURE – 8C
60
85
Figure 6. Oscillator Frequency vs. Temperature
5.05
125
5.00
100
OUTPUT VOLTAGE – Volts
AVERAGE INPUT CURRENT – mA
VIN = +5.0V
75
50
4.95
VIN = +5.0V
4.90
VIN = +4.0V
4.85
VIN = +3.3V
4.80
VIN = +3.0V
25
4.75
0
4.70
10
15
20
25
30
35
40
OUTPUT CURRENT – mA
45
50
0
Figure 4. Average Input Current vs. Output Current
25
50
75
125
100
LOAD CURRENT – mA
150
175
200
Figure 7. Output Voltage vs. Load Current
–4–
REV. 0
ADP3607
3.7
300
250
SUPPLY CURRENT – mA
SUPPLY CURRENT – mA
3.6
FIXED VERSION
3.5
ADJUSTABLE VERSION
R = 38kV
3.4
200
FIXED VERSION
150
100
ADJUSTABLE VERSION
R = 38kV
50
3.3
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE – Volts
0
3.0
5.0
Figure 8. Supply Current vs. Supply Voltage in
Normal Mode
4.0
4.5
SUPPLY VOLTAGE – Volts
5.0
Figure 11. Supply Current vs. Supply Voltage in
Shutdown Mode
240
80
VIN = +5.0V
70
220
60
200
EFFICIENCY – %
SUPPLY CURRENT – mA
3.5
VIN = +4.0V
180
160
50
40
30
VIN = +3.3V
20
140
10
VIN = +3.0V
120
–40
–15
10
35
TEMPERATURE – 8C
60
0
0
85
Figure 9. Supply Current vs. Temperature in
Shutdown Mode
10
20
30
LOAD CURRENT – mA
50
Figure 12. Efficiency vs. Load Current Based on Circuit of
Figure 1
VO = +5.0V
VO = +5.0V
VOUT
VOUT
VO = +4.96V
VO = 0V
IO = 50mA
IL
VIN = +3.3V
VIN
T
CH1 2.00V CH2 2.00V M2.00ms CH2
IO = 1mA
VIN = 0V
CH2 20.0mV BW M4.00ms CH4
CH4 10.0mV V BW
1.12V
Figure 10. Start-up Under Full Load Based on Circuit of
Figure 1
REV. 0
40
9.0mV
Figure 13. Load Transient Response Based on Circuit of
Figure 1
–5–
ADP3607
THEORY OF OPERATION
When selecting the capacitors, keep in mind that not all manufacturers guarantee capacitor ESR in the range required by the
circuit. In general, the capacitor’s ESR is inversely proportional
to its physical size, so larger capacitance values and higher voltage ratings tend to reduce ESR. Since the ESR is also a function
of the operating frequency, when selecting a capacitor make sure
its value is rated at the circuit’s operating frequency. Another
factor affecting capacitor performance is temperature.
The ADP3607 uses a switched capacitor principle to generate
a regulated boost voltage from a positive input voltage. An
on-board oscillator generates a two-phase clock to control a
switching network that transfers charge between the storage
capacitors. The switches turn on and off at a 250 kHz rate that
is generated from an internal 500 kHz oscillator. The basic
principle behind the voltage conversion scheme is illustrated in
Figures 14 and 15.
VIN
S1
S2
CP
S4
Figure 16 illustrates the temperature effect on various capacitors. If the circuit has to operate at temperatures significantly
different from +25°C, the capacitance and ESR values must be
carefully selected to adequately compensate for the change.
Various capacitor technologies offer improved performance over
temperature; for example, certain tantalum capacitors provide
good low temperature ESR but at a higher cost. Table II provides the ratings for different types of capacitor technologies to
help the designer select the right capacitors for the application.
The exact values of CIN and CO are not critical. However, low
ESR capacitors such as solid tantalum and multilayer ceramic
capacitors are recommended to minimize voltage loss at high
currents. Table III shows a partial list of the recommended low
ESR capacitor manufacturers.
VOUT
+
–
S3
Figure 14. ADP3607 Switch Configuration Charging the
Pump Capacitor
During phase one, S1 and S3 are ON, charging the pump capacitor to the input voltage. Before the next phase begins, S1
and S3 are turned OFF, as are S2 and S4 to prevent any overlap. S2 and S4 are turned ON during the second phase (see
Figure 15) and charge stored in the pump capacitor is transferred to the output capacitor.
40
S1
S2
CP
S4
VOUT
ADP3607-5
+
–
35
S3
OUTPUT RIPPLE – mV
VIN
Figure 15. ADP3607 Switch Configuration Charging the
Output Capacitor
During the second phase, the negative terminal of the pump
capacitor is connected to VIN through variable resistance switch
S4, and the positive terminal is connected to the output, resulting in a voltage shift at the output terminal. The ADP3607
block diagram is shown on the front page.
30
ILOAD = 50mA
25
20
150mV
15
100mV
10
50mV
5
10
0
20
ALUMINUM
40
60
80
100
CAPACITANCE – mF
120
140
Figure 17. Output Ripple Voltage (mV) vs. Capacitance
and ESR
ESR – V
1.0
Input Capacitor
CERAMIC
A small 1 µF input bypass capacitor (preferably with low ESR)
such as tantalum or multilayer ceramic, is recommended to
reduce noise and supply transients, and supply part of the peak
input current drawn by the ADP3607. A large capacitor is recommended if the input supply is connected to the ADP3607
through long leads, or if the pulse current drawn by the device
might affect other circuitry through supply coupling.
TANTALUM
0.1
ORGANIC SEMIC
0.01
–50
0
50
TEMPERATURE – 8C
Output Capacitor
100
The output capacitor (CO) is alternately charged to the CP voltage when CP is switched in parallel with CO. The ESR of CO
introduces steps in the VOUT waveform whenever the charge
pump charges CO, which contributes to VOUT ripple. Thus,
ceramic or tantalum capacitors are recommended for CO to
minimize ripple on the output. Figure 17 illustrates the output
ripple voltage effect for various capacitance and ESR values.
Note that as the capacitor value increases beyond the point
where the dominant contribution to the output ripple is due to
the ESR, no significant reduction in VOUT ripple is achieved by
added capacitance. Since output current is supplied solely by
Figure 16. ESR vs. Temperature
APPLICATION INFORMATION
Capacitor Selection
The ADP3607’s high internal oscillator frequency permits the
use of small capacitors for both the pump and the output capacitors. For a given load current, factors affecting the output
voltage performance are:
• Pump (CP) and output (CO) capacitance.
• ESR of the CP and CO.
–6–
REV. 0
ADP3607
the output capacitor, CO, during one-half of the charge-pump
cycle, peak-to-peak output ripple voltage is calculated by using
the following formula.
VRIPPLE =
IL
2 × FPUMP × CO
Because of the external Schottky diode between VIN and VOUT,
the output voltage will be held to a diode drop below VIN when
the ADP3607 is in shutdown mode.
Power Dissipation
+ 2 × I L × ESRCO
The power dissipation of the ADP3607 circuit must be limited
such that the junction temperature of the device does not exceed
the maximum junction temperature rating. Total power dissipation is calculated as follows:
where
IL = Load Current
P = (2 VIN – VOUT) IOUT + (VIN) IS
FPUMP = 250 kHz nominal switching frequency
CO = 10 µF with an ESR of 0.15 Ω
VRIPPLE =
Where IOUT and IS are output current and supply current, VIN
and VOUT are input and output voltages respectively.
50 mA
+ 2 × 50 mA × 0.15 = 25 mV
2 × 250 kHz × 10 µF
For example: assuming worst case conditions, VIN = 5 V,
VOUT = 5 V, IOUT = 50 mA and IS = 6 mA. Calculated device
power dissipation is:
Multiple smaller capacitors can be connected in parallel to yield
lower ESR and potential cost savings. For lighter loads, proportionally smaller capacitors are required. To reduce high frequency
noise, bypass the output with a 0.1 µF ceramic capacitor in parallel
with the output capacitor.
P ≈ (2 × 5 V – 5 V)(0.05 A) + (5 V)(0.006 A) = 280 mW
This is far below the 660 mW power dissipation capability of the
ADP3607.
General Board Layout Guidelines
Pump Capacitor
The ADP3607 alternately charges CP to the input voltage when
CP is switched in parallel with the input supply, and then transfers charge to CO when CP is switched in parallel with CO. During the time CP is charging, the peak current is approximately
two times the output current. During the time CP is delivering
charge to CO, the supply current drops down to about 3 mA.
Since the ADP3607’s internal switches turn on and off very
quickly, good PC board layout practices are critical to ensure
optimal operation of the device. Improper layouts will result in
poor load regulation, especially with heavy loads. Following
these simple layout guidelines will improve output performance.
A low ESR capacitor has much greater impact on performance
for CP than CO since current through CP is twice the CO current. Therefore, the voltage drop due to CP is about four times
the ESR of CP times the load current. While the ESR of CO
affects the output ripple voltage, the voltage drop generated by
the ESR of CP, combined with the voltage drop due to the output source resistance, determines the maximum available VOUT.
2. Use single point ground for device ground and input and
output capacitor grounds.
Improved Load Regulation
Maximum unregulated output voltage can be obtained by connecting the VSENSE pin to ground instead of to the VOUT pin (see
Figure 18). Under this condition, the magnitude of the unregulated output voltage depends on the load current. VOUT is
inversely proportional to the load current.
1. Use adequate ground and power traces or planes.
3. Keep external components as close to the device as possible.
4. Use short traces from the input and output capacitors
to the input and output pins respectively.
Maximum Output Voltage
In most applications, IR drops due to printed circuit board
traces are not critical. VSENSE should be connected to the output
at a convenient pcb location close to the load. However, if a
reduction in IR drops, or improvement in load regulation is
desired, the sense line can be used to monitor the output voltage
at the load. To avoid excessive noise pickup, keep the VSENSE
line as short as possible and away from any noisy line.
7.3
7.1
VIN = 3.6V
OUTPUT VOLTAGE – Volts
Shutdown Mode
The ADP3607’s output can be disabled by pulling the SD Pin
to a TTL /CMOS logic high level which will stop the internal
oscillator. Applying a logic low will turn ON the oscillator. If
the shutdown feature is not used, the SD pin should be tied to
ground. The shutdown mode current is dominated by the resistor divider connected to the VSENSE pin. This current can be
calculated using one of the following formulas.
5 V fixed output version:
(VIN – 0.3V )
23.75 kΩ
VIN = 3.3V
6.5
IN5819
6.3
D1
VIN
6.1
CIN
5.9
VIN VOUT
+
CP +
4.7mF
4.7mF
CP+
VSENSE
CP–
SD GND
VO
+
CO
4.7mF
5.5
0
Adjustable output version:
5
10
15
20
25
30
35
OUTPUT CURRENT – mA
40
45
50
Figure 18. Maximum Unregulated Output Voltage
(VIN – 0.3 V )
=
(9.5 kΩ + REXT )
where REXT is in kΩ.
REV. 0
6.7
5.7
I SENSE(SD ) =
I SENSE(SD )
6.9
–7–
ADP3607
Regulated Adjustable Output Voltage
D3
IN5819
VOUT =
C1
4.7mF
+
12V
+C
O2
D1
1N5819
ADP3607
CP+
CP +
4.7mF
VOUT
4.7mF
R1
104.5kV
+C
O
4.7mF
CP–
VSENSE
VIN
CIN
4.7mF
VIN
SD
+
GND
Figure 20. Regulated 12 V from a 5 V Input
Regulated Dual Supply System
The circuit in Figure 21 provides regulated positive and negative
voltages for systems that require dual supplies from a single
battery or power supply.
R
+1
9.5
SD103
where VOUT is in volts and R is in kΩs.
ADP3607-5
6.5
VIN = +3.3V
10mF
R = 47.5kV
6.0
OUTPUT VOLTAGE – Volts
D2
SD103
C3500–8–8/99
For the adjustable version of the ADP3607, the regulated output voltage is programmed by a resistor that is inserted between
the VSENSE and VOUT pins, as illustrated in Figure 19. The inherent limit of the output voltage of a single doubling charge
pump stage is two times the input voltage. The scaling factor of
2.00 is reduced somewhat due to losses that increase with output current. To increase the scaling factor to attain a more
positive output voltage, an external pump stage can be added
with just passive components as shown in Figure 20. That single
stage increases the scaling factor to a limit of 3, although the
diode drops will limit the ability to noticeably attain that exact
3.00 scaling factor. Even further increases can be achieved
with more external pump stages. High accuracy on the adjustable output is achieved through the use of precision trimmed
internal resistors, which eliminates the need to trim the external
resistor or add a second resistor to form a divider. The adjustable output voltage is set using the following formula:
VIN
+
VOUT
+C
+5V
O1
CP1
10mF
+
CP+
10mF
VSENSE
CP–
5.5
GND
SD
IN5819
D1
5.0
VIN = 3.3V
CIN
CP
4.7mF
4.5
VO
VIN VOUT
+
+
CP+
R
VSENSE
CP–
SD GND
4.7mF
+
ADP3605
CO
4.7mF
VIN
CP2
10mF
4.0
+
CP+
VSENSE
SD
3.5
5
10
15
20
25
30
35
OUTPUT CURRENT – mA
40
45
R1
16.5kV
1%
CO2
+10mF
CP–
R = 24.9kV
0
–2.6V
VOUT
GND
50
Figure 19. Regulated Adjustable Output Voltage
Figure 21. Regulated Dual Supply System
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
0.122 (3.10)
0.114 (2.90)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
8
5
1
4
PRINTED IN U.S.A.
8-Lead TSSOP
(RU-8)
8
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0500 0.0192 (0.49)
SEATING (1.27)
0.0098 (0.25)
PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
5
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
0.0196 (0.50)
x 45°
0.0099 (0.25)
1
4
PIN 1
0.0256 (0.65)
BSC
8°
0° 0.0500 (1.27)
0.0160 (0.41)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
–8–
0.0118 (0.30)
0.0075 (0.19)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
88
08
0.028 (0.70)
0.020 (0.50)
REV. 0