Pr E2G0129-17-61 im el y 2,097,152-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM51V17805D/DSL is a 2,097,152-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM51V17805D/DSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal CMOS process. The MSM51V17805D/DSL is available in a 28-pin plastic SOJ or 28-pin plastic TSOP. The MSM51V17805DSL (the self-refresh version) is specially designed for lower-power applications. FEATURES • 2,097,152-word ¥ 8-bit configuration • Single 3.3 V power supply, ±0.3 V tolerance • Input : LVTTL compatible, low input capacitance • Output : LVTTL compatible, 3-state • Refresh : 2048 cycles/32 ms, 2048 cycles/128 ms (SL version) • Fast page mode with EDO, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Multi-bit test mode capability • Package options: 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM51V17805D/DSL-xxJS) 28-pin 400 mil plastic TSOP (TSOPII28-P-400-1.27-K) (Product : MSM51V17805D/DSL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA ar This version: Mar. 1998 MSM51V17805D/DSL in ¡ Semiconductor MSM51V17805D/DSL ¡ Semiconductor Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM51V17805D/DSL-50 50 ns 25 ns 13 ns 13 ns 84 ns 360 mW MSM51V17805D/DSL-60 60 ns 30 ns 15 ns 15 ns 104 ns 324 mW MSM51V17805D/DSL-70 70 ns 35 ns 20 ns 20 ns 124 ns 288 mW 1.8 mW/ 0.72 mW (SL version) 1/17 ¡ Semiconductor MSM51V17805D/DSL PIN CONFIGURATION (TOP VIEW) VCC 1 28 VSS VCC 1 DQ1 2 27 DQ8 DQ1 2 27 DQ8 DQ2 3 26 DQ7 DQ2 3 26 DQ7 DQ3 4 25 DQ6 DQ3 4 25 DQ6 DQ4 5 24 DQ5 DQ4 5 24 DQ5 WE 6 23 CAS WE 6 23 CAS RAS 7 22 OE RAS 7 22 OE NC 8 21 A9 NC 8 21 A9 A10R 9 20 A8 A10R 9 20 A8 A0 10 19 A7 A0 10 19 A7 A1 11 18 A6 A1 11 18 A6 A2 12 17 A5 A2 12 17 A5 A3 13 16 A4 A3 13 16 A4 VCC 14 15 VSS VCC 14 15 VSS 28-Pin Plastic SOJ Pin Name A0 - A9, A10R RAS Note : 28 VSS 28-Pin Plastic TSOP (K Type) Function Address Input Row Address Strobe CAS Column Address Strobe DQ1 - DQ8 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (3.3 V) VSS Ground (0 V) The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/17 ¡ Semiconductor MSM51V17805D/DSL BLOCK DIAGRAM RAS WE Timing Generator OE I/O Controller CAS 8 Output Buffers 8 Input Buffers 8 DQ1 - DQ8 10 Internal Address Counter A0 - A9 10 A10R Column Address Buffers 1 10 Refresh Control Clock Row Row Address 11 DecoBuffers ders Word Drivers Column Decoders Sense Amplifiers 8 I/O Selector 8 8 Memory Cells VCC On Chip VBB Generator VSS 3/17 ¡ Semiconductor MSM51V17805D/DSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Unit Symbol Rating Voltage on Any Pin Relative to VSS VT –0.5 to 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 — VCC + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V Capacitance (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A9, A10R) CIN1 — 5 pF Input Capacitance (RAS, CAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ8) CI/O — 7 pF Parameter 4/17 ¡ Semiconductor MSM51V17805D/DSL DC Characteristics Parameter (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Symbol Condition MSM51V17805 MSM51V17805 MSM51V17805 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –2.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0 mA 0 0.4 0 0.4 0 0.4 V –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 100 — 90 — 80 mA 1, 2 — 2 — 2 — 2 — 0.5 — 0.5 — 0.5 mA 1 — 200 — 200 — 200 mA 1, 5 — 100 — 90 — 80 mA 1, 2 — 5 — 5 — 5 mA 1 — 100 — 90 — 80 mA 1, 2 — 100 — 90 — 80 mA 1, 3 — 300 — 300 — 300 mA — 300 — 300 — 300 mA 0 V £ VI £ VCC + 0.3 V; Input Leakage Current ILI All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) DQ disable 0 V £ VO £ VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, Average Power Supply Current ICC3 CAS = VIH, (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, DQ = enable Average Power Supply Current ICC6 (CAS before RAS Refresh) ICC7 CAS cycling, (Fast Page Mode) tHPC = Min. tRC = 62.5 ms, Average Power Supply Current CAS before RAS RAS = VIL, Average Power Supply Current RAS cycling, ICC10 CAS before RAS, tRAS £ 1 ms (Battery Backup) 1, 4, 5 Average Power Supply Current (CAS before RAS ICCS RAS £ 0.2 V, CAS £ 0.2 V 1, 5 Self-Refresh) Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ VCC + 0.3 V, –0.3 V £ VIL £ 0.2 V. SL version. 5/17 ¡ Semiconductor MSM51V17805D/DSL AC Characteristics (1/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13 Parameter Random Read or Write Cycle Time Symbol tRC MSM51V17805 MSM51V17805 MSM51V17805 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. — 104 124 ns ns Read Modify Write Cycle Time tRWC 84 110 135 160 — — Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time tHPC 20 — — — — 25 — 30 — ns tHPRWC 58 — 68 — 78 — ns Access Time from RAS tRAC — 50 — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC — 13 — 15 — 20 ns 4, 5 Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 25 30 — — 30 35 — — 35 40 ns ns 4, 6 4 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 13 — — 0 15 — — 0 20 — ns ns 4 4 Data Output Hold After CAS Low tDOH 5 — 5 — 5 — ns CAS to Data Output Buffer Turn-off Delay Time tCEZ 0 13 0 15 0 20 ns 7, 8 RAS to Data Output Buffer Turn-off Delay Time tREZ 0 0 15 15 0 0 20 20 7, 8 tOEZ tWEZ 13 13 ns OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time 0 0 13 50 32 0 1 — 15 50 32 0 1 — 20 50 32 ns ns 7 7 ns ms 3 14 Transition Time Refresh Period tREF 0 1 — Refresh Period (SL version) tREF — 128 — 128 — 128 ms RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode with EDO) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH 7 RAS Hold Time referenced to OE tROH 7 — — 10 10 — — 13 13 — — ns ns CAS Precharge Time (Fast Page Mode with EDO) tCP 7 — 10 — 10 — ns CAS Pulse Width tCAS 7 10,000 10 10,000 13 10,000 ns CAS Hold Time tCSH — 45 5 — — 40 5 — tCRP 35 5 — CAS to RAS Precharge Time — ns ns tT RAS Hold Time from CAS Precharge tRHCP 30 — 35 — 40 — ns OE Hold Time from CAS (DQ Disable) tCHO RAS to CAS Delay Time tRCD — 37 25 30 5 14 12 — 50 tRAD 5 14 12 — 45 RAS to Column Address Delay Time 5 11 9 35 ns ns ns Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 7 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Column Address Hold Time tCAH 7 — 10 — 13 — ns Column Address to RAS Lead Time tRAL 25 — 30 — 35 — ns 5 6 6/17 ¡ Semiconductor MSM51V17805D/DSL AC Characteristics (2/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13 Parameter Symbol MSM51V17805MSM51V17805 MSM51V17805 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. Min. Max. Min. Max. Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 9 Read Command Hold Time referenced to RAS Write Command Set-up Time tRRH tWCS 0 0 — — 0 0 — — 0 0 — — ns ns 9 10 Write Command Hold Time tWCH 7 — 10 — 13 — ns Write Command Pulse Width tWP 7 — 10 — 10 — ns WE Pulse Width (DQ Disable) tWPE 7 — 10 — 10 — ns OE Command Hold Time tOEH 7 — 10 — 13 OE Precharge Time tOEP 7 — 10 — 10 — — ns ns OE Command Hold Time tOCH 7 — 10 — 10 — ns Write Command to RAS Lead Time tRWL 7 — 10 — 13 Write Command to CAS Lead Time tCWL 7 0 — — 10 0 — — 13 0 — — ns ns — ns 11 — — — — — 10 15 34 49 79 — — — — — 13 20 44 59 94 — — — — — ns ns ns ns ns 11 10 Data-in Set-up Time tDS Data-in Hold Time OE to Data-in Delay Time tDH tOED CAS to WE Delay Time Column Address to WE Delay Time tCWD tAWD RAS to WE Delay Time tRWD 7 13 30 42 67 CAS Precharge WE Delay Time 10 10 10 tCPWD 47 — 54 — 64 — ns CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tCSR tCHR 5 10 — — 5 10 — — 5 10 — — ns ns WE to RAS Precharge Time (CAS before RAS) tWRP — — — — 10 10 10 10 — 10 10 10 10 — — — — ns ns tWTS tWTH 10 10 10 10 tRASS 100 — 100 — 100 — ms 14 tRPS 90 — 110 — 130 — ns 14 tCHS –50 — –50 — –50 — ns 14 WE Hold Time from RAS (CAS before RAS) tWRH RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) — — — ns ns 7/17 ¡ Semiconductor Notes: MSM51V17805D/DSL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 14. Only SL version. 8/17 E2G0102-17-41O ,, , , , ,,,, ,, ¡ Semiconductor MSM51V17805D/DSL TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH – VIL – tCRP tCSH tCRP CAS tRCD VIH – VIL – tRAD tASR Address VIH – VIL – tRSH tCAS tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tREZ tOEA VIH – VIL – tCAC tRAC DQ VOH – tOEZ Open VOL – tRCH tRRH tCEZ Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tCRP tCRP CAS VIH – VIL – VIH – VIL – tASC Row tCAS tCAH tRAL Column tWCS WE tRSH tRAD tRAH tASR Address tCSH tRCD VIH – VIL – tWCH tWP tCWL tRWL VIH – OE VIL – tDS DQ VIH – VIL – tDH Valid Data-in Open "H" or "L" 9/17 ,,, ¡ Semiconductor MSM51V17805D/DSL Read Modify Write Cycle tRWC tRAS VIH – RAS VIL – tRCD tRSH tCAS VIH – VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tOEA tOED tCAC VI/OH– VI/OL– tCWL tRWL tWP tCWD tAWD tRCS tRAC DQ tCRP tCSH tCRP CAS tRP tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/17 ,, ,, , , ¡ Semiconductor MSM51V17805D/DSL Fast Page Mode Read Cycle (Part-1) tRASP RAS VIH – VIL – tRHCP tCRP CAS VIH VIL WE VIH – VIL – tCP tCP tCAS tCAS tCAS tRAD tASR VIH – VIL – tHPC tRCD – – Address tRP tASC tRAH Row tCSH tCAH tASC Column tASC tCAH Column Column tRCS tRRH tCHO DQ tOCH tRAC tAA OE tCAH tOEP tAA VIH – VIL – tCPA tOEA tCAC VOH – VOL – tOEZ tCAC Valid Data-out Valid Data-out tCLZ tOEA tOEA tCAC tDOH tOEP tAA tOEZ Valid* Data-out * : Same Data, tREZ Valid* Data-out "H" or "L" Fast Page Mode Read Cycle (Part-2) tRASP RAS VIH – VIL – tRHCP WE OE DQ VIH – VIL – VIH – VIL – tCP tRAH tCSH tASC tCAH Row tASC Column tCAH Column tRCS tCAS tASC tCAH Column tRCS tRAC tAA VIH – VIL – VOH – VOL – tCP tCAS tRAD tASR Address tRCD tCAS VIH – VIL – tCRP tHPC tCRP CAS tRP tRCH tWPE tAA tAA tCPA tOEA tCAC tCLZ tWEZ Valid Data-out tCAC tDOH tCAC Valid Data-out tCEZ Valid Data-out "H" or "L" 11/17 , ,, , , ¡ Semiconductor MSM51V17805D/DSL Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS VIH – VIL – CAS tRAD tRAH tASR VIH – VIL – WE VIH – VIL – OE VIH – VIL – tASC Column tWCS VIH – VIL – tCAS tCAH tWCS tDH Valid Data-in Column tWCH tDS tRSH tCAH tASC Column tWCH tDS DQ tCP tCAS tCSH tASC tCAH Row tHPC tCP tCAS VIH – VIL – Address tHPC tRCD tCRP tDH Valid Data-in tWCS tWCH tDS tDH Valid Data-in "H" or "L" Fast Page Mode Read Modify Write Cycle tRASP RAS tRWD VIH – VIL – tCRP CAS VIH – VIL – VIH – VIL – tCWD tRAD tASR Address tCP tRCD Row tCWL tCAH tRCS tAWD VIH – VIL – tAWD tDS tWP VIH – VIL – tCAC VI/OH – VI/OL – tOED tOEZ Valid Data-out tCLZ tRWL tCWD tRAC tOEA DQ tCPA tCAH Column tAA OE tASC Column tRCS WE tCPWD tHPRWC tRAH tASC tAA tOEH tDS tOED tOEA tCAC tDH Valid Data-in tOEZ Valid Data-out tCLZ tWP tOEH tDH Valid Data-in "H" or "L" 12/17 :FMNOPQRSK]^_ ¡ Semiconductor MSM51V17805D/DSL RAS-Only Refresh Cycle t RC tRP tRAS RAS V IH – V IL – tRPC tCRP CAS V IH – V IL – tRAH tASR Address V IH – V IL – Row tCEZ DQ V OH – V OL – Open Note: WE, OE = "H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC t RP RAS tRP tRAS VIH – VIL – t RPC tRPC tCP CAS tCSR tCHR tWRP tWRH VIH – VIL – WE VIH – VIL – DQ VOH – VOL – tWRP t CEZ Open Note: OE, Address = "H" or "L" "H" or "L" 13/17 , ,, ,, , ,, ¡ Semiconductor MSM51V17805D/DSL Hidden Refresh Read Cycle tRC tRAS RAS VIH – VIL – CAS VIH – VIL – Address VIH – VIL – tCRP tASR WE OE tRSH tRCD tRAD tASC tRRH tRAL VIH – VIL – tAA tROH tOEA VIH – VIL – VOH – VOL – tCHR Column tRCS tRAC DQ tRP tCAH tRAH Row tRC tRAS tRP tCEZ tCAC tCLZ tOEZ Open tREZ Valid Data-out "H" or "L" Hidden Refresh Write Cycle tRC tRAS RAS CAS Address VIH – VIL – VIH – VIL – VIH – VIL – tCRP tASR tRCD tRAD tASC tRAH VIH – VIL – OE VIH – VIL – DQ VIH – VIL – tRSH tCAH tRP tCHR tRAL Column Row tWCS WE tRC tRAS tRP tRWL tWCH tWP tDS tDH Valid Data-in "H" or "L" 14/17 FOPQRS\]^_KLM ¡ Semiconductor MSM51V17805D/DSL CAS before RAS Self-Refresh Cycle tRC tRP RAS CAS VIH – VIL – t RPC tCP VIH – VIL – WE VIH – VIL – DQ VOH – VOL – tRAS tCSR tCHR tWTS tWTH t OFF Open Note: OE, Address = "H" or "L" Only SL version "H" or "L" , Test Mode Initiate Cycle tRC tRP RAS VIH – VIL – tRPC tCP CAS tRAS tCSR VIH – VIL – tWTS WE tCHR tWTH VIH – VIL – tOFF DQ VOH – VOL – Open Note: OE, Address = "H" or "L" "H" or "L" 15/17 ¡ Semiconductor MSM51V17805D/DSL PACKAGE DIMENSIONS (Unit : mm) SOJ28-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/17 ¡ Semiconductor MSM51V17805D/DSL (Unit : mm) TSOPII28-P-400-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.51 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17