LANSDALE MC144110P Digital-to-analog converters with serial interface Datasheet

ML144110
ML144111
Digital–to–Analog Converters
with Serial Interface
CMOS LSI
Legacy Device: Motorola/Freescale MC144110, MC144111
The ML144110 and ML144111 are low–cost 6–bit D/A converters with
serial interface ports to provide communication with CMOS microprocessors and microcomputers. The ML144110 contains six static D/A converters; the ML144111 contains four converters.
Due to a unique feature of these DACs, the user is permitted easy scaling
of the analog outputs of a system. Over a 5 to 15 V supply range, these
DACs maybe directly interfaced to CMOS MPUs operating at 5 V.
•
•
•
•
•
•
•
•
Direct R–2R Network Outputs
Buffered Emitter–Follower Outputs
Serial Data Input
Digital Data Output Facilitates Cascading
Direct Interface to CMOS µP
Wide Operating Voltage Range: 4.5 to 15 V
Wide Operating Temperature Range: TA = 0 to 85°C
Software Information is Contained in Document M68HC11RM/AD
MC144110
P DIP 18 = VP
PLASTIC DIP
CASE 707
18
1
SO 20W = -6P
SOG PACKAGE
CASE 751D
20
1
MC144111
P DIP 14 = CP
PLASTIC DIP
CASE 646
14
BLOCK DIAGRAM
VDD
1
Qn Rn
R1 OUT OUT OUT
Q1 OUT
SO 16W = -5P
SOG PACKAGE
CASE 751G
16
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 18
MC144110P
ML144110VP
SO 20W
MC144110DW
ML144110-6P
P DIP 14
MC144111P
ML144111CP
SO 16W
MC144111DW
ML144111-5P
2R
2R
R
R
R
R
R
2R
2R
2R
2R
2R
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
HEX BUFFER (INVERTING)
C
ENB
CLK
C
*
D Q
Din
HEX LATCH
C
D
6–BIT SHIFT REGISTER
Dout
* Transparent Latch
Page 1 of 8
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Issue A
ML144110, ML144111
LANSDALE Semiconductor, Inc.
PIN ASSIGNMENTS
ML144110VP
ML144110-6P
Din
1
18
VDD
Din
1
20
VDD
Q1 Out
2
17
Dout
Q1 Out
2
19
Dout
R1 Out
3
16
R6 Out
R1 Out
3
18
R6 Out
Q2 Out
4
15
Q6 Out
Q2 Out
4
17
Q6 Out
R2 Out
5
14
R5 Out
R2 Out
5
16
R5 Out
Q3 Out
6
13
Q5 Out
Q3 Out
6
15
Q5 Out
R3 Out
7
12
R4 Out
R3 Out
7
14
R4 Out
ENB
8
11
Q4 Out
ENB
8
13
Q4 Out
VSS
9
10
CLK
VSS
9
12
CLK
10
11
NC
NC
ML144111CP
ML144111-5P
Din
1
14
VDD
Din
1
16
VDD
Q1 Out
2
13
Dout
Q1 Out
2
15
Dout
R1 Out
3
12
R4 Out
R1 Out
3
14
R4 Out
Q2 Out
4
11
Q4 Out
Q2 Out
4
13
Q4 Out
R2 Out
5
12
R3 Out
R2 Out
5
10
R3 Out
ENB
6
9
Q3 Out
ENB
6
11
Q3 Out
VSS
7
8
CLK
VSS
7
10
CLK
NC
8
9
NC
NC = NO CONNECTION
Page 2 of 8
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Issue A
ML144110, ML144111
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS* (Voltages referenced to VSS)
Parameter
Symbol
Value
Unit
VDD
– 0.5 to + 18
V
Vin
– 0.5 to VDD + 0.5
V
I
± 10
DC Supply Voltage
Input Voltage, All Inputs
DC Input Current, per Pin
Power Dissipation (Per Output)
TA = 70°C, MC144110
MC144111
TA = 85°C, MC144110
MC144111
mA
POH
mW
30
50
10
20
Power Dissipation (Per Package)
TA = 70°C, MC144110
MC144111
TA = 85°C, MC144110
MC144111
PD
Storage Temperature Range
Tstg
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields; however, it is advised that precautions be taken to avoid
application of voltage higher than maximum
rated voltages to this high–impedance circuit.
For proper operation it is recommended that
Vin and Vout be constrained to the range VSS ≤
(Vin or Vout) ≤VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD).
mW
100
150
25
50
– 65 to + 150
°C
* Maximum Ratings are those values beyond which damage to the device may occur.
ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS, TA = 0 to 85°C unless otherwise indicated)
VDD
Min
Max
Unit
VIH
High–Level Input Voltage (Din, ENB, CLK)
5
10
15
3.0
3.5
4
—
—
—
V
VIL
Low–Level Input Voltage (Din, ENB, CLK)
5
10
15
—
—
—
0.8
0.8
0.8
V
IOH
High–Level Output Current (Dout)
Vout = VDD – 0.5 V
5
– 200
—
µA
IOL
Low–Level Output Current (Dout)
Vout = 0.5 V
5
200
—
µA
IDD
Quiescent Supply Current
Iout = 0 µA
15
15
—
—
12
8
mA
Input Leakage Current (Din, ENB, CLK)
Vin = VDD or 0 V
15
—
±1
µA
Vnonl
Nonlinearity Voltage (Rn Out)
See Figure 1
5
10
15
—
—
—
100
200
300
mV
Vstep
Step Size (Rn Out)
See Figure 2
5
10
15
19
39
58
137
274
411
mV
Voffset
Offset Voltage from VSS
Din = $00, See Figure 1
—
—
1
LSB
IE
Emitter Leakage Current
VRn Out = 0 V
15
—
10
µA
hFE
DC Current Gain
IE = 0.1 to 10.0 mA
TA = 25°C
—
40
—
—
VBE
Base–to–Emitter Voltage Drop
IE = 1.0 mA
—
0.4
0.7
V
Symbol
Iin
Page 3 of 8
Parameter
Test Conditions
ML144110
ML144111
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Issue A
ML144110, ML144111
LANSDALE Semiconductor, Inc.
SWITCHING CHARACTERISTICS
(Voltages referenced to VSS, TA = 0 to 85°C, CL = 50 pF, Input tr = tf = 20 ns unless otherwise indicated)
Symbol
Parameter
VDD
Min
Max
Unit
twH
Positive Pule Width, CLK (Figures 3 and 4)
5
10
15
2
1.5
1
—
—
—
µs
twL
Negative Pulse Width, CLK (Figure 3 and 4)
5
10
15
5
3.5
2
—
—
—
µs
tsu
Setup Time, ENB to CLK (Figures 3 and 4)
5
10
15
5
3.5
2
—
—
—
µs
tsu
Setup Time, Din to CLK (Figures 3 and 4)
5
10
15
1000
750
500
—
—
—
ns
th
Hold Time, CLK to ENB (Figures 3 and 4)
5
10
15
5
3.5
2
—
—
—
µs
th
Hold Time, CLK to Din (Figures 3 and 4)
5
10
15
5
3.5
2
—
—
—
µs
Input Rise and Fall Times
5 – 15
—
2
µs
Cin
Input Capacitance
5 – 15
—
7.5
pF
OUTPUT VOLTAGE @ Rn Out, % (VDD – VSS )
tr, tf
100
75
Vnonl
ACTUAL
50
IDEAL
25
Voffset
0
0
$00
15
$0F
31
$1F
47
$2F
63
$3F
PROGRAM STEP
LINEARITY ERROR (integral linearity). A measure of how
straight a device’s transfer function is, it indicates the worst–case
deviation of linearity of the actual transfer function from the best–
fit straight line. It is normally specified in parts of an LSB.
Figure 1. D/A Transfer Function
Page 4 of 8
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Issue A
ML144110, ML144111
LANSDALE Semiconductor, Inc.
VRn OUT
STEP
SIZE
Step Size =
VDD ± 0.75 VDD
64
64
(For any adjacent pair of digital numbers)
DIGITAL NUMBER
Figure 2. Definition of Step Size
ENB
50%
tsu
CLK
th
50%
C1
C2
twH
twL
D1
Din
CN
D2
DN
th
tsu
Figure 3. Serial Input, Positive Clock
ENB
tsu
th
CLK
C1
twL
Din
C2
CN
twH
D1
D2
tsu
DN
th
Figure 4. Serial Input, Negative Clock
Page 5 of 8
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Issue A
ML144110, ML144111
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
INPUTS
Din
Data Input
Six–bit words are entered serially, MSB first, into digital
data input, Din. Six words are loaded into the ML144110 during each D/A cycle; four words are loaded into the ML144111.
The last 6–bit word shifted in determines the output level of
pins Q1 Out and R1 Out. The next–to–last 6–bit word affects
pins Q2 Out and R2 Out, etc.
ENB
Negative Logic Enable
The ENB pin must be low (active) during the serial load. On
the low–to–high transition of ENB, data contained in the shift
register is loaded into the latch.
CLK
Shift Register Clock
Data is shifted into the register on the high–to–low transition of CLK. CLK is fed into the D–input of a transparent
latch, which is used for inhibiting the clocking of the shift register when ENB is high.
The number of clock cycles required for the ML144110 is
usually 36. The ML144111 usually uses 24 cycles. SeeTable 1
for additional information.
OUTPUTS
Dout
Data Output
The digital data output is primarily used for cascading the
DACs and may be fed into Din of the next stage.
R1 Out through Rn Out
Resistor Network Outputs
These are the R–2R resistor network outputs. These outputs
may be fed to high–impedance input FET op amps to bypass
the on–chip bipolar transistors. The R value of the resistor network ranges from 7 to 15 kΩ.
Q1 Out through Qn Out
NPN Transistor Outputs
Buffered DAC outputs utilize an emitter–follower configuration for current–gain, thereby allowing interface to low–impedance circuits.
SUPPLY PINS
VSS
Negative Supply Voltage
This pin is usually ground.
VDD
Positive Supply Voltage
The voltage applied to this pin is used to scale the analog
output swing from 4.5 to 15 V p–p.
Table 1. Number of Channels vs Clocks Required
Number of
Channels
Required
Page 6 of 8
Number of
Clock Cycles
Outputs Used on ML144110
Outputs Used on ML144111
1
6
Q1/R1
Q1/R1
2
12
Q1/R1, Q2/R2
Q1/R1, Q2/R2
3
18
Q1/R1, Q2/R2, Q3/R3
Q1/R1, Q2/R2, Q3/R3
4
24
Q1/R1, Q2/R2, Q3/R3, Q4/R4
Q1/R1, Q2/R2, Q3/R3, Q4/R4
5
30
Q1/R1, Q2/R2, Q3/R3, Q4/R4, Q5/R5
Not Applicable
6
36
Q1/R1, Q2/R2, Q3/R3, Q4/R4, Q5/R5, Q6/R6
Not Applicable
www.lansdale.com
Issue A
ML144110, ML144111
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 18 = VP
(ML144110VP)
PLASTIC DIP
CASE 707–02
18
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
10
B
1
9
A
L
C
K
N
F
H
D
J
M
SEATING
PLANE
G
DIM
A
B
C
D
F
G
H
J
K
L
M
N
SO 20W = -6P
(ML144110-6P)
SOG PACKAGE
CASE 751D–04
–A–
20
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R
C
–T–
18X
Page 7 of 8
G
K
SEATING
PLANE
INCHES
MIN
MAX
0.875 0.915
0.240 0.260
0.140 0.180
0.014 0.022
0.050 0.070
0.100 BSC
0.040 0.060
0.008 0.012
0.115 0.135
0.300 BSC
0°
15°
0.020 0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
11
–B–
MILLIMETERS
MIN
MAX
22.22 23.24
6.10
6.60
3.56
4.57
0.36
0.56
1.27
1.78
2.54 BSC
1.02
1.52
0.20
0.30
2.92
3.43
7.62 BSC
15°
0°
0.51
1.02
X 45
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0
7
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0
7
0.395
0.415
0.010
0.029
M
www.lansdale.com
Issue A
ML144110, ML144111
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 14 = CP
(ML144111CP)
PLASTIC DIP
CASE 646–06
14
8
1
7
B
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0
10
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0
10
0.39
1.01
SO 16W = -5P
(ML144111-5P)
SOG PACKAGE
CASE 751G–02
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0
7
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0
7
0.395
0.415
0.010
0.029
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 8 of 8
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Issue A
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