Fairchild CD4013BCSJ Dual d-type flip-flop Datasheet

Revised January 1999
CD4013BC
Dual D-Type Flip-Flop
General Description
Features
The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent data, set, reset, and clock inputs
and “Q” and “Q” outputs. These devices can be used for
shift register applications, and by connecting “Q” output to
the data input, for counter and toggle applications. The
logic level present at the “D” input is transferred to the Q
output during the positive-going transition of the clock
pulse. Setting or resetting is independent of the clock and
is accomplished by a high level on the set or reset line
respectively.
■ Wide supply voltage range:
■ High noise immunity:
3.0V to 15V
0.45 VDD (typ.)
■ Low power TTL: fan out of 2 driving 74L
compatibility:
or 1 driving 74LS
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm system
• Industrial electronics
• Remote metering
• Computers
Ordering Code:
Order Number
Package Number
Package Description
CD4013BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4013BCSJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4013BCN
N14A
14-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC and SOP
CL
(Note 1)
D
R
S
Q
Q
0
0
0
0
1
1
0
0
1
0
x
0
0
Q
Q
x
x
1
0
0
1
x
x
0
1
1
0
x
x
1
1
1
1
No Change
x = Don't Care Case
Note 1: Level Change
Top View
© 1999 Fairchild Semiconductor Corporation
DS005946.prf
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CD4013BC Dual D-Type Flip-Flop
October 1987
CD4013BC
Schematic Diagrams
Logic Diagram
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2
Recommended Operating
Conditions (Note 3)
DC Supply Voltage (VDD)
Input Voltage (VIN)
−0.5 VDC to +18 VDC
Input Voltage (VIN)
−65°C to +150°C
Storage Temperature Range (TS)
700 mW
Small Outline
500 mW
Symbol
IDD
VOL
Parameter
VIH
IOL
IIN
Min
Max
+25°C
Min
Typ
+85°C
Max
Min
Max
Units
VDD = 5V, VIN = VDD or VSS
4.0
4.0
30
VDD = 10V, VIN = VDD or VSS
8.0
8.0
60
µA
VDD = 15V, VIN = VDD or VSS
16.0
16.0
120
µA
LOW Level
HIGH Level
µA
|IO| < 1.0 µA
VDD = 5V
0.05
0.05
0.05
V
VDD = 10V
0.05
0.05
0.05
V
VDD = 15V
0.05
0.05
0.05
V
|IO| < 1.0 µA
VDD = 5V
4.95
4.95
4.95
V
VDD = 10V
9.95
9.95
9.95
V
VDD = 15V
14.95
14.95
14.95
V
LOW Level
|IO| < 1.0 µA
Input Voltage
VDD = 5V, VO = 0.5V or 4.5V
1.5
1.5
1.5
VDD = 10V, VO = 1.0V or 9.0V
3.0
3.0
3.0
V
VDD = 15V, VO = 1.5V or 13.5V
4.0
4.0
4.0
V
V
HIGH Level
|IO| < 1.0 µA
Input Voltage
VDD = 5V, VO = 0.5V or 4.5V
3.5
3.5
3.5
V
VDD = 10V, VO = 1.0V or 9.0V
7.0
7.0
7.0
V
VDD = 15V, VO = 1.5V or 13.5V
11.0
11.0
11.0
V
VDD = 5V, VO = 0.4V
0.52
0.44
0.88
0.36
mA
LOW Level Output
VDD = 10V, VO = 0.5V
1.3
1.1
2.25
0.9
mA
VDD = 15V, VO = 1.5V
3.6
3.0
8.8
2.4
mA
HIGH Level Output
VDD = 5V, VO = 4.6V
−0.52
−0.44
−0.88
−0.36
mA
Current (Note 4)
VDD = 10V, VO = 9.5V
−1.3
−1.1
−2.25
−0.9
mA
VDD = 15V, VO = 13.5V
−3.6
Input Current
VDD = 15V, VIN = 0V
−0.3
−10−5
−0.3
−1.0
µA
VDD = 15V, VIN = 15V
0.3
10−5
0.3
1.0
µA
Current (Note 4)
IOH
−40°C
Conditions
Current
Output Voltage
VIL
(Note 3)
Quiescent Device
Output Voltage
VOH
Note 3: VSS = 0V unless otherwise specified.
260°C
DC Electrical Characteristics
−40°C to +85°C
Note 2: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation.
Lead Temperature (TL)
(Soldering, 10 seconds)
0 VDC to VDD VDC
Operating Temperature Range (TA)
Power Dissipation (PD)
Dual-In-Line
+3 VDC to +15 VDC
DC Supply Voltage (VDD)
−0.5 VDC to VDD +0.5 VDC
−3.0
−8.8
−2.4
mA
Note 4: IOH and IOL are measured one output at a time.
3
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CD4013BC
Absolute Maximum Ratings(Note 2)
(Note 3)
CD4013BC
AC Electrical Characteristics
(Note 5)
TA = 25°C, CL = 50 pF, RL = 200k, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CLOCK OPERATION
tPHL, tPLH
tTHL, tTLH
tWL, tWH
tRCL, tFCL
tSU
fCL
VDD = 5V
200
350
ns
VDD = 10V
80
160
ns
VDD = 15V
65
120
ns
VDD = 5V
100
200
ns
VDD = 10V
50
100
ns
VDD = 15V
40
80
ns
Minimum Clock
VDD = 5V
100
200
ns
Pulse Width
VDD = 10V
40
80
ns
VDD = 15V
32
65
ns
Propagation Delay Time
Transition Time
Maximum Clock Rise and
VDD = 5V
15
µs
Fall Time
VDD = 10V
10
µs
VDD = 15V
5
µs
Minimum Set-Up Time
VDD = 5V
20
40
ns
VDD = 10V
15
30
ns
VDD = 15V
12
25
ns
Maximum Clock
VDD = 5V
2.5
5
MHz
Frequency
VDD = 10V
6.2
12.5
MHz
VDD = 15V
7.6
15.5
MHz
SET AND RESET OPERATION
tPHL(R),
Propagation Delay Time
tPLH(S)
VDD = 5V
150
300
ns
VDD = 10V
65
130
ns
VDD = 15V
45
90
ns
tWH(R),
Minimum Set and
VDD = 5V
90
180
ns
tWH(S)
Reset Pulse Width
VDD = 10V
40
80
ns
VDD = 15V
25
50
ns
Any Input
5
7.5
pF
CIN
Average Input Capacitance
Note 5: AC Parameters are guaranteed by DC correlated testing.
Switching Time Waveforms
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4
CD4013BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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CD4013BC Dual D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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