IDT IDT71124S20Y Cmos static ram 1 meg (128k x 8-bit) revolutionary pinout Datasheet

IDT71124
CMOS Static RAM
1 Meg (128K x 8-Bit)
Revolutionary Pinout
Description
Features
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The IDT71124 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using IDT’s high-performance,
high-reliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a costeffective solution for high-speed memory needs. The JEDEC
centerpower/GND pinout reduces noise generation and improves
system performance.
The IDT71124 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71124 are TTL-compatible
and operation is from a single 5V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
The IDT71124 is packaged in a 32-pin 400 mil Plastic SOJ.
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise.
Equal access and cycle times
– Commercial and Industrial: 12/15/20ns
One Chip Select plus one Output Enable pin
Bidirectional inputs and outputs directly TTL-compatible
Low power consumption via chip deselect
Available in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A0
•
•
•
ADDRESS
DECODER
•
•
•
1,048,576-BIT
MEMORY ARRAY
A16
I/O0 - I/O7
8
•
I/O CONTROL
8
,
8
WE
OE
CS
CONTROL
LOGIC
3514 drw 01
FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-3514/10
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Pin Configuration
Absolute Maximum Ratings(1)
Symbol
A0
A1
A2
A3
CS
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
1
32
2
31
3
30
4
29
5
28
6 SO32-3 27
7
26
8
25
9
24
23
10
22
11
21
12
13
20
14
19
15
18
16
17
,
Rating
Value
Unit
V
VTERM (2)
Terminal Voltage with
Respect to GND
-0.5 to +7.0(2)
TA
Operating Temperature
0 to +70
o
C
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-55 to +125
o
C
PT
Power Dissipation
1.25
W
IOUT
DC Output Current
50
mA
3514 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliabilty.
2. VTERM must not exceed Vcc + 0.5V.
3514 drw 02
SOJ
Top View
Capacitance
(TA = +25°C, f = 1.0MHz)
CS
OE
WE
I/O
L
L
H
DATAOUT
Read Data
L
X
L
DATAIN
Write Data
L
H
H
High-Z
Output Disabled
H
X
X
High-Z
Deselected - Standby (I SB)
VHC(3)
X
X
High-Z
Deselected - Standby (I SB1)
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VCC -0.2V.
3. Other inputs ≥ VHC or ≤ VLC.
Parameter(1)
Symbol
Truth Table(1,2)
Function
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 3dV
8
pF
VOUT = 3dV
8
pF
3514 tbl 03
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
3514 tbl 01
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature
GND
VCC
Commercial
0°C to +70°C
0V
5.0V ± 10%
Industrial
–40°C to +85°C
0V
5.0V ± 10%
3514 tbl 04
Recommended DC Operating
Conditions
Symbol
Parameter
VCC
Supply Voltage
GND
Ground
VIH
VIL
Input High Voltage
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
VCC +0.5
V
____
0.8
-0.5
(1)
V
3514 tbl 05
6.42
2
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
Symbol
|ILI|
|ILO|
Parameter
Test Conditions
Min.
Max.
Unit
Input Leakage Current
VCC = Max., VIN = GND to VCC
___
5
µA
Output Leakage Current
VCC = Max., CS = VIH, VOUT = GND to VCC
___
5
µA
___
0.4
V
2.4
___
V
VOL
Output Low Voltage
IOL = 8mA, VCC = Min.
VOH
Output High Voltage
IOH = –4mA, VCC = Min.
3514 tbl 06
DC Electrical Characteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)
71124S12
Symbol
Parameter
71124S15
71124S20
Com'l.
Ind.
Com'l.
Ind.
Com'l.
Ind.
Unit
ICC
Dynamic Operating Current
CS < VIL, Outputs Open, VCC = Max., f = fMAX(2)
160
160
155
155
140
140
mA
ISB
Standby Power Supply Current (TTL Level)
CS > VIH, Outputs Open, VCC = Max., f = fMAX(2)
40
40
40
40
40
40
mA
ISB1
Full Standby Power Supply Current (CMOS Level)
CS > VHC, Outputs Open, VCC = Max., f = 0(2)
VIN < VLC or VIN > VHC
10
10
10
10
10
10
mA
3514 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figure 1 and 2
3514 tbl 08
AC Test Loads
5V
5V
480Ω
480Ω
DATA OUT
DATA OUT
30pF
255Ω
.
5pF*
255Ω
3514 drw 04
3514 drw 03
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
6.42
3
.
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71124S12
Sym bol
Param eter
71124S15
71124S20
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Re ad Cyc le Tim e
12
____
15
____
20
____
ns
tAA
A d d re ss A cc e ss Tim e
____
12
____
15
____
20
ns
tACS
Chip S e le ct A cc e ss Tim e
____
12
____
15
____
20
ns
tCLZ(1)
Chip Se le c t to Outp ut in Lo w-Z
3
____
3
____
3
____
ns
tCHZ
Chip De se le c t to Outp ut in Hig h-Z
0
6
0
7
0
8
ns
tOE
Outp ut E nab le to Outp ut Valid
____
6
____
7
____
8
ns
tOLZ(1)
Outp ut E nab l e to Outp ut in Lo w-Z
0
____
0
____
0
____
ns
tOHZ(1)
Outp ut Disab le to O utp ut in Hig h-Z
0
5
0
5
0
7
ns
4
____
4
____
ns
(1)
tOH
Outp ut Ho ld fro m A d d re ss Chang e
4
____
tPU(1)
Chip S e le ct to P o we r-Up Tim e
0
____
0
____
0
____
ns
tPD(1)
Chip De s e le c t to P o we r-Do wn Tim e
____
12
____
15
____
20
ns
Write Cy c le Tim e
12
____
15
____
20
____
ns
8
____
12
____
15
____
ns
8
____
12
____
15
____
ns
0
____
0
____
0
____
ns
8
____
12
____
15
____
ns
0
____
0
____
0
____
ns
6
____
8
____
9
____
ns
0
____
0
____
0
____
ns
3
____
4
____
ns
0
5
0
8
WRITE CYCLE
tWC
tAW
A d d re ss V alid to End o f W rite
tCW
Chip S e le c t to E nd o f W rite
tAS
A d d re ss S e t-up Tim e
tWP
Write Pulse W id th
tWR
Write Re co v e ry Tim e
tDW
Data Valid to E nd -o f-Write
tDH
Data Ho ld Tim e
(1)
tOW
Outp ut active fro m End -o f-Write
3
____
tWHZ(1)
W rite E nab le to Outp ut in Hig h-Z
0
5
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42
4
ns
3514 tbl 09
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
tAA
OE
tOE
CS
tOLZ
tCLZ
DATAOUT
VCC SUPPLY ICC
CURRENT ISB
(5)
(5)
tACS
(3)
tCHZ
HIGH IMPEDANCE
(5)
tOHZ (5)
.
DATAOUT VALID
tPD
tPU
3514 drw 05
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC
ADDRESS
tAA
tOH
DATAOUT
tOH
PREVIOUS DATAOUT VALID
.
DATAOUT VALID
3514 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
5
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
tAW
CS
tWR
tAS
tWP
(2)
.
WE
tWHZ
(5)
tOW
(5)
HIGH IMPEDANCE
(3)
DATAOUT
(3)
tDH
tDW
DATAIN
tCHZ (5)
DATAIN VALID
3514 drw 07
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
tAS
tCW
tWR
.
WE
tDW
tDH
DATAIN VALID
DATAIN
3514 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period.
5. Transition is measured ±200mV from steady state.
6.42
6
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Ordering Information
IDT
71124
S
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
I
Industrial (–40°C to +85°C)
Y
400-mil SOJ (SO32-3)
12
15
20
Speed in nanoseconds
3514 drw 09
6.42
7
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Datasheet Document History
8/5/99
8/13/99
9/30/99
2/18/00
3/14/00
4/01/00
8/09/00
02/01/01
Pg. 3
Pg. 4
Pg. 6
Pg. 8
Pg. 1, 3, 4, 7
Pg. 3
Pg. 3
Pg.4
Updated to new format
Removed military entries on DC table
Removed Note 1 and renumbered footnotes
Revised footnotes on Write Cycle No. 1 diagram
Added Datasheet Document History
Added 12ns, 15ns, and 20ns industrial temperature speed grade offerings
Revise ISB for Industrial Temperature offerings to meet commerical specifications
Revised ISB to accomidate speed functionality
Tightened tAW, tCW, tWP and tDW within the AC Electrical Characteristics
Not recommended for new designs
Removed "Not recommended for new designs"
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6.42
8
for Tech Support:
[email protected]
800-544-7726, x4033
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