AD AD8354ACP-R2 100 mhz-2.7 ghz rf gain block Datasheet

100 MHz to 2.7 GHz
RF Gain Block
AD8354
FEATURES
Fixed Gain of 20 dB
Operational Frequency of 100 MHz to 2.7 GHz
Linear Output Power-Up to 4 dBm
Input/Output Internally Matched to 50 ⍀
Temperature and Power Supply Stable
Noise Figure 4.2 dB
Power Supply 3 V or 5 V
FUNCTIONAL BLOCK DIAGRAM
BIAS AND VREF
INPT
COM1
VPOS
VOUT
AD8354
COM2
APPLICATIONS
VCO Buffers
General Tx/Rx Amplification
Power Amplifier Predriver
Low Power Antenna Driver
GENERAL DESCRIPTION
The AD8354 is a broadband, fixed-gain linear amplifier that
operates at frequencies from 100 MHz up to 2.7 GHz. It is
intended for use in a wide variety of wireless devices including
cellular, broadband, CATV, and LMDS/MMDS applications.
By taking advantage of Analog Devices’ high performance
complementary Si bipolar process, these gain blocks provide
excellent stability over process, temperature, and power supply.
This amplifier is single-ended and internally matched to 50 Ω
with a return loss of greater than 10 dB over the full operating
frequency range.
The AD8354 provides linear output power of nearly 4.3 dBm
with 20 dB of gain at 900 MHz when biased at 3 V and an
external RF choke is connected between the power supply and
the output pin. The dc supply current is 24 mA. At 900 MHz,
the output third order intercept (OIP3) is greater than 18 dBm;
at 2.7 GHz, the OIP3 is 14 dBm.
The noise figure is 4.2 dB at 900 MHz. The reverse isolation
(S12) is –33 dB at 900 MHz.
The AD8354 can also operate with a 5 V power supply, in which
case no external inductor is required. Under these conditions,
the AD8354 delivers 4.8 dBm with 20 dB of gain at 900 MHz.
The dc supply current is 26 mA. At 900 MHz, the OIP3 is
greater than 19 dBm, and at 2.7 GHz, the OIP3 is 15 dBm.
The noise figure is 4.4 dB at 900 MHz. The reverse isolation
(S12) is –33 dB.
The AD8354 is fabricated on Analog Devices’ proprietary, high
performance 25 GHz Si complementary bipolar IC process. The
AD8354 is available in a chip scale package that utilizes an exposed
paddle for excellent thermal impedance and low impedance
electrical connection to ground. It operates over a –40°C to
+85°C temperature range.
An evaluation board is available.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
(V = 3 V, T = 25ⴗC, 100 nH external inductor between VOUT and VPOS, Z = 50 ⍀,
otherwise noted.)
AD8354–SPECIFICATIONS unless
S
Parameter
OVERALL FUNCTION
Frequency Range
Gain
A
O
Conditions
Min
Typ
Unit
2.7
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz, –40°C ≤ TA ≤ +85°C
f = 1.9 GHz, –40°C ≤ TA ≤ +85°C
f = 2.7 GHz, –40°C ≤ TA ≤ +85°C
VPOS ± 10%, f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
19.5
18.6
17.1
–0.97
–1.05
–1.33
0.54
0.37
0.2
–33.5
–38
–32.9
GHz
dB
dB
dB
dB
dB
dB
dB/V
dB/V
dB/V
dB
dB
dB
RF INPUT INTERFACE
Input Return Loss
Pin RFIN
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
24.4
23
12.7
dB
dB
dB
RF OUTPUT INTERFACE
Output Compression Point
Pin VOUT
f = 900 MHz, 1 dB compression
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz, –40°C ≤ TA ≤ +85°C
f = 1.9 GHz, –40°C ≤ TA ≤ +85°C
f = 2.7 GHz, –40°C ≤ TA ≤ +85°C
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
4.6
3.7
2.7
0.7
0.7
0.8
23.6
16.5
14.6
dBm
dBm
dBm
dB
dB
dB
dB
dB
dB
f = 900 MHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 1.9 GHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 2.7 GHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 900 MHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
19
16
14.2
29.7
4.2
4.8
5.4
dBm
dBm
dBm
dBm
dB
dB
dB
Delta Gain
Gain Supply Sensitivity
Reverse Isolation (S12)
Delta Compression Point
Output Return Loss
DISTORTION/NOISE
Output Third Order Intercept
Output Second Order Intercept
Noise Figure
POWER INTERFACE
Supply Voltage
Total Supply Current
Supply Voltage Sensitivity
Temperature Sensitivity
0.1
Max
Pin VPOS
2.7
16
–40°C ≤ TA ≤ +85°C
3
23
6.2
33
3.3
31
V
mA
mA/V
µA/°C
Specifications subject to change without notice.
–2–
REV. A
AD8354
SPECIFICATIONS
(VS = 5 V, TA = 25ⴗC, no external inductor between VOUT and VPOS, ZO = 50 ⍀, unless otherwise noted.)
Parameter
OVERALL FUNCTION
Frequency Range
Gain
Conditions
Min
Typ
Unit
2.7
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz, –40°C ≤ TA ≤ +85°C
f = 1.9 GHz, –40°C ≤ TA ≤ +85°C
f = 2.7 GHz, –40°C ≤ TA ≤ +85°C
VPOS ± 10%, f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
19.5
18.7
17.3
–0.93
–0.99
–1.21
0.32
0.21
0.08
–33.5
–37.6
–32.9
GHz
dB
dB
dB
dB
dB
dB
dB/V
dB/V
dB/V
dB
dB
dB
RF INPUT INTERFACE
Input Return Loss
Pin RFIN
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
24.4
23.9
13.5
dB
dB
dB
RF OUTPUT INTERFACE
Output 1 dB Compression
Pin VOUT
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz, –40°C ≤ TA ≤ +85°C
f = 1.9 GHz, –40°C ≤ TA ≤ +85°C
f = 2.7 GHz, –40°C ≤ TA ≤ +85°C
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
4.8
4.6
3.6
0.37
–0.14
–0.05
23.7
22.5
17.6
dBm
dBm
dBm
dB
dB
dB
dB
dB
dB
f = 900 MHz, ⌬f = 50 MHz, PIN = –30 dBm
f = 1.9 GHz, ⌬f = 50 MHz, PIN = –30 dBm
f = 2.7 GHz, ⌬f = 50 MHz, PIN = –30 dBm
f = 900 MHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
19.3
17.3
15.3
28.7
4.4
5
5.6
dBm
dBm
dBm
dBm
dB
dB
dB
Delta Gain
Gain Supply Sensitivity
Reverse Isolation (S12)
Delta Compression Point
Output Return Loss
DISTORTION/NOISE
Output Third Order Intercept
Output Second Order Intercept
Noise Figure
POWER INTERFACE
Supply Voltage
Total Supply Current
Supply Voltage Sensitivity
Temperature Sensitivity
0.1
Max
Pin VPOS
4.5
17
TA = 27°C
–40°C ≤ TA ≤ +85°C
Specifications subject to change without notice.
REV. A
–3–
5
25
4
28
5.5
34
V
mA
mA/V
µA/°C
AD8354
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Power (re: 50 Ω) . . . . . . . . . . . . . . . . . . . . . . . . 10 dBm
Equivalent Voltage . . . . . . . . . . . . . . . . . . . . . . 700 mV rms
Internal Power Dissipation
Paddle Not Soldered . . . . . . . . . . . . . . . . . . . . . . . . 325 mW
Paddle Soldered . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 mW
␪JA (Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . 200°C/W
␪JA (Paddle Soldered) . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 240°C
8
COM1
AD8354
7
VOUT
TOP VIEW
(Not to Scale)
6
VPOS
5
COM2
COM1 1
NC 2
INPT
3
COM2 4
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Pin No.
Mnemonic
Description
1, 8
COM1
Device Common. Connect to low
impedance ground.
2
NC
No Connection.
3
INPT
RF Input Connection. Must be
ac-coupled.
4, 5
COM2
Device Common. Connect to low
impedance ground.
6
VPOS
Positive Supply Voltage.
7
VOUT
RF Output Connection. Must be
ac-coupled.
ORDERING GUIDE
Model
AD8354ACP-R2
AD8354ACP-REEL7
AD8354-EVAL
Temperature
Range
Package
Description
Package
Option
Branding
–40°C to +85°C
–40°C to +85°C
8-Lead LFCSP
8-Lead LFCSP
Evaluation Board
CP-8
CP-8
JCA
JCA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8354 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. A
Typical Performance Characteristics–AD8354
90
90
120
120
60
150
150
30
330
210
0
330
210
300
240
30
180
0
180
60
300
240
270
270
TPC 1. S11 vs. Frequency, VS = 3 V, TA = 25 ⬚C,
100 MHz ≤ f ≤ 3.0 GHz
TPC 4. S22 vs. Frequency, VS = 3 V, TA = 25 ⬚C,
100 MHz ≤ f ≤ 3.0 GHz
25
25
GAIN AT 3.3V
GAIN AT –40ⴗC
20
20
GAIN AT 2.7V
GAIN AT 3.0V
GAIN (dB)
GAIN (dB)
15
10
5
GAIN AT +25ⴗC
GAIN AT +85ⴗC
10
5
0
0
500
1000
1500
2000
FREQUENCY (MHz)
2500
0
3000
–5
–5
–10
–10
REVERSE ISOLATION (dB)
0
–15
–20
–25
S12 AT 3.3V
S12 AT 2.7V
1500
2000
2500
3000
–15
–20
–25
S12 AT –40ⴗC
–30
S12 AT +25ⴗC
0
500
S12 AT +85ⴗC
S12 AT 3.0V
1000
1500
2000
2500
–40
3000
FREQUENCY (MHz)
TPC 3. Reverse Isolation vs. Frequency, VS = 2.7 V,
3 V, and 3.3 V, TA = 25 ⬚C
REV. A
1000
–35
–35
–40
500
TPC 5. Gain vs. Frequency, VS = 3 V, TA = –40 ⬚C,
+25 ⬚C, and +85 ⬚C
0
–30
0
FREQUENCY (MHz)
TPC 2. Gain vs. Frequency, VS = 2.7 V, 3.0 V, and
3.3 V, TA = 25 ⬚C
REVERSE ISOLATION (dB)
15
0
500
1000
1500
2000
FREQUENCY (MHz)
2500
3000
TPC 6. Reverse Isolation vs. Frequency, VS = 3 V,
TA = –40 ⬚C, +25 ⬚C, and +85 ⬚C
–5–
AD8354
6
7
P1 dB AT +85ⴗC
6
5
P1 dB AT 3.3V
5
P1 dB (dBm)
P1 dB (dBm)
4
4
3
P1 dB AT 3.0V
2
P1 dB AT +25ⴗC
3
P1 dB AT –40ⴗC
2
P1 dB AT 2.7V
1
1
0
0
–1
0
500
1000
1500
2000
2500
0
3000
1000
1500
2000
FREQUENCY (MHz)
500
FREQUENCY (MHz)
50
50
45
45
40
40
35
35
PERCENTAGE
PERCENTAGE
3000
TPC 10. P1 dB vs. Frequency, VS = 3 V, TA = –40 ⬚C,
+27 ⬚C, and +85 ⬚C
TPC 7. P1 dB vs. Frequency, VS = 2.7 V, 3 V, and 3.3 V,
TA = 27 ⬚C
30
25
20
30
25
20
15
15
10
10
5
5
0
2.5
2500
0
14.4
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
OUTPUT 1dB COMPRESSION POINT (dBm)
TPC 8. Distribution of P1 dB, VS = 3 V, TA = 25 ⬚C,
f = 2.2 GHz
14.6
14.8
15.0
15.2
15.4
OIP3 (dBm)
15.6
15.8
16.0
TPC 11. Distribution of OIP3, VS = 3 V, TA = 25 ⬚C,
f = 2.2 GHz
22
22
20
18
18
OIP3 (dBm)
OIP3 (dBm)
OIP3 AT 3.3V
20
16
OIP3 AT 3.0V
OIP3 AT +25ⴗC
16
OIP3 AT +85ⴗC
14
14
OIP3 AT 2.7V
12
12
10
10
OIP3 AT –40ⴗC
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
0
500
1000
1500
2000
FREQUENCY (MHz)
2500
3000
TPC 12. OIP3 vs. Frequency, VS = 3 V, TA = –40 ⬚C,
+25 ⬚C, and +85 ⬚C
TPC 9. OIP3 vs. Frequency, VS = 2.7 V, 3 V, and
3.3 V, TA = 25 ⬚C
–6–
REV. A
AD8354
6.5
6.0
5.8
6.0
5.6
NOISE FIGURE (dB)
NOISE FIGURE (dB)
5.4
5.2
5.0
NF AT 3.0V
4.8
NF AT 3.3V
4.6
5.5
5.0
NF AT +85ⴗC
4.5
NF AT +25ⴗC
4.0
NF AT –40ⴗC
4.4
3.5
4.2
NF AT 2.7V
4.0
3.0
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 13. Noise Figure vs. Frequency, VS = 2.7 V, 3 V,
and 3.3 V, TA = 25 ⬚C
2500
3000
TPC 16. Noise Figure vs. Frequency, VS = 3 V,
TA = –40 ⬚C, +25 ⬚C, and +85 ⬚C
40
30
IS AT 3.3V
35
25
SUPPLY CURRENT (mA)
30
PERCENTAGE
25
20
15
10
20
IS AT 2.7V
IS AT 3.0V
15
10
5
5
0
–60
0
4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
NOISE FIGURE (dB)
TPC 14. Distribution of Noise Figure, VS = 3 V,
TA = 25 ⬚C, f = 2.2 GHz
–40
–20
150
120
100
0
30
0
180
330
210
60
150
30
180
330
210
300
300
240
270
270
TPC 15. S11 vs. Frequency, VS = 5 V, TA = 25 ⬚C, 100
MHz ≤ f ≤ 3 GHz
REV. A
80
90
60
240
60
TPC 17. Supply Current vs. Temperature, VS = 2.7 V,
3 V, and 3.3 V
90
120
0
20
40
TEMPERATURE (ⴗC)
TPC 18. S22 vs. Frequency, VS = 5 V, TA = 25 ⬚C,
100 MHz ≤ f ≤ 3 GHz
–7–
AD8354
25
25
GAIN AT –40ⴗC
GAIN AT 5.5V
20
20
GAIN AT 5.0V
GAIN AT 4.5V
15
GAIN (dB)
GAIN (dB)
15
10
GAIN AT +25ⴗC
10
GAIN AT +85ⴗC
5
5
0
0
0
500
1000
1500
2000
2500
3000
0
500
2000
1000
1500
FREQUENCY (MHz)
FREQUENCY (MHz)
0
–5
–5
–10
–10
REVERSE ISOLATION (dB)
REVERSE ISOLATION (dB)
0
–15
–20
S12 AT 4.5V
S12 AT 5.0V
3000
TPC 22. Gain vs. Frequency, VS = 5 V, TA = –40 ⬚C,
+25 ⬚C, and +85 ⬚C
TPC 19. Gain vs. Frequency, VS = 4.5 V, 5.0 V, and
5.5 V, TA = 25 ⬚C
–25
2500
S12 AT 5.5V
–30
–35
–15
–20
S12 AT –40ⴗC
–25
S12 AT +85ⴗC
S12 AT +25ⴗC
–30
–35
–40
0
500
1500
2000
1000
FREQUENCY (MHz)
2500
–40
3000
0
TPC 20. Reverse Isolation vs. Frequency, VS = 4.5 V,
5 V, and 5.5 V, TA = 25 ⬚C
500
1000
1500
2000
FREQUENCY (MHz)
2500
3000
TPC 23. Reverse Isolation vs. Frequency, VS = 5 V,
TA = –40 ⬚C, +25 ⬚C, and +85 ⬚C
6
7
P1 dB AT +85ⴗC
6
P1 dB AT 5.5V
5
P1 dB AT –40ⴗC
5
P1 dB (dBm)
P1 dB (dBm)
4
4
P1 dB AT 5.0V
3
P1 dB AT 4.5V
P1 dB AT +25ⴗC
3
2
2
1
1
0
0
0
500
1000
1500
2000
FREQUENCY (MHz)
2500
3000
0
500
1000
1500
2000
FREQUENCY (MHz)
2500
3000
TPC 24. P1 dB vs. Frequency, VS = 5 V, TA = –40 ⬚C,
+25 ⬚C, and +85 ⬚C
TPC 21. P1 dB vs. Frequency, VS = 4.5 V, 5 V, and
5.5 V, TA = 25 ⬚C
–8–
REV. A
AD8354
50
35
45
30
40
25
PERCENTAGE
PERCENTAGE
35
30
25
20
15
20
15
10
10
5
5
0
3.95 4.00 4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 4.45 4.50
OUTPUT 1 dB COMPRESSION POINT (dBm)
0
16.0 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 17.0 17.1 17.2
OIP3 (dBm)
TPC 25. Distribution of P1 dB, VS = 5 V, TA = 25 ⬚C,
f = 2.2 GHz
TPC 28. Distribution of OIP3, VS = 5 V, TA = 25 ⬚C,
f = 2.2 GHz
22
22
20
20
18
18
OIP3 (dBm)
OIP3 (dBm)
OIP3 AT 5.5V
16
OIP3 AT 5.0V
OIP3 AT 4.5V
OIP3 AT +85ⴗC
OIP3 AT +25ⴗC
16
14
14
12
12
10
OIP3 AT –40ⴗC
10
0
500
1000
1500
2000
2500
3000
0
500
FREQUENCY (MHz)
1000
1500
2000
2500
3000
FREQUENCY (MHz)
TPC 29. OIP3 vs. Frequency, VS = 5 V, TA = –40 ⬚C,
+25 ⬚C, and +85 ⬚C
TPC 26. OIP3 vs. Frequency, VS = 4.5 V, 5 V, and
5.5 V, TA = 25 ⬚C
7.5
7.0
7.0
6.5
NOISE FIGURE (dB)
NOISE FIGURE (dB)
6.5
6.0
5.5
NF AT 5.5V
5.0
6.0
5.5
5.0
NF AT +85ⴗC
4.5
NF AT +25ⴗC
4.0
4.5
NF AT –40ⴗC
3.5
NF AT 4.5V
NF AT 5.0V
4.0
3.0
0
500
1000
1500
2000
2500
0
3000
TPC 27. Noise Figure vs. Frequency, VS = 4.5 V,
5 V, and 5.5 V, TA = 25 ⬚C
REV. A
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 30. Noise Figure vs. Frequency, VS = 5 V,
TA = –40 ⬚C, +25 ⬚C, and +85 ⬚C
–9–
AD8354
40
15
20
10
19
5
18
0
17
–5
16
–10
15
35
20
15
GAIN (dB)
25
POUT (dBm)
PERCENTAGE
30
10
5
0
4.5
–15
4.6
4.7
4.8
4.9 5.0 5.1 5.2
NOISE FIGURE (dB)
5.3
5.4
5.5
5.6
–20
–15
–10
–5
0
TPC 33. Output Power and Gain vs. Input Power,
VS = 3 V, TA = 25 ⬚C, f = 900 MHz
35
15
20
10
19
5
18
0
17
–5
16
–10
15
IS AT 5.5V
IS AT 4.5V
20
IS AT 5.0V
15
GAIN (dB)
25
POUT (dBm)
SUPPLY CURRENT (mA)
–25
PIN (dBm)
TPC 31. Distribution of Noise Figure, VS = 5 V,
TA = 25 ⬚C, f = 2.2 GHz
30
14
–30
10
5
0
–60
–40
–20
0
20
40
60
80
–15
–30
100
TEMPERATURE (ⴗC)
–25
–20
–15
–10
–5
0
14
PIN (dBm)
TPC 32. Supply Current vs. Temperature, VS = 4.5 V,
5 V, and 5.5 V
TPC 34. Output Power and Gain vs. Input Power,
VS = 5 V, TA = 25 ⬚C, f = 900 MHz
–10–
REV. A
AD8354
THEORY OF OPERATION
APPLICATIONS
The AD8354 is a two-stage feedback amplifier employing both
shunt-series and shunt-shunt feedback. The first stage is degenerated and resistively loaded, and provides approximately 10 dB
of gain. The second stage is a PNP-NPN Darlington output
stage, which provides another 10 dB of gain. Series-shunt feedback from the emitter of the output transistor sets the input
impedance to 50 Ω over a broad frequency range. Shunt-shunt
feedback from the amplifier output to the input of the Darlington
stage helps to set the output impedance to 50 Ω. The amplifier
can be operated from a 3 V supply by adding a choke inductor
from the amplifier output to VPOS. Without this choke inductor,
operation from a 5 V supply is also possible.
The AD8354 RF gain block may be used as a general-purpose
fixed-gain amplifier in a wide variety of applications, such as a
driver for a transmitter power amplifier (Figure 1). Its excellent
reverse isolation also makes this amplifier suitable for use as a
local oscillator buffer amplifier that would drive the local oscillator port of an up or down converter mixer (Figure 2).
HIGH POWER
AMPLIFIER
AD8354
Figure 1. AD8354 as a Driver Amplifier
BASIC CONNECTIONS
The AD8354 RF gain block is a fixed-gain amplifier with singleended input and output ports whose impedances are nominally
equal to 50 Ω over the frequency range 100 MHz to 2.7 GHz.
Consequently, it can be directly inserted into a 50 Ω system
with no impedance matching circuitry required. The input and
output impedances are sufficiently stable versus variations in
temperature and supply voltage that no impedance matching
compensation is required. A complete set of scattering parameters
is available at the Analog Devices website (www.analog.com).
MIXER
AD8354
LOCAL
OSCILLATOR
Figure 2. AD8354 as a LO Driver Amplifier
AD8354
The input pin (INPT) is connected directly to the base of the
first amplifier stage, which is internally biased to approximately
1 V, so a dc-blocking capacitor should be connected between
the source that drives the AD8354 and the input pin, INPT.
When the supply voltage is 3 V, it is recommended that an external
RF choke be connected between the supply voltage and the
output pin, VOUT. This will increase the dc voltage applied to
the collector of the output amplifier stage, which will improve
performance of the AD8354 to be very similar to the performance produced when 5 V is used for the supply voltage. The
inductance of the RF choke should be approximately 100 nH.
Care should be taken to ensure that the lowest series self-resonant
frequency of this choke is well above the maximum frequency of
operation for the AD8354.
The supply voltage input, VPOS, should be bypassed using a large
value capacitance (approximately 0.47 µF or larger) and a smaller,
high frequency bypass capacitor (approximately 100 pF) physically located close to the VPOS pin.
2 NC
VOUT 7
3 INPT
VPOS 6
C2
1000pF
OUTPUT
L1
VP
C3
100pF
4 COM2
C4
0.47␮F
COM2 5
NC = NO CONNECT
Figure 3. Evaluation Board Schematic
EVALUATION BOARD
Figure 3 shows the schematic of the AD8354 evaluation board.
Note that L1 is shown as an optional component, which is used
to obtain maximum gain only when VP = 3 V. The board is
powered by a single supply in the 2.7 V to 5.5 V range. The
power supply is decoupled by 0.47 µF and 100 pF capacitors.
Table I. Evaluation Board Configuration Options
Component Function
Default Value
C1, C2
C3
1000 pF, 0603
C4
L1
The recommended connections and components are shown in
the schematic of the AD8354 evaluation board (Figure 3).
REV. A
COM1 8
C1
1000pF
INPUT
It is critical to supply very low inductance ground connections
to the ground pins (Pins 1, 4, 5, and 8) as well as to the backside exposed paddle. This will ensure stable operation.
The AD8354 is designed to operate over a wide supply voltage
range from 2.7 V to 5.5 V. The output of the part, VOUT, is
taken directly from the collector of the output amplifier stage.
This node is internally biased to approximately 3.2 V when the
supply voltage is 5 V. Consequently, a dc-blocking capacitor
should be connected between the output pin, VOUT, and the
load that it drives. The value of this capacitor is not critical, but
it should be 100 pF or larger.
1 COM1
–11–
AC Coupling Capacitors.
High Frequency Bypass
Capacitor.
Low Frequency Bypass
Capacitor.
Optional RF Choke. Used
to increase current through
output stage when VP = 3 V.
Not recommended for use
when VP = 5 V.
100 pF, 0603
0.47 µF, 0603
100 nH, 0603
AD8354
Figure 4. Silkscreen Top
Figure 5. Component Side
–12–
REV. A
AD8354
OUTLINE DIMENSIONS
8-Lead Lead Frame Chip Scale Package [LFCSP]
2mm x 3 mm Body
(CP-8)
Dimensions shown in millimeters
1.89
1.74
1.59
3.25
3.00
2.75
PIN 1
INDICATOR
1.00
0.90
0.80
SEATING
PLANE
0.60
0.45
0.30
2.25
2.00
1.75
1.95
1.75
1.55
5
BOTTOM VIEW
4
2.95
2.75
2.55
0.50 BSC
12ⴗ
0ⴗ
0.80 MAX
0.65 NOM
0.30
0.23
0.18
0.05
0.02
0.00
0.20 REF
NOTES
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2. PADDLE IS COPPER PLATED WITH LEAD FINISH.
REV. A
–13–
0.55
0.40
0.30
8
0.15
0.10
0.05
1
0.25
0.20
0.15
AD8354
Revision History
Location
Page
6/02—Data Sheet changed from REV. 0 to REV. A.
Change to ORDERING GIUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Replaced TPC 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
–14–
REV. A
–15–
–16–
C02722–0–6/03(A)