Revised February 2000 DM74174 Hex/Quad D-Type Flip-Flop with Clear General Description Features These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input. ■ Contains six flip-flops with single-rail outputs Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. ■ Applications include: ■ Buffered clock and direct clear inputs ■ Individual data input to each flip-flop Buffer/storage registers Shift registers Pattern generators ■ Typical clock frequency 40 MHz ■ Typical power dissipation per flip-flop 38 mW Ordering Code: Order Number DM74174 Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table (Each Flip-Flop) Inputs Outputs Clear Clock D L X X Q L H ↑ H H H ↑ L L H L X Q0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care ↑ = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady-state input conditions were established. © 2000 Fairchild Semiconductor Corporation DS006557 www.fairchildsemi.com DM74174 Hex/Quad D-Type Flip-Flop with Clear September 1986 DM74174 Logic Diagram www.fairchildsemi.com 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.8 mA 2 V IOL LOW Level Output Current fCLK Clock Frequency (Note 2) tW Pulse Width Clock LOW 25 (Note 2) Clock HIGH 10 Clear 20 tSU Data Setup Time (Note 2) 20 ns tH Data Hold Time (Note 2) 0 ns tREL Clear Release Time (Note 2) 30 TA Free Air Operating Temperature 0 0 16 mA 30 MHz ns ns °C 70 Note 2: TA = 25°C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −12 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min, VIL = Max Min Typ (Note 3) Max Units −1.5 V 2.4 V 0.4 V mA II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 IIH HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA IOS Short Circuit Output Current VCC = Max (Note 4) ICC Supply Current VCC = Max (Note 5) −18 45 −57 mA 65 mA Note 3: All typicals are at VCC = 5V, TA = 25°C. Note 4: Not more than one output should be shorted at a time. Note 5: With all outputs open and all DATA and CLEAR inputs at 4.5V, ICC is measured after a momentary ground, then 4.5V applied to the CLOCK input. Switching Characteristics at VCC = 5V and TA = 25°C Symbol Parameter From (Input) To (Output) fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output RL = 400Ω, CL = 15 pF Min Units Max 30 MHz Clock to Any Q 25 ns Clock to Any Q 25 ns Clear to Any Q 40 ns 3 www.fairchildsemi.com DM74174 Absolute Maximum Ratings(Note 1) DM74174 Hex/Quad D-Type Flip-Flop with Clear Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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