Freescale MPC8358TVRADDDA Powerquiccâ ¢ ii pro processor revision 2.1 pbga silicon hardware specification Datasheet

Freescale Semiconductor
Technical Data
Document Number: MPC8358EEC
Rev. 1, 12/2007
MPC8358E
PowerQUICC™ II Pro Processor
Revision 2.1 PBGA Silicon
Hardware Specifications
This document provides an overview of the MPC8358E
PowerQUICC™ II Pro processor revision 2.1 PBGA
features, including a block diagram showing the major
functional components. This device is a cost-effective,
highly integrated communications processor that addresses
the needs of the networking, wireless infrastructure and
telecommunications markets. Target applications include
next generation DSLAMs, network interface cards for 3G
basestations (Node Bs), routers, media gateways and high
end IADs. The device extends current PowerQUICC II Pro
offerings, adding higher CPU performance, additional
functionality, faster interfaces and robust interworking
between protocols while addressing the requirements related
to time-to-market, price, power, and package size. This
device can be used for the control plane along with data
plane functionality.
For functional characteristics of the processor, refer to the
MPC8360E PowerQUICC™ Pro Integrated
Communications Processor Family Reference Manual,
Rev. 2.
To locate any published errata or updates for this document,
contact your Freescale sales office.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 17
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
UCC Ethernet Controller: Three-Speed Ethernet, MII
Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
HDLC, BISYNC, Transparent, and Synchronous
UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . 66
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
System Design Information . . . . . . . . . . . . . . . . . . . . 90
Document Revision History. . . . . . . . . . . . . . . . . . . . 94
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 94
Overview
1
Overview
This section describes a high-level overview including features and general operation of the MPC8358E
PowerQUICC™ II Pro processor. A major component of this device is the e300 core which includes
32 Kbytes of instruction and data cache and is fully compatible with the PowerPC™ 603e instruction set.
The new QUICC Engine™ module provides termination, interworking, and switching between a wide
range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module's enhanced
interworking eases the transition and reduces investment costs from ATM to IP based systems. The
MPC8358E has a single DDR SDRAM memory controller. The MPC8358E also offers a 32-bit PCI
controller, a flexible local bus, and a dedicated security engine.
System Interface Unit
(SIU)
e300 Core
32KB
I-Cache
Security Engine
32KB
D-Cache
Memory Controllers
GPCM/UPM/SDRAM
Classic G2 MMUs
32/64 DDR Interface Unit
FPU
Power
Management
PCI Bridge
JTAG/COP
Timers
Local Bus
PCI
Local
Bus Arbitration
QUICC Engine Module
Multi-User
RAM
Accelerators
Baud Rate
Generators
DDRC
Dual 32-bit RISC CP
DUART
Serial DMA
&
2 Virtual
DMAs
Dual I2C
4 Channel DMA
Parallel I/O
SPI2
SPI1
USB
UCC8
UCC5
UCC4
UCC3
UCC2
UCC1
Interrupt Controller
Protection & Configuration
System Reset
Time Slot Assigner
Clock Synthesizer
Serial Interface
4 TDM Ports
6 MII/
RMII
2 GMII/
RGMII/TBI/RTBI
1 UTOPIA/POS
(31/124 MPHY)
Figure 1. MPC8358E Block Diagram
Major features of the MPC8358E are as follows:
• e300 PowerPC processor core (enhanced version of the MPC603e core)
— Operates at up to 400 MHz (for the MPC8358E)
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Overview
—
—
—
—
•
32-Kbyte instruction cache, 32-Kbyte data cache
Lockable portion of L1 cache
Dynamic power management
Software-compatible with the Freescale processor families implementing the Power
Architecture™ technology
QUICC Engine unit
— Two 32-bit RISC controllers for flexible support of the communications peripherals, each
operating up to 400 MHz (for the MPC8358E)
— Serial DMA channel for receive and transmit on all serial channels
— QE peripheral request interface (for SEC, PCI, IEEE® Std 1588™)
— Six UCCs on the MPC8358E supporting the following protocols and interfaces (not all of them
simultaneously):
– IEEE Std. 1588 protocol supported
– 10/100 Mbps Ethernet/IEEE Std. 802.3® CDMA/CS interface through a
media-independent interface (MII, RMII, RGMII)1
– 1000 Mbps Ethernet/IEEE Std. 802.3 CDMA/CS interface through a media-independent
interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2
– 9.6K jumbo frames
– ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1 and AAL5 in
accordance ITU-T I.363.5
– ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex
(with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2
– ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM
forum TM4.1 for up to 64K simultaneous ATM channels
– ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance
with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000
– IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in
accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001
(Version 1.1)
– ATM Transmission Convergence layer support in accordance with ITU-T I.432
– ATM OAM handling features compatible with ITU-T I.610
– PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the
following RFCs: 1661, 1662, 1990, 2686 and 3153
– IP support for IPv4 packets including TOS, TTL and header checksum processing
– Ethernet over first mile IEEE Std. 802.3ah®
– Shim header
– Ethernet-to-Ethernet/AAL5/AAL2 inter-working
– L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q® VLAN tags
1. SMII or SGMII media-independent interface is not currently supported
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Overview
•
– ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including
bridging of ATM ports to Ethernet ports
– Extensive support for ATM statistics and Ethernet RMON/MIB statistics
– AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate
– Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY
– POS hardware; microcode must be loaded as an IRAM package
– Transparent up to 70-Mbps full-duplex
– HDLC up to 70-Mbps full-duplex
– HDLC BUS up to 10 Mbps
– Asynchronous HDLC
– UART
– BISYNC up to 2 Mbps
– User-programmable Virtual FIFO size
– QUICC Multichannel Controller (QMC) for 64 TDM channels
— One UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY
— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management
— Four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel
— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC
serial channels
— Four independent 16-bit timers that can be interconnected as four 32-bit timers
— Interworking functionality:
– Layer 2 10/100-Base T Ethernet switch
– ATM-to-ATM switching (AAL0, 2, 5)
– Ethernet-to-ATM switching with L3/L4 support
– PPP interworking
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
802.11i, iSCSI, and IKE processing. The security engine contains four crypto-channels, a
controller, and a set of crypto execution units (EUs).
— Public key execution unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Overview
•
•
— Advanced encryption standard unit (AESU)
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits, two key
– ECB, CBC, CCM, and counter modes
— ARC four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either SHA or MD5 algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— Storage/NAS XOR parity generation accelerator for RAID applications
DDR SDRAM memory controller on the MPC8358E
— Programmable timing supporting both DDR1 and DDR2 SDRAM
— On the MPC8358E, the DDR bus can be configured as a 32-bit or a 64-bit bus
— 32- or 64-bit data interface, up to 266 MHz (for the MPC8358E) data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gigabit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open
pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— Supports source clock mode
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
— External driver impedance calibration
— On-die termination (ODT)
PCI interface
— PCI Specification Revision 2.3 compatible
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Overview
•
•
•
— Data bus widths:
– Single 32-bit data PCI interface that operates at up to 66 MHz
— PCI 3.3-V compatible (not 5-V compatible)
— PCI host bridge capabilities on both interfaces
— PCI agent mode supported on PCI interface
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting five masters on PCI
— Support for accesses to all PCI address spaces
— Parity support
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle supported when the device is the target
— Internal configuration registers accessible from PCI
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for one external (optional) and seven internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to communication processor
— Redirects interrupts to external INTA pin when in core disable mode
— Unique vector number for each interrupt source
Dual industry-standard I2C interfaces
— Two-wire interface
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Electrical Characteristics
—
—
—
—
•
•
•
•
•
2
Multiple master support
Master or slave I2C mode support
On-chip digital filtering rejects spikes on the bus
System initialization data is optionally loaded from I2C-1 EPROM by boot sequencer
embedded hardware
DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible by local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
— DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3].
There is one set for each DMA channel. The pins are multiplexed to the parallel IO pins with
other QE functions.
DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
IEEE Std. 1149.1™ compliant, JTAG boundary scan
Integrated PCI bus and SDRAM clock generation
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8358E. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings1
Characteristic
Symbol
Core supply voltage
Max Value
Unit
VDD
Notes
V
–0.3 to 1.32
PLL supply voltage
V
AV DD
–0.3 to 1.32
DDR and DDR2 DRAM I/O voltage
V
GVDD
–0.3 to 2.75
–0.3 to 1.89
DDR
DDR2
Three-speed Ethernet I/O, MII management voltage
LVDD
–0.3 to 3.63
V
PCI, local bus, DUART, system control and power management,
I2C, SPI, and JTAG I/O voltage
OVDD
–0.3 to 3.63
V
Input voltage
MVIN
–0.3 to (GVDD + 0.3)
V
2, 5
MVREF
–0.3 to (GVDD + 0.3)
V
2, 5
Three-speed Ethernet signals
LVIN
–0.3 to (LVDD + 0.3)
V
4, 5
Local bus, DUART, CLKIN, system
control and power management, I2C,
SPI, and JTAG signals
OVIN
–0.3 to (OV DD + 0.3)
V
3, 5
PCI
OVIN
–0.3 to (OV DD + 0.3)
V
6
TSTG
–55 to 150
°C
DDR DRAM signals
DDR DRAM reference
Storage temperature range
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or
cause permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation,
as shown in Figure 3.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Electrical Characteristics
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the device. Note that the values in Table 2 are
the recommended and tested operating conditions. Proper device operation outside of these conditions is
not guaranteed.
Table 2. Recommended Operating Conditions
Symbol
Recommended
Value
Unit
Notes
Core supply voltage
VDD
1.2 V ± 60 mV
V
1
PLL supply voltage
AVDD
1.2 V ± 60 mV
V
1
Characteristic
DDR and DDR2 DRAM I/O supply voltage
V
GVDD
2.5 V ± 125 mV
1.8V ± 90 mV
DDR
DDR2
Three-speed Ethernet I/O supply voltage
LVDD0
3.3 V ± 330 mV
2.5 V ± 125 mV
V
Three-speed Ethernet I/O supply voltage
LVDD1
3.3 V ± 330 mV
2.5 V ± 125 mV
V
Three-speed Ethernet I/O supply voltage
LVDD2
3.3 V ± 330 mV
2.5 V ± 125 mV
V
PCI, local bus, DUART, system control and power management, I2C, SPI,
and JTAG I/O voltage
OVDD
3.3 V ± 330 mV
V
TJ
0 to 105
°C
Junction temperature
Notes:
1. GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or
negative direction.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the device.
G/L/OVDD + 20%
G/L/OVDD + 5%
VIH
G/L/OVDD
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tinterface1
Note:
1. Note that tinterface refers to the clock period associated with the bus clock interface.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the device for the 3.3-V
signals, respectively.
11 ns
(Min)
+7.1 V
7.1 V p-to-p
(Min)
Overvoltage
Waveform
4 ns
(Max)
0V
4 ns
(Max)
62.5 ns
+3.6 V
7.1 V p-to-p
(Min)
Undervoltage
Waveform
–3.5 V
Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Driver Type
Output Impedance (Ω)
Supply Voltage
Local bus interface utilities signals
42
OVDD = 3.3 V
PCI signals
25
PCI output clocks (including PCI_SYNC_OUT)
42
DDR signal
20
36 (half strength mode) 1
GVDD = 2.5 V
DDR2 signal
18
36 (half strength mode) 1
GVDD = 1.8 V
42
LV DD = 2.5/3.3 V
42
OVDD = 3.3 V
42
OVDD = 3.3 V
LV DD = 2.5/3.3 V
10/100/1000 Ethernet signals
DUART, system control,
I2C,
SPI, JTAG
GPIO signals
1
2.2
DDR output impedance values for half strength mode are verified by design and not tested
Power Sequencing
This section details the power sequencing considerations for the MPC8358E.
2.2.1
Power-Up Sequencing
MPC8358E does not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD,
LVDD, and OVDD) to be applied in any particular order. During the power ramp up, before the power
supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of
time that all input and output pins will actively be driven and cause contention and excessive current. In
order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage
(VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power supplies
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Power Characteristics
fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90%
of its nominal value before the I/O supplies reach 0.7 V, see Figure 4.
Figure 4. Power Sequencing Example
Voltage
I/O Voltage (GVDD, LV DD, OVDD)
Core Voltage (VDD, AVDD)
0.7 V
90%
Time
I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one
another.
2.2.2
Power-Down Sequencing
The MPC8358E does not require the core supply voltage and I/O supply voltages to be powered-down in
any particular order.
3
Power Characteristics
The estimated typical power dissipation values are shown in Table 4.
Table 4. MPC8358E PBGA Core Power Dissipation1
Core
Frequency (MHz)
CSB
QUICC Engine
Frequency (MHz) Frequency (MHz)
Typical
Maximum
Unit
Notes
266
266
266
2.2
2.3
W
2, 3, 4
400
266
266
2.4
2.5
W
2, 3, 4
Notes:
1. The values do not include I/O supply power (OV DD, LV DD, GVDD) or AVDD. For I/O power values, see Table 5.
2. Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark
application.
3. Thermal solutions will likely need to design to a value higher than typical power on the end application, TA target, and I/O
power.
4. Maximum power is based on a voltage of VDD = 1.2 V, WC process, a junction TJ = 105°C, and an artificial smoke test.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Clock Input Timing
Table 5 shows the estimated typical I/O power dissipation for the device.
Table 5. Estimated Typical I/O Power Dissipation
GVDD
(1.8 V)
GVDD
(2.5 V)
200 MHz, 1x32 bits
0.3
0.46
W
200 MHz, 1x64 bits
0.4
0.58
W
200 MHz, 2x32 bits
0.6
0.92
W
266 MHz, 1x32 bits
0.35
0.56
W
266 MHz, 1x64 bits
0.46
0.7
W
266 MHz, 2x32 bits
0.7
1.11
W
Interface
DDR I/O
65% utilization
2.5 V
Rs = 20 Ω
Rt = 50 Ω
2 pairs of
clocks
Local Bus I/O
Load = 25 pf
3 pairs of
clocks
Parameter
OVDD
(3.3 V)
LV DD
(3.3 V)
133 MHz, 32 bits
0.22
W
83 MHz, 32 bits
0.14
W
66 MHz, 32 bits
0.12
W
50 MHz, 32 bits
0.09
W
PCI I/O
Load = 30 pf
33 MHz, 32 bits
0.05
W
66 MHz, 32 bits
0.07
W
10/100/1000
Ethernet I/O
Load = 20 pf
MII or RMII
0.01
W
GMII or TBI
0.04
W
RGMII or RTBI
0.04
Other I/O
4
LV DD
Unit
(2.5 V)
0.1
Comments
Multiply by number
of interfaces used.
W
W
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8358E.
4.1
DC Electrical Characteristics
Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.
Table 6. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
—
VIH
2.7
OVDD + 0.3
V
Input low voltage
—
VIL
–0.3
0.4
V
0 V ≤ VIN ≤ OVDD
IIN
—
±10
μA
PCI_SYNC_IN input current
0 V ≤ VIN ≤ 0.5V or
OV DD – 0.5V ≤ VIN ≤ OVDD
IIN
—
±10
μA
PCI_SYNC_IN input current
0.5 V ≤ VIN ≤ OVDD – 0.5 V
IIN
—
±100
μA
CLKIN input current
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
13
RESET Initialization
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
Table 7. CLKIN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
CLKIN/PCI_CLK frequency
fCLKIN
—
—
66.67
MHz
1
CLKIN/PCI_CLK cycle time
tCLKIN
15
—
—
ns
—
CLKIN/PCI_CLK rise and fall time
tKH, tKL
0.6
1.0
2.3
ns
2
tKHK/tCLKIN
40
—
60
%
3
—
—
—
±150
ps
4, 5
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or
minimum operating frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set
low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8358E.
5.1
RESET DC Electrical Characteristics
Table 8 provides the DC electrical characteristics for the RESET pins of the device.
Table 8. RESET Pins DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
2.0
OVDD +
0.3
V
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
±10
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
14
Freescale Semiconductor
RESET Initialization
Table 8. RESET Pins DC Electrical Characteristics (continued)
Characteristic
Output low voltage
Symbol
Condition
Min
Max
Unit
VOL
IOL = 3.2 mA
—
0.4
V
Notes:
1. This table applies for pins PORESET, HRESET, SRESET and QUIESCE.
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
5.2
RESET AC Electrical Characteristics
This section describes the AC electrical specifications for the reset initialization timing requirements of
the device. Table 9 provides the reset initialization AC timing specifications for the DDR SDRAM
component(s).
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET
(input) to activate reset flow
32
—
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable
clock applied to CLKIN when the device is in PCI host
mode
32
—
tCLKIN
2
Required assertion time of PORESET with stable
clock applied to PCI_SYNC_IN when the device is in
PCI agent mode
32
—
tPCI_SYNC_IN
1
HRESET/SRESET assertion (output)
512
—
tPCI_SYNC_IN
1
HRESET negation to SRESET negation (output)
16
—
tPCI_SYNC_IN
1
Input setup time for POR config signals
(CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of
PORESET when the device is in PCI host mode
4
—
tCLKIN
2
Input setup time for POR config signals
(CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of
PORESET when the device is in PCI agent mode
4
—
tPCI_SYNC_IN
1
Input hold time for POR config signals with respect to
negation of HRESET
0
—
ns
Time for the device to turn off POR config signals with
respect to the assertion of HRESET
—
4
ns
3
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
15
RESET Initialization
Table 9. RESET Initialization Timing Specifications (continued)
Time for the device to turn on POR config signals with
respect to the negation of HRESET
1
—
1, 3
tPCI_SYNC_IN
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode
the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of
CFG_CLKIN_DIV. See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more
details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode.
See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 10 provides the PLL and DLL lock times.
Table 10. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs
DLL lock times
7680
122,880
csb_clk cycles
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk).
A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 22, “Clocking,” for more information.
5.3
QE Operating Frequency Limitations
This section specify the limits of the AC electrical characteristics for the operation of the QE’s
communication interfaces.
NOTE
The settings listed below are required for correct hardware interface
operation. Each protocol by itself requires a minimal QE operating
frequency setting for meeting the performance target. Because the
performance is a complex function of all the QE settings, the user should
make use of the QE performance utility tool provided by Freescale to
validate their system.
Table 11 lists the maximal QE I/O frequencies and the minimal QE core frequency for each interface.
Table 11. QE Operating Frequency Limitations
Interface Operating
Frequency (MHz)
Max interface
Bit Rate (Mbps)
Min QE Operating
Frequency1 (MHz)
Ethernet Management:
MDC/MDIO
10 (max)
10
20
MII
25 (typ)
100
50
RMII
50 (typ)
100
50
GMII/RGMII/TBI/RTBI
125 (typ)
1000
250
Interface
Notes
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
16
Freescale Semiconductor
DDR and DDR2 SDRAM
Table 11. QE Operating Frequency Limitations (continued)
Interface Operating
Frequency (MHz)
Max interface
Bit Rate (Mbps)
Min QE Operating
Frequency1 (MHz)
SPI (master/slave)
10 (max)
10
20
UCC through TDM
50 (max)
70
8×F
2
MCC
25 (max)
16.67
16 × F
2, 4
UTOPIA L2
50 (max)
800
2×F
2
POS-PHY L2
50 (max)
800
2×F
2
HDLC Bus
10 (max)
10
20
HDLC/Transparent
50 (max)
50
8/3 × F
UART/Async HDLC
3.68 (max internal ref
clock)
115 (Kbps)
20
2 (max)
2
20
48 (ref clock)
12
96
Interface
BISYNC
USB
Notes
2, 3
Note:
1. The QE needs to run at a frequency higher than or equal to what is listed in this table.
2. ‘F’ is the actual interface operating frequency.
3. The bit rate limit is independent of the data bus width (i.e. the same for serial, nibble, or octal
interfaces).
4. TDM in high-speed mode for serial data interface.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface
of the MPC8358E.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GVDD(typ) = 1.8 V.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.71
1.89
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GV DD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.125
GVDD + 0.3
V
Input low voltage
VIL
–0.3
MVREF – 0.125
V
Output leakage current
IOZ
—
±10
μA
Output high current (VOUT = 1.420 V)
IOH
–13.4
—
mA
4
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
17
DDR and DDR2 SDRAM
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
Output low current (VOUT = 0.280 V)
MV REF input leakage current
Input current (0 V ≤VIN ≤ OVDD)
IOL
13.4
—
mA
IVREF
—
±10
μA
IIN
—
μA
±10
Notes:
1. GV DD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MV REF is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise
on MVREF cannot exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal
MV REF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV DD.
Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) of the
device when GVDD(typ) = 2.5 V.
Table 14. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
Input low voltage
VIL
–0.3
MVREF – 0.18
V
Output leakage current
IOZ
—
±10
μA
Output high current (VOUT = 1.95 V)
IOH
–15.2
—
mA
Output low current (VOUT = 0.35 V)
IOL
15.2
—
mA
IVREF
—
±10
μA
MV REF input leakage current
4
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Freescale Semiconductor
DDR and DDR2 SDRAM
Table 14. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V (continued)
Input current (0 V ≤VIN ≤ OVDD)
IIN
—
μA
±10
Notes:
1. GV DD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MV REF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected
to be equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV DD.
Table 15 provides the DDR capacitance when GVDD(typ) = 2.5 V.
Table 15. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak to peak) =
0.2 V.
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
Table 16 provides the input AC timing specifications for the DDR2 SDRAM interface when
GVDD(typ) = 1.8 V.
Table 16. DDR2 SDRAM Input AC Timing Specifications for GVDD(typ) = 1.8 V
At recommended operating conditions with GVDD of 1.8 V ± 5%.
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—
MVREF – 0.25
V
AC input high voltage
VIH
MVREF + 0.25
—
V
Notes
Table 17 provides the input AC timing specifications for the DDR SDRAM interface when
GVDD(typ) = 2.5 V.
Table 17. DDR SDRAM Input AC Timing Specifications Mode for GVDD(typ) = 2.5 V
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
AC input low voltage
Symbol
Min
Max
Unit
VIL
—
MVREF – 0.31
V
Notes
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
19
DDR and DDR2 SDRAM
Table 17. DDR SDRAM Input AC Timing Specifications Mode for GVDD(typ) = 2.5 V (continued)
At recommended operating conditions with GVDD of 2.5 V ± 5%.
AC input high voltage
VIH
MVREF + 0.31
—
V
Notes:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if
0 ≤ n ≤ 7) or ECC (MECC[{0...7}] if n = 8).
Table 18. DDR and DDR2 SDRAM Input AC Timing Specifications Mode for GVDD(typ) = 2.5 V
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol
MDQS—MDQ/MECC input skew per byte
266 MHz
200 MHz
tDISKEW
Min
Max
-1125
-1250
1125
1250
Unit
Notes
ps
1, 2
Notes:
1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if
0 ≤ n ≤ 7) or ECC (MECC[{0...7}] if n = 8).
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 19 and Table 20 provide the output AC timing specifications and measurement conditions for the
DDR and DDR2 SDRAM interface.
Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.
Parameter 8
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
Symbol 1
Min
Max
Unit
Notes
tMCK
6
10
ns
2
ns
3
-1.1
-1.2
0.3
0.4
—
ns
4
—
ns
4
—
ns
4
—
ns
4
0.6
ns
5
tAOSKEW
266 MHz
200 MHz
ADDR/CMD output setup with respect to MCK
266 MHz
200 MHz
tDDKHAS
ADDR/CMD output hold with respect to MCK
266 MHz - DDR1
266 MHz - DDR2
200 MHz
tDDKHAX
MCS(n) output setup with respect to MCK
tDDKHCS
2.8
3.5
2.6
2.8
3.5
2.8
3.5
266 MHz
200 MHz
MCS(n) output hold with respect to MCK
tDDKHCX
2.7
3.5
266 MHz
200 MHz
MCK to MDQS
tDDKHMH
–0.75
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Freescale Semiconductor
DDR and DDR2 SDRAM
Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications for Source Synchronous Mode
(continued)
Parameter 8
Symbol 1
MDQ/MECC/MDM output setup with respect to MDQS
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
MDQ/MECC/MDM output hold with respect to MDQS
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
MDQS preamble start
tDDKHMP
MDQS epilogue end
tDDKHME
Min
Max
Unit
Notes
—
ns
6
—
ns
6
-0.5 × tMCK – 0.6
-0.5 × tMCK + 0.6
ns
7
–0.6
0.9
ns
7
1.0
1.2
1.0
1.2
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control
Register. For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the
address/command valid with the rising edge of MCK.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks
by 1/2 applied cycle.
5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to
the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these
2 parameters have been set to the same adjustment value. See the MPC8360E Integrated Communications Processor
Reference Manual, Rev. 2 for a description and understanding of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that tDDKHMP follows the symbol
conventions described in note 1.
8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
21
DDR and DDR2 SDRAM
Figure 5 shows the DDR SDRAM output timing for address skew with respect to any MCK.
MCK[n]
MCK[n]
tMCK
tAOSKEW(max)
ADDR/CMD
CMD
NOOP
tAOSKEW(min)
ADDR/CMD
CMD
NOOP
Figure 5. Timing Diagram for tAOSKEW Measurement
Figure 6 provides the AC test load for the DDR bus.
Output
Z0 = 50 Ω
RL = 50 Ω
GVDD/2
Figure 6. DDR AC Test Load
Table 20. DDR and DDR2 SDRAM Measurement Conditions
Symbol
VTH
VOUT
DDR
DDR2
Unit
Notes
MVREF ± 0.31 V
MVREF ± 0.25 V
V
1
0.5 × GVDD
0.5 × GVDD
V
2
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
22
Freescale Semiconductor
DDR and DDR2 SDRAM
Figure 7 shows the DDR SDRAM output timing diagram for source synchronous mode.
MCK[n]
MCK[n]
tMCK
tDDKHAS ,tDDKHCS
tDDKHAX ,tDDKHCX
ADDR/CMD
Write A0
NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKHME
tDDKHDS
tDDKLDS
MDQ[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 7. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
Table 21 provides approximate delay information that can be expected for the address and command
signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.
These numbers are the result of simulations for one topology. The delay numbers will strongly depend on
the topology used. These delay numbers show the total delay for the address and command to arrive at the
DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the
system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup
requirements at the DRAM.
Table 21. Expected Delays for Address/Command
Load
Delay
Unit
4 devices (12 pF)
3.0
ns
9 devices (27 pF)
3.6
ns
36 devices (108 pF) + 40 pF compensation capacitor
5.0
ns
36 devices (108 pF) + 80 pF compensation capacitor
5.2
ns
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
23
DUART
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8358E.
7.1
DUART DC Electrical Characteristics
Table 22 provides the DC electrical characteristics for the DUART interface of the device.
Table 22. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage OVDD
VIL
–0.3
0.8
V
High-level output voltage,
IOH = –100 μA
VOH
OV DD – 0.4
—
V
Low-level output voltage,
IOL = 100 μA
VOL
—
0.2
V
IIN
—
±10
μA
Input current
(0 V ≤VIN ≤ OV DD)
Notes
1
Note:
1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2.
7.2
DUART AC Electrical Specifications
Table 23 provides the AC timing parameters for the DUART interface of the device.
Table 23. DUART AC Timing Specifications
Parameter
Value
Unit
Minimum baud rate
256
baud
Maximum baud rate
> 1,000,000
baud
1
16
—
2
Oversample rate
Notes
Notes:
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition
of the start bit. Subsequent bit values are sampled each 16th sample.
8
UCC Ethernet Controller: Three-Speed Ethernet, MII
Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII
management.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
24
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.1
Three-Speed Ethernet Controller (10/100/1000 Mbps)—
GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics
The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII
(media independent interface), RMII (reduced media independent interface), TBI (ten-bit interface),
RGMII (reduced gigabit media independent interface), and RTBI (reduced ten-bit interface) signals except
MDIO (management data input/output) and MDC (management data clock). The MII, RMII, GMII and
TBI interfaces are only defined for 3.3V, while the RGMII and RTBI interfaces are only defined for 2.5 V.
The RGMII and RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit
Ethernet Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for
the MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical
Characteristics.”
8.1.1
10/100/1000 Ethernet DC Electrical Characteristics
All GMII, MII, RMII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric
attributes specified in Table 24 and Table 25. The potential applied to the input of a GMII, MII, RMII, TBI,
RGMII, or RTBI receiver may exceed the potential of the receiver’s power supply (i.e., a RGMII driver
powered from a 3.6-V supply driving VOH into a RGMII receiver powered from a 2.5 V supply). Tolerance
for dissimilar RGMII driver and receiver supply potentials is implicit in these specifications. The RGMII
and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 24. RGMII/RTBI, GMII, TBI, MII, and RMII DC Electrical Characteristics (when operating at 3.3 V)
Parameter
Symbol
Conditions
Min
Max
Unit
Notes
Supply voltage 3.3 V
LVDD
—
2.97
3.63
V
1
Output high voltage
VOH
IOH = –4.0 mA
LVDD = Min
2.40
LVDD + 0.3
V
Output low voltage
VOL
IOL = 4.0 mA
LVDD = Min
GND
0.50
V
Input high voltage
VIH
—
—
2.0
LVDD + 0.3
V
Input low voltage
VIL
—
—
–0.3
0.90
V
Input current
IIN
—
±10
μA
0 V ≤ VIN ≤ LVDD
Note:
1. GMII/MII pins that are not needed for RGMII, RMII or RTBI operation are powered by the OVDD supply.
Table 25. RGMII/RTBI DC Electrical Characteristics (when operating at 2.5 V)
Parameters
Symbol
Conditions
Min
Max
Unit
Supply voltage 2.5 V
LVDD
—
2.37
2.63
V
Output high voltage
VOH
IOH = –1.0 mA
LVDD = Min
2.00
LVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDD = Min
GND – 0.3
0.40
V
Input high voltage
VIH
—
LVDD = Min
1.7
LVDD + 0.3
V
Input low voltage
VIL
—
LVDD = Min
–0.3
0.70
V
Input current
IIN
—
±10
μA
0 V ≤ VIN ≤ LVDD
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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25
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
8.2.1
GMII Timing Specifications
This sections describe the GMII transmit and receive AC timing specifications.
8.2.1.1
GMII Transmit AC Timing Specifications
Table 26 provides the GMII transmit AC timing specifications.
Table 26. GMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
tGTX
—
8.0
—
ns
tGTXH/tGTX
40
—
60
%
tGTKHDX
tGTKHDV
0.5
—
—
—
5.0
ns
GTX_CLK clock rise time, VIL(min) to VIH(max)
tGTXR
—
—
1.0
ns
GTX_CLK clock fall time, VIH(max) to VIL(min)
tGTXF
—
—
1.0
ns
GTX_CLK125 clock period
tG125
—
8.0
—
ns
2
tG125H/tG125
45
—
55
%
2
Parameter/Condition
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK125 reference clock duty cycle measured at LVDD/2
Notes
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV
symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to
the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit
timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals
(D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX)
clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming
convention.
Figure 8 shows the GMII transmit AC timing diagram.
tGTXR
tGTX
GTX_CLK
tGTXH
tGTXF
TXD[7:0]
TX_EN
TX_ER
tGTKHDX
Figure 8. GMII Transmit AC Timing Diagram
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.1.2
GMII Receive AC Timing Specifications
Table 27 provides the GMII receive AC timing specifications.
Table 27. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.
Symbol 1
Min
Typ
Max
Unit
tGRX
—
8.0
—
ns
tGRXH/tGRX
40
—
60
%
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
—
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0.3
—
—
ns
RX_CLK clock rise time, VIL(min) to VIH(max)
tGRXR
—
—
1.0
ns
RX_CLK clock fall time, VIH(max) to VIL(min)
tGRXF
—
—
1.0
ns
Parameter/Condition
RX_CLK clock period
RX_CLK duty cycle
Notes
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII
receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference
(K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
Figure 9 shows the GMII receive AC timing diagram.
tGRXR
tGRX
RX_CLK
tGRXH
tGRXF
RXD[7:0]
RX_DV
RX_ER
tGRDXKH
tGRDVKH
Figure 9. GMII Receive AC Timing Diagram
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.2
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1
MII Transmit AC Timing Specifications
Table 28 provides the MII transmit AC timing specifications.
Table 28. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—
400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—
40
—
ns
tMTXH/tMTX
35
—
65
%
tMTKHDX
tMTKHDV
1
—
5
—
15
ns
TX_CLK data clock rise time, VIL(min) to VIH(max)
tMTXR
1.0
—
4.0
ns
TX_CLK data clock fall time, VIH(max) to VIL(min)
tMTXF
1.0
—
4.0
ns
Parameter/Condition
TX_CLK duty cycle
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs
(D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters
representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 10 shows the MII transmit AC timing diagram.
tMTX
tMTXR
TX_CLK
tMTXH
tMTXF
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 10. MII Transmit AC Timing Diagram
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.2.2
MII Receive AC Timing Specifications
Table 29 provides the MII receive AC timing specifications.
Table 29. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—
400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—
40
—
ns
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
—
ns
RX_CLK clock rise time, VIL(min) to VIH(max)
tMRXR
1.0
—
4.0
ns
RX_CLK clock fall time, VIH(max) to VIL(min)
tMRXF
1.0
—
4.0
ns
Parameter/Condition
RX_CLK duty cycle
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V)
relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive
timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K)
going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on
three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII
(M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
Figure 11 provides the AC test load.
Z0 = 50 Ω
Output
RL = 50 Ω
LVDD/2
Figure 11. AC Test Load
Figure 12 shows the MII receive AC timing diagram.
tMRXR
tMRX
RX_CLK
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRXF
Valid Data
tMRDVKH
tMRDXKH
Figure 12. MII Receive AC Timing Diagram
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.3
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.3.1
RMII Transmit AC Timing Specifications
Table 30 provides the RMII transmit AC timing specifications.
Table 30. RMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
tRMX
—
20
—
ns
tRMXH/tRMX
35
—
65
%
tRMTKHDX
tRMTKHDV
2
—
—
—
10
ns
REF_CLK data clock rise time, VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK data clock fall time, VIH(max) to VIL(min)
tRMXF
1.0
—
4.0
ns
Parameter/Condition
REF_CLK clock
REF_CLK duty cycle
REF_CLK to RMII data TXD[1:0], TX_EN delay
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tRMTKHDX symbolizes RMII transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data
outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three
letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII(RM)
reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 13 shows the RMII transmit AC timing diagram.
tRMX
tRMXR
REF_CLK
tRMXH
tRMXF
TXD[1:0]
TX_EN
tRMTKHDX
Figure 13. RMII Transmit AC Timing Diagram
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.3.2
RMII Receive AC Timing Specifications
Table 31 provides the RMII receive AC timing specifications.
Table 31. RMII Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
tRMX
—
20
—
ns
tRMXH/tRMX
35
—
65
%
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
—
—
ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
—
—
ns
REF_CLK clock rise time, VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK clock fall time, VIH(max) to VIL(min)
tRMXF
1.0
—
4.0
ns
Parameter/Condition
REF_CLK clock period
REF_CLK duty cycle
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tRMRDVKH symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state
(V) relative to the tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII
receive timing (RMR) with respect to the time data input signals (D) went invalid (X) relative to the tRMX clock
reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation
is based on three letters representing the clock of a particular functional. For example, the subscript of tRMX
represents the RMII (RM) reference (X) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
Figure 14 provides the AC test load.
Z0 = 50 Ω
Output
RL = 50 Ω
LVDD/2
Figure 14. AC Test Load
Figure 15 shows the RMII receive AC timing diagram.
tRMXR
tRMX
REF_CLK
tRMXH
RXD[1:0]
CRS_DV
RX_ER
tRMXF
Valid Data
tRMRDVKH
tRMRDXKH
Figure 15. RMII Receive AC Timing Diagram
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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31
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1
TBI Transmit AC Timing Specifications
Table 32 provides the TBI transmit AC timing specifications.
Table 32. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
tTTX
—
8.0
—
ns
tTTXH/tTTX
40
—
60
%
tTTKHDX
tTTKHDV
0.9
—
—
—
5.0
ns
GTX_CLK clock rise time, VIL(min) to VIH(max)
tTTXR
—
—
1.0
ns
GTX_CLK clock fall time, VIH(max) to VIL(min)
tTTXF
—
—
1.0
ns
GTX_CLK125 reference clock period
tG125
—
8.0
—
ns
tG125H/tG125
45
—
55
ns
Parameter/Condition
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK to TBI data TCG[9:0] delay
GTX_CLK125 reference clock duty cycle
Notes
2
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state
)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV
symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data
signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to
the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
Figure 16 shows the TBI transmit AC timing diagram.
tTTXR
tTTX
GTX_CLK
tTTXH
tTTXF
TXD[7:0]
TX_EN
TX_ER
tTTKHDX
Figure 16. TBI Transmit AC Timing Diagram
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.4.2
TBI Receive AC Timing Specifications
Table 33 provides the TBI receive AC timing specifications.
Table 33. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.
Symbol1
Parameter/Condition
PMA_RX_CLK clock period
Min
Typ
tTRX
Max
16.0
Unit
Notes
ns
PMA_RX_CLK skew
tSKTRX
7.5
—
8.5
ns
RX_CLK duty cycle
tTRXH/tTRX
40
—
60
%
RCG[9:0] setup time to rising PMA_RX_CLK
tTRDVKH
2.5
—
—
ns
2
RCG[9:0] hold time to rising PMA_RX_CLK
tTRDXKH
1.0
—
—
ns
2
RX_CLK clock rise time, VIL(min) to VIH(max)
tTRXR
0.7
—
2.4
ns
RX_CLK clock fall time, VIH(max) to VIL(min)
tTRXF
0.7
—
2.4
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH
symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the
tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with
respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript
is skew (SK) followed by the clock that is being skewed (TRX).
2. Setup and hold time of even numbered RCG are measured from riding edge of PMA_RX_CLK1. Setup and hold time of
odd numbered RCG are measured from riding edge of PMA_RX_CLK0.
Figure 17 shows the TBI receive AC timing diagram.
tTRX
tTRXR
PMA_RX_CLK1
tTRXH
tTRXF
Even RCG
RCG[9:0]
Odd RCG
tTRDVKH
tTRDXKH
tSKTRX
PMA_RX_CLK0
tTRXH
tTRDXKH
tTRDVKH
Figure 17. TBI Receive AC Timing Diagram
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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33
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.5
RGMII and RTBI AC Timing Specifications
Table 34 presents the RGMII and RTBI AC timing specifications.
Table 34. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Symbol1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGTKHDX
tSKRGTKHDV
–0.5
—
—
—
0.5
ns
Data to clock input skew (at receiver)
tSKRGDXKH
tSKRGDVKH
1.1
—
—
—
2.6
ns
2
tRGT
7.2
8.0
8.8
ns
3
Duty cycle for 1000Base-T
tRGTH/tRGT
45
50
55
%
4, 5
Duty cycle for 10BASE-T and 100BASE-TX
tRGTH/tRGT
40
50
60
%
3, 5
Rise time (20%–80%)
tRGTR
—
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
—
0.75
ns
tG125
—
8.0
—
ns
tG125H/tG125
47
—
53
%
Parameter/Condition
Clock cycle duration
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes
6
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Duty cycle reference is LVDD/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.7.In
rev2.1 silicon, due to errata, tSKRGTKHDX minimum is -0.65 ns for UCC2 option 1 and -0.9 for UCC2 option 2, and tSKRGTKHDV
maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2. Please refer to QE_ENET10 in the device
errata document. UCC1 does meet tSKRGTKHDX minimum for rev2.1 silicon.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 18 shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT
tRGTH
GTX_CLK
(At Transmitter)
tSKRGTKHDX
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CTL
TXD[3:0]
TXD[8:5]
TXD[7:4]
TXD[4]
TXEN
TXD[9]
TXERR
tSKRGTKHDX
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[3:0] RXD[7:4]
tSKRGTKHDX
RX_CTL
RXD[4]
RXDV
RXD[9]
RXERR
tSKRGTKHDX
RX_CLK
(At PHY)
Figure 18. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
GMII, RGMII, TBI and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller
(10/100/1000 Mbps)— GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics.”
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics
for MDIO and MDC are provided in Table 35.
Table 35. MII Management DC Electrical Characteristics when powered at 3.3V
Parameter
Supply voltage (3.3 V)
Symbol
Conditions
Min
Max
Unit
OVDD
—
2.97
3.63
V
Output high voltage
VOH
IOH = -1.0 mA
OVDD = Min
2.10
OVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
OVDD = Min
GND
0.50
V
Input high voltage
VIH
2.00
—
V
—
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
35
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Table 35. MII Management DC Electrical Characteristics when powered at 3.3V (continued)
Input low voltage
VIL
—
—
0.80
V
Input current
IIN
0 V ≤ VIN ≤ OVDD
—
±10
μA
8.3.2
MII Management AC Electrical Specifications
Table 36 provides the MII management AC timing specifications.
Table 36. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V ± 10%
Symbol1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
—
2.5
—
MHz
2
MDC period
tMDC
—
400
—
ns
MDC clock pulse width high
tMDCH
32
—
—
ns
MDC to MDIO delay
tMDTKHDX
tMDTKHDV
10
—
—
—
110
ns
MDIO to MDC setup time
tMDRDVKH
10
—
—
ns
MDIO to MDC hold time
tMDRDXKH
0
—
—
ns
MDC rise time
tMDCR
—
—
10
ns
MDC fall time
tMDHF
—
—
10
ns
Parameter/Condition
3
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data
outputs (D) are invalid (X) or data hold time. Also, tMDRDVKH symbolizes management data timing (MD) with respect
to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high
(H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is
8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz
and the minimum frequency is 1.7 MHz).
3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a
ce_clk of 300 MHz, the delay is 63 ns).
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Freescale Semiconductor
Local Bus
Figure 19 shows the MII management AC timing diagram.
tMDCR
tMDC
MDC
tMDHF
tMDCH
MDIO
(Input)
tMDRDVKH
tMDRDXKH
MDIO
(Output)
tMDTKHDX
Figure 19. MII Management Interface Timing Diagram
8.3.3
IEEE Std. 1588™ Timer AC Specifications
Table 37 provides the IEEE Std. 1588 timer AC specifications.
Table 37. 1588 Timer AC Specifications
Parameter
Symbol
Min
Max
Unit
Notes
Timer clock cycle time
tTMRCK
0
70
MHz
1
Input Setup to timer clock
tTMRCKS
—
—
—
2,3
Input Hold from timer clock
tTMRCKH
—
—
—
2,3
Output clock to output valid
tGCLKNV
0
6
ns
Timer alarm to output valid
tTMRAL
—
—
—
2
Notes:
1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected. Min and
Max requirement for both rtc_clock and tmr_clock are the same.
2. These are asynchronous signals.
3. Inputs need to be stable at least one TMR clock.
9
Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8358E.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
37
Local Bus
9.1
Local Bus DC Electrical Characteristics
Table 38 provides the DC electrical characteristics for the local bus interface.
Table 38. Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
High-level output voltage,
IOH = –100 μA
VOH
OV DD – 0.4
—
V
Low-level output voltage,
IOL = 100 μA
VOL
—
0.2
V
IIN
—
±10
μA
Input current
9.2
Local Bus AC Electrical Specifications
Table 39 describes the general timing parameters of the local bus interface of the device.
Table 39. Local Bus General Timing Parameters—DLL Enabled
Symbol1
Min
Max
Unit
Notes
tLBK
7.5
—
ns
2
Input setup to local bus clock (except LUPWAIT)
tLBIVKH1
1.7
—
ns
3, 4
LUPWAIT input setup to local bus clock
tLBIVKH2
1.9
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
tLBIXKH1
1.0
—
ns
3, 4
LUPWAIT Input hold from local bus clock
tLBIXKH2
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3.0
—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
Local bus clock to LALE rise
tLBKHLR
—
4.5
ns
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKHOV1
—
4.5
ns
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—
4.5
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—
4.5
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
tLBKHOX1
1.0
—
ns
3
Output hold from local bus clock for LAD/LDP
tLBKHOX2
1.0
—
ns
3
Parameter
Local bus cycle time
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Freescale Semiconductor
Local Bus
Table 39. Local Bus General Timing Parameters—DLL Enabled (continued)
Parameter
Local bus clock to output high impedance for LAD/LDP
Symbol1
Min
Max
Unit
tLBKHOZ
—
3.8
ns
Notes
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to
go high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to rising edge of LSYNC_IN.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 × OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10pF less than
the load on LAD output pins.
6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10pF less than the
load on LAD output pins.
7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output
pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Table 40 describes the general timing parameters of the local bus interface of the device.
Table 40. Local Bus General Timing Parameters—DLL Bypass Mode
Symbol1
Min
Max
Unit
Notes
tLBK
15
—
ns
2
Input setup to local bus clock
tLBIVKH
7
—
ns
3, 4
Input hold from local bus clock
tLBIXKH
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3
—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
Local bus clock to output valid
tLBKHOV
—
3
ns
3
Parameter
Local bus cycle time
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
39
Local Bus
Table 40. Local Bus General Timing Parameters—DLL Bypass Mode (continued)
Parameter
Local bus clock to output high impedance for LAD/LDP
Symbol1
Min
Max
Unit
tLBKHOZ
—
4
ns
Notes
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10pF less than
the load on LAD output pins.
6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10pF less than the
load on LAD output pins.
7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output
pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
9. DLL bypass mode is not recommended for use at frequencies above 66MHz.
Figure 20 provides the AC test load for the local bus.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 20. Local Bus C Test Load
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
40
Freescale Semiconductor
Local Bus
Figure 21 through Figure 26 show the local bus signals.
LSYNC_IN
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE/
tLBKHOV
tLBKHOX
tLBKHOV
tLBKHOZ
tLBKHOX
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV
tLBKHOZ
tLBKHOX
Output (Address) Signal:
LAD[0:31]
tLBKHLR
tLBOTOT
LALE
Figure 21. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
41
Local Bus
LCLK[n]
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH
tLBIXKH
tLBIVKH
Input Signal:
LGTA
tLBIXKH
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE/
tLBKHOV
tLBKHOV
tLBKHOZ
Output Signals:
LAD[0:31]/LDP[0:3]
tLBOTOT
LALE
Figure 22. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
LSYNC_IN
T1
T3
tLBKHOV1
tLBKHOZ1
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIVKH2
tLBIXKH2
UPM Mode Input Signal:
LUPWAIT
tLBIVKH1
tLBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV1
tLBKHOZ1
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
42
Freescale Semiconductor
Local Bus
LCLK
T1
T3
tLBKHOV
tLBKHOZ
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIVKH
tLBIXKH
UPM Mode Input Signal:
LUPWAIT
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBKHOV
tLBIXKH
tLBKHOZ
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
43
Local Bus
LCLK
T1
T2
T3
T4
tLBKHOV
tLBKHOZ
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIVKH
tLBIXKH
UPM Mode Input Signal:
LUPWAIT
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBKHOV
tLBIXKH
tLBKHOZ
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
44
Freescale Semiconductor
JTAG
LSYNC_IN
T1
T2
T3
T4
tLBKHOZ1
tLBKHOV1
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH2
tLBIVKH2
UPM Mode Input Signal:
LUPWAIT
tLBIXKH1
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ1
tLBKHOV1
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)
10 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface
of the MPC8358E.
10.1
JTAG DC Electrical Characteristics
Table 41 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the device.
Table 41. JTAG interface DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = -6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.5
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ OVDD
—
±10
μA
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
45
JTAG
This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the
device.
Table 42 provides the JTAG AC timing specifications as defined in Figure 28 through Figure 31.
Table 42. JTAG AC Timing Specifications (Independent of CLKIN)1
At recommended operating conditions (see Table 2).
Symbol 2
Min
Max
Unit
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
JTAG external clock cycle time
tJTG
30
—
ns
JTAG external clock duty cycle
tJTKHKL/tJTG
45
55
%
JTAG external clock rise and fall times
tJTGR & tJTGF
0
2
ns
tTRST
25
—
ns
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
4
—
—
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
10
—
—
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
2
11
11
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
2
—
—
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
2
19
9
Parameter
TRST assert time
Notes
3
ns
Input setup times:
Input hold times:
4
ns
Valid times:
4
ns
Output hold times:
5
ns
5
ns
5, 6
6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see Figure 20). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
(V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K)
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Freescale Semiconductor
JTAG
Figure 27 provides the AC test load for TDO and the boundary-scan outputs of the device.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 27. AC Test Load for the JTAG Interface
Figure 28 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
tJTGR
tJTKHKL
tJTGF
tJTG
VM = Midpoint Voltage (OVDD/2)
Figure 28. JTAG Clock Input Timing Diagram
Figure 29 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD /2)
Figure 29. TRST Timing Diagram
Figure 30 provides the boundary-scan timing diagram.
JTAG
External Clock
VM
VM
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OV DD/2)
Figure 30. Boundary-Scan Timing Diagram
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
47
I2C
Figure 31 provides the test access port timing diagram.
JTAG
External Clock
VM
VM
tJTIVKH
tJTIXKH
Input
Data Valid
TDI, TMS
tJTKLOV
tJTKLOX
Output Data Valid
TDO
tJTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 31. Test Access Port Timing Diagram
11 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8358E.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
48
Freescale Semiconductor
I2C
11.1
I2C DC Electrical Characteristics
Table 43 provides the DC electrical characteristics for the I2C interface of the device.
Table 43. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7 × OV DD
OVDD + 0.3
V
Input low voltage level
VIL
–0.3
0.3 × OV DD
V
Low level output voltage
VOL
0
0.4
V
1
Output fall time from VIH(min) to VIL(max) with a
bus capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1 × CB
250
ns
2
Pulse width of spikes which must be suppressed
by the input filter
tI2KHKL
0
50
ns
3
Capacitance for each I/O pin
CI
—
10
pF
Input current
(0 V ≤VIN ≤ OV DD)
IIN
—
±10
μA
4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for information on the
digital filter used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
11.2
I2C AC Electrical Specifications
Table 44 provides the AC timing parameters for the I2C interface of the device.
Table 44. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 43).
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
1.3
—
μs
High period of the SCL clock
tI2CH
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs
Hold time (repeated) START condition (after this period,
the first clock pulse is generated)
tI2SXKL
0.6
—
μs
Data setup time
tI2DVKH
100
—
νσ
—
02
—
0.9 3
20 + 0.1 Cb 4
300
Parameter
Data hold time:
μs
tI2DXKL
CBUS compatible masters
I2C bus devices
Rise time of both SDA and SCL signals
tI2CR
ns
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
49
I2C
Table 44. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 43).
Symbol1
Min
Max
Unit
tI2CF
20 + 0.1 Cb 4
300
ns
Set-up time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1 × OV DD
—
V
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
0.2 × OV DD
—
V
Parameter
Fall time of both SDA and SCL signals
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to
the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the
time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going
to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the
stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or
setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
Figure 32 provides the AC test load for the I2C.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 32. I2C AC Test Load
Figure 33 shows the AC timing diagram for the I2C bus.
SDA
tI2CF
tI2DVKH
tI2CL
tI2KHKL
tI2SXKL
tI2CF
tI2CR
SCL
tI2SXKL
S
tI2CH
tI2DXKL
tI2SVKH
Sr
tI2PVKH
P
S
Figure 33. I2C Bus AC Timing Diagram
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PCI
12 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8358E.
12.1
PCI DC Electrical Characteristics
Table 45 provides the DC electrical characteristics for the PCI interface of the device.
Table 45. PCI DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
VIH
VOUT ≥ VOH (min) or
0.5 × OVDD
OVDD + 0.5
V
Low-level input voltage
VIL
VOUT ≤ VOL (max)
-0.5
0.3 × OVDD
V
High-level output voltage
VOH
IOH = –500 μA
0.9 × OVDD
—
V
Low-level output voltage
VOL
IOL = 1500 μA
—
0.1 × OVDD
V
—
±10
μA
Input current
IIN
0V≤
VIN1
≤ OVDD
Notes:
1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2.
12.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the device. Note that the
PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the device is
configured as a host or agent device. Table 46 provides the PCI AC timing specifications at 66 MHz.
.
Table 46. PCI AC Timing Specifications at 66 MHz
Symbol 1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—
6.0
ns
2
Output hold from Clock
tPCKHOX
1
—
ns
2
Clock to output high impedance
tPCKHOZ
—
14
ns
2, 3
Input setup to Clock
tPCIVKH
3.0
—
ns
2, 4
Input hold from Clock
tPCIXKH
0.3
—
ns
2, 4
Parameter
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional
block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F)
going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
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PCI
Table 47. PCI AC Timing Specifications at 33 MHz
Symbol 1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—
11
ns
2
Output hold from Clock
tPCKHOX
2
—
ns
2
Clock to output high impedance
tPCKHOZ
—
14
ns
2, 3
Input setup to Clock
tPCIVKH
7.0
—
ns
2, 4
Input hold from Clock
tPCIXKH
0.3
—
ns
2, 4
Parameter
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional
block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F)
going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
Figure 34 provides the AC test load for PCI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 34. PCI AC Test Load
Figure 35 shows the PCI input AC timing conditions.
CLK
tPCIVKH
tPCIXKH
Input
Figure 35. PCI Input AC Timing Measurement Conditions
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Timers
Figure 36 shows the PCI output AC timing conditions.
CLK
tPCKHOV
tPCKHOX
Output Delay
tPCKHOZ
High-Impedance
Output
Figure 36. PCI Output AC Timing Measurement Condition
13 Timers
This section describes the DC and AC electrical specifications for the timers of the MPC8358E.
13.1
Timers DC Electrical Characteristics
Table 48 provides the DC electrical characteristics for the device timer pins, including TIN, TOUT,
TGATE and RTC_CLK.
Table 48. Timers DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ OVDD
—
±10
μA
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GPIO
13.2
Timers AC Timing Specifications
Table 49 provides the timer input and output AC timing specifications.
Table 49. Timers Input AC Timing Specifications1
Characteristic
Symbol 2
Typ
Unit
tTIWID
20
ns
Timers inputs—minimum pulse width
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before
use by any external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper
operation.
Figure 37 provides the AC test load for the timers.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 37. Timers AC Test Load
14 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8358E.
14.1
GPIO DC Electrical Characteristics
Table 50 provides the DC electrical characteristics for the device GPIO.
Table 50. GPIO DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
1
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
1
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
1
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
1
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ OVDD
—
±10
μA
Note: This specification applies when operating from 3.3V supply.
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IPIC
14.2
GPIO AC Timing Specifications
Table 51 provides the GPIO input and output AC timing specifications.
Table 51. GPIO Input AC Timing Specifications1
Characteristic
Symbol 2
Typ
Unit
tPIWID
20
ns
GPIO inputs—minimum pulse width
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use
by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper
operation.
Figure 38 provides the AC test load for the GPIO.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Figure 38. GPIO AC Test Load
15 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the
MPC8358E.
15.1
IPIC DC Electrical Characteristics
Table 52 provides the DC electrical characteristics for the external interrupt pins of the IPIC.
Table 52. IPIC DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
2.0
OVDD + 0.3
V
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
±10
μA
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Notes:
1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts.
2. IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins.
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15.2
IPIC AC Timing Specifications
Table 53 provides the IPIC input and output AC timing specifications.
Table 53. IPIC Input AC Timing Specifications1
Characteristic
Symbol 2
Min
Unit
tPIWID
20
ns
IPIC inputs—minimum pulse width
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
2.IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by
any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation
when working in edge triggered mode.
16 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8358E.
16.1
SPI DC Electrical Characteristics
Table 54 provides the DC electrical characteristics for the device SPI.
Table 54. SPI DC Electrical Characteristics
Characteristic
16.2
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ OVDD
—
±10
μA
SPI AC Timing Specifications
Table 55 and provide the SPI input and output AC timing specifications.
Table 55. SPI AC Timing Specifications1
Symbol 2
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
tNIKHOX
tNIKHOV
0.4
—
—
8
ns
SPI outputs—Slave mode (external clock) delay
tNEKHOX
tNEKHOV
2
—
—
8
ns
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
8
—
ns
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0
—
ns
Characteristic
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SPI
Table 55. SPI AC Timing Specifications1
Symbol 2
Min
Max
Unit
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4
—
ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2
—
ns
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the
high state (H) until outputs (O) are valid (V).
Figure 39 provides the AC test load for the SPI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 39. SPI AC Test Load
Figure 40 through Figure 41 represent the AC timing from Table 55. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 40 shows the SPI timing in slave mode (external clock).
SPICLK (input)
Input Signals:
SPIMOSI
(See Note)
tNEIVKH
Output Signals:
SPIMISO
(See Note)
tNEIXKH
tNEKHOV
Note: The clock edge is selectable on SPI.
Figure 40. SPI AC Timing in Slave mode (External Clock) Diagram
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TDM/SI
Figure 41 shows the SPI timing in Master mode (internal clock).
SPICLK (output)
tNIIXKH
tNIIVKH
Input Signals:
SPIMISO
(See Note)
tNIKHOV
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 41. SPI AC Timing in Master mode (Internal Clock) Diagram
17 TDM/SI
This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial
interface of the MPC8358E.
17.1
TDM/SI DC Electrical Characteristics
Table 56 provides the DC electrical characteristics for the device TDM/SI.
Table 56. TDM/SI DC Electrical Characteristics
Characteristic
17.2
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –2.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.5
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ OV DD
—
±10
μA
TDM/SI AC Timing Specifications
Table 57 provides the TDM/SI input and output AC timing specifications.
Table 57. TDM/SI AC Timing Specifications1
Symbol2
Min
Max3
Unit
TDM/SI outputs—External clock delay
tSEKHOV
2
10
ns
TDM/SI outputs—External clock high impedance
tSEKHOX
2
10
ns
TDM/SI inputs—External clock input setup time
tSEIVKH
5
—
ns
Characteristic
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TDM/SI
Table 57. TDM/SI AC Timing Specifications1 (continued)
Characteristic
TDM/SI inputs—External clock input hold time
Symbol2
Min
Max3
Unit
tSEIXKH
2
—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tSEKHOX symbolizes the TDM/SI outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes
from the high state (H) until outputs (O) are invalid (X).
3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and
SITXCEI[TXCEIx]. See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more
details.
Figure 42 provides the AC test load for the TDM/SI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 42. TDM/SI AC Test Load
Figure 43 represents the AC timing from Table 55. Note that although the specifications generally
reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the
active edge.
Figure 43 shows the TDM/SI timing with external clock.
TDM/SICLK (input)
Input Signals:
TDM/SI
(See Note)
Output Signals:
TDM/SI
(See Note)
tSEIVKH
tSEIXKH
tSEKHOV
tSEKHOX
Note: The clock edge is selectable on TDM/SI
Figure 43. TDM/SI AC Timing (External Clock) Diagram
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UTOPIA/POS
18 UTOPIA/POS
This section describes the DC and AC electrical specifications for the UTOPIA/POS of the MPC8358E.
18.1
UTOPIA/POS DC Electrical Characteristics
Table 58 provides the DC electrical characteristics for the device UTOPIA.
Table 58. UTOPIA DC Electrical Characteristics
Characteristic
18.2
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ OVDD
—
±10
μA
Utopia/POS AC Timing Specifications
Table 59 provides the UTOPIA input and output AC timing specifications.
Table 59. UTOPIA AC Timing Specifications1
Symbol 2
Min
Max
Unit
UTOPIA outputs—Internal clock delay
tUIKHOV
0
11.5
ns
UTOPIA outputs—External clock delay
tUEKHOV
1
11.6
ns
UTOPIA outputs—Internal clock High Impedance
tUIKHOX
0
8.0
ns
UTOPIA outputs—External clock High Impedance
tUEKHOX
1
10.0
ns
UTOPIA inputs—Internal clock input setup time
tUIIVKH
6
—
ns
UTOPIA inputs—External clock input setup time
tUEIVKH
4.2
—
ns
UTOPIA inputs—Internal clock input Hold time
tUIIXKH
2.4
—
ns
UTOPIA inputs—External clock input hold time
tUEIXKH
1
—
ns
Characteristic
Notes
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA
outputs internal timing (UI) for the time tUTOPIA memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).
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HDLC, BISYNC, Transparent, and Synchronous UART
Figure 44 provides the AC test load for the UTOPIA.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 44. UTOPIA AC Test Load
Figure 45 and Figure 46 represent the AC timing from Table 55. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 45 shows the UTOPIA timing with external clock.
UtopiaCLK (input)
Input Signals:
UTOPIA
tUEIVKH
tUEIXKH
tUEKHOV
Output Signals:
UTOPIA
tUEKHOX
Figure 45. UTOPIA AC Timing (External Clock) Diagram
Figure 46 shows the UTOPIA timing with internal clock.
UtopiaCLK (output)
Input Signals:
UTOPIA
Output Signals:
UTOPIA
tUIIVKH
tUIIXKH
tUIKHOV
tUIKHOX
Figure 46. UTOPIA AC Timing (Internal Clock) Diagram
19 HDLC, BISYNC, Transparent, and Synchronous UART
This section describes the DC and AC electrical specifications for the high level data link control (HDLC),
BiSync, transparent, and synchronous UART protocols of the MPC8358E.
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HDLC, BISYNC, Transparent, and Synchronous UART
19.1
HDLC, BISYNC, Transparent, and Synchronous UART DC
Electrical Characteristics
Table 60 provides the DC electrical characteristics for the device HDLC, BISYNC, transparent, and
synchronous UART protocols.
Table 60. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics
Characteristic
19.2
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –2.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.5
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ OVDD
—
±10
μA
HDLC, BISYNC, Transparent, and Synchronous UART AC Timing
Specifications
Table 61 and Table 62 provide the input and output AC timing specifications for HDLC, BiSync,
transparent, and synchronous UART protocols.
Table 61. HDLC, BISYNC, and Transparent AC Timing Specifications1
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tHIKHOV
0
11.2
ns
Outputs—External clock delay
tHEKHOV
1
10.8
ns
Outputs—Internal clock High Impedance
tHIKHOX
-0.5
5.5
ns
Outputs—External clock High Impedance
tHEKHOX
1
8
ns
Inputs—Internal clock input setup time
tHIIVKH
8.5
—
ns
Inputs—External clock input setup time
tHEIVKH
4
—
ns
Inputs—Internal clock input Hold time
tHIIXKH
1.4
—
ns
Inputs—External clock input hold time
tHEIXKH
1
—
ns
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high
state (H) until outputs (O) are invalid (X).
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Table 62. Synchronous UART AC Timing Specifications1
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tUAIKHOV
0
11.3
ns
Outputs—External clock delay
tUAEKHOV
1
14
ns
Outputs—Internal clock High Impedance
tUAIKHOX
0
11
ns
Outputs—External clock High Impedance
tUAEKHOX
1
14
ns
Inputs—Internal clock input setup time
tUAIIVKH
6
—
ns
Inputs—External clock input setup time
tUAEIVKH
8
—
ns
Inputs—Internal clock input Hold time
tUAIIXKH
1
—
ns
Inputs—External clock input hold time
tUAEIXKH
1
—
ns
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high
state (H) until outputs (O) are invalid (X).
Figure 47 provides the AC test load.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 47. AC Test Load
19.3
AC Test Load
Figure 48 and Figure 49 represent the AC timing from Table 61 and Table 62. Note that although the
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
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HDLC, BISYNC, Transparent, and Synchronous UART
Figure 48 shows the timing with external clock.
Serial CLK (input)
Input Signals:
tHEIXKH
tHEIVKH
(See Note)
tHEKHOV
Output Signals:
(See Note)
tHEKHOX
Note: The clock edge is selectable.
Figure 48. AC Timing (External Clock) Diagram
Figure 49 shows the timing with internal clock.
Serial CLK (output)
Input Signals:
tHIIVKH
tHIIXKH
(See Note)
tHIKHOV
Output Signals:
(See Note)
tHIKHOX
Note: The clock edge is selectable.
Figure 49. AC Timing (Internal Clock) Diagram
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USB
20 USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8358E.
20.1
USB DC Electrical Characteristics
Table 63 provides the DC electrical characteristics for the USB interface.
Table 63. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
High-level output voltage,
IOH = –100 μA
VOH
OVDD – 0.4
—
V
Low-level output voltage,
IOL = 100 μA
VOL
—
0.2
V
IIN
—
±10
μA
Input current
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and
Table 2.
20.2
USB AC Electrical Specifications
Table 64 describes the general timing parameters of the USB interface of the device.
Table 64. USB General Timing Parameters
Symbol 1
Min
Max
Unit
Notes
usb clock cycle time
tUSCK
20.83
—
ns
full speed 48MHz
usb clock cycle time
tUSCK
166.67
—
ns
low speed 6MHz
tUSTSPN
—
5
ns
skew among RXP, RXN and RXD
tUSRSPND
—
10
ns
full speed transitions
skew among RXP, RXN and RXD
tUSRPND
—
100
ns
low speed transitions
Parameter
skew between TXP and TXN
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(state)
(signal) for receive signals and t(First two letters of functional block)(state)(signal) for transmit signals. For example,
tUSRSPND symbolizes usb timing (US) for the usb receive signals skew (RS) among RXP, RXN, and RXD
(PND). Also, tUSTSPN symbolizes usb timing (US) for the usb transmit signals skew (TS) between TXP and
TXN (PN).
2.Skew measurements are done at OVDD/2 of the rising or falling edge of the signals.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Package and Pin Listings
Figure 50 provide the AC test load for the USB.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 50. USB AC Test Load
21 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8358E is available in
a plastic ball grid array (PBGA), see Section 21.1, “Package Parameters for the PBGA Package,” and
Section 21.2, “Mechanical Dimensions of the PBGA Package,” for information on the package.
21.1
Package Parameters for the PBGA Package
The package parameters for rev 2.0 silicon are as provided in the following list. The package type is 29
mm x 29 mm, 668 plastic ball grid array (PBGA).
Package outline
29 mm x 29 mm
Interconnects
668
Pitch
1.00 mm
Module height (typical)
1.46 mm
Solder Balls
62 Sn/36 Pb/2 Ag (ZQ package)
95.5 Sn/0.5 Cu/4Ag (VR package)
Ball diameter (typical)
0.64 mm
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Package and Pin Listings
21.2
Mechanical Dimensions of the PBGA Package
Figure 51 depicts the mechanical dimensions and bottom surface nomenclature of the 668-PBGA package.
Figure 51. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
Notes:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
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Package and Pin Listings
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Parallelism measurement must exclude any effect of mark on top surface of package.
6. Distance from the seating plane to the encapsulant material.
21.3
Pinout Listings
Table 65 shows the pin list of the MPC8358E PBGA package.
Table 65. MPC8358E PBGA Pinout Listing
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
DDR SDRAM Memory Controller Interface
MEMC_MDQ[0:63]
AD20, AG24, AF24, AH24, AF23, AE22, AH26, AD21,
AH25, AD22, AF27, AB24, AG25, AC22, AE25, AC24,
AD25, AB25, AC25, AG28, AD26, AE23, AG26, AC26,
AD27, V25, AA28, AA25, Y26, W27, U24, W24, E28,
H24, E26, D25, G27, H25, G26, F26, F27, F25, D26, F24,
G25, E27, D27, C28, C27, F22, B26, F21, B28, E22, D24,
C24, A25, E20, F20, D20, A23, C21, C23, E19
I/O
GVDD
MEMC_MECC[0:7]
N26, N24, J26, H28, N28, P24, L26, K24
I/O
GVDD
MEMC_MDM[0:8]
AG23, AD23, AE26, V28, G28, D28, D23, B24, U27
O
GVDD
MEMC_MDQS[0:8]
AH23, AH27, AF28, T28, H26, E25, B25, A24, R28
I/O
GVDD
MEMC_MBA[0:2]
V26, W28, Y28
O
GVDD
MEMC_MA[0:14]
L25, M25, M24, K28, P28, T24, M27, R25, P25, L28,
U26, M28, L27, K27, H27
O
GVDD
MEMC_MODT[0:3]
AE21, AC19, E23, B23
GVDD
6
MEMC_MWE
R27
O
GVDD
MEMC_MRAS
W25
O
GVDD
MEMC_MCAS
R24
O
GVDD
MEMC_MCS[0:3]
T26, U28, J25, F28
O
GVDD
MEMC_MCKE[0:1]
AD24, AE28
O
GVDD
MEMC_MCK[0:5]
AG22, AG27, A26, C26, P26, E21
O
GVDD
MEMC_MCK[0:5]
AF22, AF26, A27, B27, N27, D22
O
GVDD
MDIC[0:1]
F19, AA27
I/O
GVDD
11
2
3
PCI
PCI_INTA/
PF[5]
R3
I/O
LVDD2
PCI_RESET_OUT/
PF[6]
P6
I/O
LVDD2
PCI_AD[0:31]/
PG[0:31]
AB5, AC5, AG1, AA5, AF2, AD4, Y6, AF1, AE2, AC4,
AD3, AE1, Y4, AC3, AD2, AD1, AB2, Y3, AA1, Y1, W1,
V6, W3, V4, T5, W2, V5, V1, U4, V2, U2, T2
I/O
LVDD2
PCI_C_BE[0:3]/
PF[7:10]
Y5, AC2, Y2, U5
I/O
OVDD
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Package and Pin Listings
Table 65. MPC8358E PBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
PCI_PAR/
PF[11]
AA4
I/O
OVDD
PCI_FRAME/
PF[12]
W4
I/O
OVDD
5
PCI_TRDY/
PF[13]
W5
I/O
OVDD
5
PCI_IRDY/
PF[14]
AB3
I/O
OVDD
5
PCI_STOP/
PF[15]
AB1
I/O
OVDD
5
PCI_DEVSEL/
PF[16]
AA2
I/O
OVDD
5
PCI_IDSEL/
PF[17]
U6
I/O
OVDD
PCI_SERR/
PF[18]
AC1
I/O
OVDD
5
PCI_PERR/
PF[19]
W6
I/O
OVDD
5
PCI_REQ[0:2]/
PF[20:22]
R2, T4, U1
I/O
LVDD2
PCI_GNT[0:2]/
PF[23:25]
T3, R5, T1
I/O
LVDD2
PCI_MODE
AE5
I
OVDD
M66EN/
CE_PF[4]
AH3
I/O
OVDD
Local Bus Controller Interface
LAD[0:31]
AC11, AE10, AD10, AD11, AE11, AG11, AH11, AH12,
AG12, AF12, AD12, AE12, AC12, AH13, AG13, AF13,
AE13, AH14, AD13, AG14, AF14, AH15, AE14, AG15,
AC13, AD14, AC14, AH16, AC15, AG16, AE15, AF16
I/O
OVDD
LDP[0:3]
AD15, AG17, AC16, AF17
I/O
OVDD
LA[27:31]
AH17, AD16, AH18, AG18, AE17
O
OVDD
LCS[0:5]
AD18, AH20, AG20, AE19, AC18, AH21
O
OVDD
LWE[0:3]
AG21, AH22, AC20, AD19
O
OVDD
LBCTL
AF18
O
OVDD
LALE
AF10
O
OVDD
LGPL0/
LSDA10/
cfg_reset_source0
AC17
I/O
OVDD
LGPL1/
LSDWE/
cfg_reset_source1
AD17
I/O
OVDD
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Package and Pin Listings
Table 65. MPC8358E PBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
LGPL2/
LSDRAS/
LOE
AH19
O
OVDD
LGPL3/
LSDCAS/
cfg_reset_source2
AE18
I/O
OVDD
LGPL4/
LGTA/
LUPWAIT/
LPBSE
AG19
I/O
OVDD
LGPL5/
cfg_clkin_div
AF19
I/O
OVDD
LCKE
AD8
O
OVDD
LCLK[0]
AC9
O
OVDD
LCLK[1]/
LCS[6]
AG6
O
OVDD
LCLK[2]/
LCS[7]
AE7
O
OVDD
LSYNC_OUT
AG4
O
OVDD
LSYNC_IN
AC8
I
OVDD
Notes
Programmable Interrupt Controller
MCP_OUT
AG3
O
OVDD
IRQ0/
MCP_IN
AH4
I
OVDD
IRQ[1:2]
AG5, AH5
I/O
OVDD
IRQ[3]/
CORE_SRESET
AD7
I/O
OVDD
IRQ[4:5]
AC7, AD6
I/O
OVDD
IRQ[6:7]
AC6, AC10
I/O
OVDD
2
DUART
UART1_SOUT
AE3
O
OVDD
UART1_SIN
AE4
I/O
OVDD
UART1_CTS
AG2
I/O
OVDD
UART1_RTS
AA6
O
OVDD
I2C
Interface
IIC1_SDA
AB6
I/O
OVDD
2
IIC1_SCL
AD5
I/O
OVDD
2
IIC2_SDA
AF3
I/O
OVDD
2
IIC2_SCL
AH2
I/O
OVDD
2
I/O
LVDD0
QUICCTM Engine
CE_PA[0]
F6
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Package and Pin Listings
Table 65. MPC8358E PBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
I/O
OVDD
CE_PA[1:2]
A22, C20
CE_PA[3:7]
C3, D3, C2, D2, B1
I/O
LVDD0
CE_PA[8]
F18
I/O
OVDD
CE_PA[9:12]
E3, C1, B2, D1
I/O
LVDD0
CE_PA[13:14]
B21, D19
I/O
OVDD
CE_PA[15]
E4
I/O
LVDD0
CE_PA[16]
E18
I/O
OVDD
CE_PA[17:21]
M2, N5, N3, N4, N2
I/O
LVDD1
CE_PA[22]
F17
I/O
OVDD
CE_PA[23:26]
N1, P1, P2, P4
I/O
LVDD1
CE_PA[27:28]
A21, E17
I/O
OVDD
CE_PA[29]
P5
I/O
LVDD1
CE_PA[30]
B20
I/O
OVDD
CE_PA[31]
M4
I/O
LVDD1
CE_PB[0:27]
D18, C18, A20, B19, F16, E16, B18, A19, C17, D16, E15,
A18, F15, B17, A17, D15, B16, A16, C15, B15, A15, E14,
F14, D14, C14, B14, A14, E13
I/O
OVDD
CE_PC[0:1]
F13, D13
I/O
OVDD
CE_PC[2:3]
N6, M1
I/O
LVDD1
CE_PC[4:6]
C13, B13, A13
I/O
OVDD
CE_PC[7]
R1
I/O
LVDD2
CE_PC[8:9]
F4, E2
I/O
LVDD0
CE_PC[10:30]
D12, E12, F12, B12, A12, A11, B11, K5, K6, J1, J2, J3,
H1, J4, H6, J5, M5, L1, M3, F5, B22
I/O
OVDD
CE_PD[0:27]
H2, H3, G6, G1, H4, H5, G2, G3, F1, J6, F2, G4, E1, G5,
B3, A3, D4, C4, A2, E5, B4, F8, A4, D5, C5, B5, E6, E8
I/O
OVDD
CE_PE[0:31]
D8, A7, A5, E7, D6, F9, B6, A6, D7, C7, B7, E9, C8, E11,
C11, F11, A10, B10, C10, E10, D10, A9, B9, C9, D9, F10,
A8, B8, M6, K1, L3, L2
I/O
OVDD
CE_PF[0:3]
L6, K2, L5, K4
I/O
OVDD
Notes
Clocks
PCI_CLK[0]/
PF[26]
R6
I/O
LVDD2
PCI_CLK[1:2]/
PF[27:28]
U3, T6
I/O
OVDD
CLKIN
AH6
I
OVDD
PCI_SYNC_IN
AF7
I
OVDD
PCI_SYNC_OUT/
PF[29]
AF6
I/O
OVDD
I
OVDD
3
JTAG
TCK
AD9
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Package and Pin Listings
Table 65. MPC8358E PBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
TDI
AE8
I
OVDD
4
TDO
AG7
O
OVDD
3
TMS
AH7
I
OVDD
4
TRST
AG8
I
OVDD
4
Test
TEST
AF9
I
OVDD
TEST_SEL
AE27
I
GVDD
O
OVDD
9
PMC
QUIESCE
AF4
System Control
PORESET
AE9
I
OVDD
HRESET
AG9
I/O
OVDD
1
SRESET
AH10
I/O
OVDD
2
Thermal Management
THERM0
K25
I
GVDD
THERM1
AA26
I
GVDD
Power and Ground Signals
AVDD1
AF8
Power for
LBIU DLL
(1.2 V)
AVDD1
AVDD2
AH8
Power for
CE PLL
(1.2 V)
AVDD2
AVDD5
AB26
Power for
e300 PLL
(1.2 V)
AVDD5
AVDD6
AH9
Power for
system
PLL (1.2
V)
AVDD6
GND
C16, D11, D21, E24, F7, J10, J12, J15, J16, J17, J28,
K11, K13, K14, K17, K18, L4, L9, L11, L12, L13, L14,
L15, L16, L17, L18, L19, L24, M10, M11, M14, M15, M18,
M19, N11, N18, N25, P9, P11, P18, P19, R9, R11, R14,
R15, R18, R19, R26, T10, T11, T14, T15, T18, T25, U10,
U11, U18, V9, V11, V14, V15, V18, V24, V27, W18, W19,
Y11, Y14, Y18, Y19, Y25, Y27, AB4, AB27, AC27, AE20,
AE24, AF5, AF15, AG10
—
—
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Package and Pin Listings
Table 65. MPC8358E PBGA Pinout Listing (continued)
Signal
Power
Supply
Package Pin Number
Pin Type
Notes
GVDD
C19, C22, C25, G24, J18, J19, J20, J24, K19, K20, K26,
L20, M20, M26, N19, N20, P20, P27, R20, T19, T20, T27,
U19, U20, U25, V19, V20, W20, W26, Y20, AA24, AB28,
AC21, AC28, AD28, AF21, AF25
Power for
DDR
DRAM
I/O
Voltage
(2.5 V or
1.8 V)
LVDD0
F3, J9
LVDD0
LVDD1
P3, P10
LVDD1
10
LVDD2
R4, R10
LVDD2
10
VDD
M12, M13, M16, M17, N10, N12, N13, N14, N15, N16,
N17, P12, P13, P14, P15, P16, P17, R12, R13, R16,
R17, T12, T13, T16, T17, U12, U13, U14, U15, U16, U17,
V12, V13, V16, V17, W11, W12, W13, W15, W16, W17,
Y16, Y17
Power for
Core
(1.2 V)
VDD
OVDD
C6, C12, D17, J11, J13, J14, K3, K9, K10, K12, K15,
K16, L10, M9, N9, T9, U9, V3, V10, W9, W10, W14, Y9,
Y10, Y12, Y13, Y15, AA3, AE6, AE16, AF11, AF20
PCI,
10/100
Ethernet,
and other
Standard
(3.3 V)
OVDD
MVREF1
J27
I
DDR
Referen
ce
Voltage
MVREF2
Y24
I
DDR
Referen
ce
Voltage
—
—
GVDD
No Connect
NC
F23, G23, H23, J23, K23, L23, M23, N23, P23, R23, T23,
U23, V23, W23, Y23, AA23, AB23, AC23
—
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5.This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
7. This pin must always be tied to GND.
8. This pin must always be left not connected.
9. This pin must always be tied to GVDD.
10. Refers to MPC8360E PowerQUICC II™ Pro Integrated Communications Processor Reference Manual section on "RGMII
Pins" for information about the two UCC2 Ethernet interface options.
11. It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω
resistor for DDR2.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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73
Clocking
22 Clocking
Figure 52 shows the internal distribution of clocks within the MPC8358E.
MPC8358E
e300 core
Core PLL
core_clk
csb_clk
ce_clk to QUICC Engine block
DDRC
MEMC1_MCK[0:5]
/2
MEMC1_MCK[0:5]
DDRC
Memory
Device
ddr1_clk
QUICC
Engine
PLL
System
PLL
Clock
Unit
lb_clk
/n
LCLK[0:2]
LBIU
DLL
LSYNC_OUT
csb_clk to rest
of the device
Local Bus
Memory
Device
LSYNC_IN
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI Clock
Divider
PCI_CLK_OUT[0:2]
Figure 52. MPC8358E Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary
clock input also depends on whether PCI clock outputs are selected with RCWH[PCICKEN]. When the
device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is selected
(RCWH[PCICKEN] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and
the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn]
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
74
Freescale Semiconductor
Clocking
parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.The
OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn respectively.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the CLKIN and the CFG_CLKIN_DIV signals should be tied to GND.
When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is
disabled (RCWH[PCICKEN] = 0), clock distribution and balancing done externally on the board.
Therefore, PCI_SYNC_IN is the primary input clock.
As shown in , the primary clock input (frequency) is multiplied by the QUICC Engine block phase-locked
loop (PLL), the system PLL, and the clock unit to create the QUICC Engine clock (ce_clk), the coherent
system bus clock (csb_clk), the internal DDRC1 controller clock (ddr1_clk), and the internal clock for the
local bus interface unit and DDR2 memory controller (lb_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency; in PCI agent
mode, CFG_CLKIN_DIV must be pulled down (low), so PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is
the PCI_CLK frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)
which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,
Clocking, and Initialization,” in the MPC8360E Integrated Communications Processor Reference
Manual, Rev. 2 for more information on the clock subsystem.
The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF)
and the QUICC Engine PLL division factor (RCWL[CEPDF]) according to the following equation:
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
The internal ddr1_clk frequency is determined by the following equation:
ddr1_clk = csb_clk × (1 + RCWL[DDR1CM])
Note that the lb_clk clock frequency (for DDRC2) is determined by RCWL[LBCM]. The internal
ddr1_clk frequency is not the external memory bus frequency; ddr1_clk passes through the DDRC1 clock
divider (÷2) to create the differential DDRC1 memory bus clock outputs (MEMC1_MCK and
MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk.
The internal lb_clk frequency is determined by the following equation:
lb_clk = csb_clk × (1 + RCWL[LBCM])
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Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock
divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock
divider ratio is controlled by LCCR[CLKDIV].
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset. Table 66 specifies which units have a configurable clock
frequency.
Table 66. Configurable Clock Units
Unit
csb_clk/3
Security Core
PCI and DMA complex
1
Default
Frequency
csb_clk
Options
Off, csb_clk 1, csb_clk/2,
csb_clk/3
Off, csb_clk
with limitation, only for slow csb_clk rates, up to 166MHz
Table 67 provides the operating frequencies for the PBGA package under recommended operating
conditions (see Table 2). All frequency combinations shown in the table below may not be available.
Maximum operating frequencies depend on the part ordered, see Section 26.1, “Part Numbers Fully
Addressed by this Document” for part ordering details and contact your Freescale Sales Representative or
authorized distributor for more information.
Table 67. Operating Frequencies for the PBGA Package
Characteristic 1
400 MHz
Unit
e300 core frequency (core_clk)
266–400
MHz
Coherent system bus frequency
(csb_clk)
133–266
MHz
266
MHz
100–133
MHz
Local bus frequency
(LCLKn) 3
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66.67
MHz
133
MHz
QUICC Engine frequency
(ce_clk)
DDR and DDR2 memory bus frequency
(MCLK) 2
Security core maximum internal operating frequency
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,
MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
2 The DDR data rate is 2x the DDR memory bus frequency.
3
The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the csb_clk frequency (depending on RCWL[LBCM]).
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22.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters. Table 68 shows the
multiplication factor encodings for the system PLL.
Table 68. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication
Factor
0000
× 16
0001
Reserved
0010
×2
0011
×3
0100
×4
0101
×5
0110
×6
0111
×7
1000
×8
1001
×9
1010
× 10
1011
× 11
1100
× 12
1101
× 13
1110
× 14
1111
× 15
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 69.
Table 69. System PLL VCO Divider
RCWL[SVCOD]
VCO Divider
00
4
01
8
10
2
11
Reserved
NOTE
The VCO divider must be set properly so that the system VCO frequency is
in the range of 600-1400 MHz.
The system VCO frequency is derived from the following equations:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
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System VCO Frequency = csb_clk × VCO divider
As described in Section 22, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 70
shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN
ratios.
Table 70. CSB Frequency Options
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at reset 1
SPMF
csb_clk :
Input Clock
Ratio 2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0010
2:1
Low
0011
3:1
Low
0100
4:1
Low
0101
5:1
Low
0110
6:1
Low
0111
Low
133
100
200
100
133
266
125
166
333
100
150
200
7:1
116
175
233
1000
8:1
133
200
266
Low
1001
9:1
150
225
300
Low
1010
10 : 1
166
250
333
Low
1011
11 : 1
183
275
Low
1100
12 : 1
200
300
Low
1101
13 : 1
216
325
Low
1110
14 : 1
233
Low
1111
15 : 1
250
Low
0000
16 : 1
266
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Table 70. CSB Frequency Options (continued)
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at reset 1
csb_clk :
Input Clock
Ratio 2
SPMF
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
High
0010
2:1
133
High
0011
3:1
100
200
High
0100
4:1
133
266
High
0101
5:1
166
333
High
0110
6:1
200
High
0111
7:1
233
High
1000
8:1
High
1001
9:1
High
1010
10 : 1
High
1011
11 : 1
High
1100
12 : 1
High
1101
13 : 1
High
1110
14 : 1
High
1111
15 : 1
High
0000
16 : 1
1
CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be
pulled down (low) in agent mode.
2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
22.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 71 shows the encodings for RCWL[COREPLL]. COREPLL values not listed
in Table 71 should be considered reserved.
Table 71. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO divider
n
PLL bypassed
(PLL off, csb_clk clocks core
directly)
PLL bypassed
(PLL off, csb_clk clocks core
directly)
0001
0
1:1
0001
0
1:1
÷2
÷4
0-1
2-5
6
nn
0000
00
01
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Clocking
Table 71. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO divider
0
1:1
0001
0
1:1
00
0001
1
1.5:1
01
0001
1
1.5:1
10
0001
1
1.5:1
11
0001
1
1.5:1
00
0010
0
2:1
01
0010
0
2:1
10
0010
0
2:1
11
0010
0
2:1
00
0010
1
2.5:1
01
0010
1
2.5:1
10
0010
1
2.5:1
11
0010
1
2.5:1
00
0011
0
3:1
01
0011
0
3:1
10
0011
0
3:1
11
0011
0
3:1
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
0-1
2-5
6
10
0001
11
NOTE
Core VCO frequency = Core frequency × VCO divider. VCO divider
(RCWL[COREPLL[0:1]]) must be set properly so that the core VCO
frequency is in the range of 800–1800 MHz. Having a core frequency below
the CSB frequency is not a possible option because the core frequency must
be equal to or greater than the CSB frequency.
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22.3
QUICC Engine PLL Configuration
The QUICC Engine PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and RCWL[CEVCOD]
parameters. Table 72 shows the multiplication factor encodings for the QUICC Engine PLL.
Table 72. QUICC Engine PLL Multiplication Factors
RCWL[CEPMF]
RCWL[CEPDF]
QUICC Engine PLL Multiplication
Factor = RCWL[CEPMF] /
(1+RCWL[CEPDF])
00000
0
× 16
00001
0
Reserved
00010
0
×2
00011
0
×3
00100
0
×4
00101
0
×5
00110
0
×6
00111
0
×7
01000
0
×8
01001
0
×9
01010
0
× 10
01011
0
× 11
01100
0
× 12
01101
0
× 13
01110
0
× 14
01111
0
× 15
10000
0
× 16
10001
0
× 17
10010
0
× 18
10011
0
× 19
10100
0
× 20
10101
0
× 21
10110
0
× 22
10111
0
× 23
11000
0
× 24
11001
0
× 25
11010
0
× 26
11011
0
× 27
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Clocking
Table 72. QUICC Engine PLL Multiplication Factors (continued)
RCWL[CEPMF]
RCWL[CEPDF]
QUICC Engine PLL Multiplication
Factor = RCWL[CEPMF] /
(1+RCWL[CEPDF])
11100
0
× 28
11101
0
× 29
11110
0
× 30
11111
0
× 31
00011
1
× 1.5
00101
1
× 2.5
00111
1
× 3.5
01001
1
× 4.5
01011
1
× 5.5
01101
1
× 6.5
01111
1
× 7.5
10001
1
× 8.5
10011
1
× 9.5
10101
1
× 10.5
10111
1
× 11.5
11001
1
× 12.5
11011
1
× 13.5
11101
1
× 14.5
Notes
1. Reserved modes are not listed.
The RCWL[CEVCOD] denotes the QE PLL VCO internal frequency as shown in Table 73.
Table 73. QE PLL VCO Divider
RCWL[CEVCOD]
VCO Divider
00
4
01
8
10
2
11
Reserved
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NOTE
The VCO divider (RCWL[CEVCOD]) must be set properly so that the QE
VCO frequency is in the range of 600–1400 MHz. The QE frequency is not
restricted by the CSB and core frequencies. The CSB, core, and QE
frequencies should be selected according to the performance requirements.
The QE VCO frequency is derived from the following equations:
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)
22.4
Suggested PLL Configurations
To simplify the PLL configurations, the device might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock
domains are independent, and each of their PLLs are configured separately. Both of the domains has one
common input clock. Table 74 shows suggested PLL configurations for 33 MHz and 66 MHz input clocks
and illustrates each of the clock domains separately. Any combination of clock domains setting with same
input clock are valid. Refer to Section 22, “Clocking,” for the appropriate operating frequencies for your
device.
Table 74. Suggested PLL Configurations
Conf
No. 1
SPMF
CORE
PLL
CEPMF
CEPDF
Input
CSB Freq Core Freq
Clock Freq
(MHz)
(MHz)
(MHz)
QUICC
Engine
Freq (MHz)
400
533
667
(MHz) (MHz) (MHz)
33 MHz CLKIN / PCI_SYNC_IN Options
s1
0100
0000100
æ
æ
33
133
266
∞
∞
∞
s2
0100
0000101
æ
æ
33
133
333
∞
∞
∞
s3
0101
0000100
æ
æ
33
166
333
∞
∞
∞
s4
0101
0000101
æ
æ
33
166
416
∞
∞
s5
0110
0000100
æ
æ
33
200
400
∞
∞
s6
0110
0000110
æ
æ
33
200
600
s7
0111
0000011
æ
æ
33
233
350
s8
0111
0000100
æ
æ
33
233
466
s9
0111
0000101
æ
æ
33
233
583
s10
1000
0000011
æ
æ
33
266
400
s11
1000
0000100
æ
æ
33
266
533
s12
1000
0000101
æ
æ
33
266
667
s13
1001
0000010
æ
æ
33
300
300
s14
1001
0000011
æ
æ
33
300
450
s15
1001
0000100
æ
æ
33
300
600
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
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Clocking
Table 74. Suggested PLL Configurations (continued)
Input
CSB Freq Core Freq
Clock Freq
(MHz)
(MHz)
(MHz)
QUICC
Engine
Freq (MHz)
400
533
667
(MHz) (MHz) (MHz)
Conf
No. 1
SPMF
CORE
PLL
CEPMF
CEPDF
s16
1010
0000010
æ
æ
33
333
333
s17
1010
0000011
æ
æ
33
333
500
s18
1010
0000100
æ
æ
33
333
667
c1
æ
æ
01001
0
33
300
∞
∞
∞
c2
æ
æ
01100
0
33
400
∞
∞
∞
c3
æ
æ
01110
0
33
466
∞
∞
c4
æ
æ
01111
0
33
500
∞
∞
c5
æ
æ
10000
0
33
533
∞
∞
c6
æ
æ
10001
0
33
566
∞
∞
∞
∞
∞
∞
∞
66 MHz CLKIN / PCI_SYNC_IN Options
∞
∞
∞
∞
∞
s1h
0011
0000110
æ
æ
66
200
400
s2h
0011
0000101
æ
æ
66
200
500
s3h
0011
0000110
æ
æ
66
200
600
s4h
0100
0000011
æ
æ
66
266
400
s5h
0100
0000100
æ
æ
66
266
533
s6h
0100
0000101
æ
æ
66
266
667
s7h
0101
0000010
æ
æ
66
333
333
s8h
0101
0000011
æ
æ
66
333
500
s9h
0101
0000100
æ
æ
66
333
667
c1h
æ
æ
00101
0
66
333
∞
∞
∞
c2h
æ
æ
00110
0
66
400
∞
∞
∞
c3h
æ
æ
00111
0
66
466
∞
∞
c4h
æ
æ
01000
0
66
533
∞
∞
c5h
æ
æ
01001
0
66
600
1
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
The Conf No. consist of prefix, an index and a postfix. The prefix ‘s’ and ‘c’ stands for ‘syset’ and ‘ce’ respectively. the postfix
‘h’ stands for ‘high input clock.’ The index is a serial number.
The following steps describe how to use Table 74. See the example that follows:
1. Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz.
2. Select a suitable CSB and core clock rates from Table 74. Copy the SPMF and CORE PLL
configuration bits.
3. Select a suitable QUICC Engine clock rate from Table 74. Copy the CEPMF and CEPDF
configuration bits.
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4. Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields respectively.
Example:
•
To configure the device with CSB clock rate of 266 MHz, core rate of 400 MHz, and QUICC
SPMF
CORE
PLL
1000
0000011
CEPMF CEPDF
01001
Input Clock
(MHz)
CSB Freq
(MHz)
Core Freq
(MHz)
QUICC
Engine
Freq (MHz)
400
(MHz)
33
266
400
300
∞
0
Engine clock rate 300 MHz while the input clock rate is 33 MHz. Conf No. “s10” and “c1” are
selected from Table 74. SPMF is “1000,” CORPLL is “0000011,” CEPMF is “01001,” and CEPDF
is “0.”
23 Thermal
This section describes the thermal specifications of the MPC8358E.
23.1
Thermal Characteristics
Table 75 provides the package thermal characteristics for the 668 29 mm x 29 mm PBGA package.
Table 75. Package Thermal Characteristics for the PBGA Package
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient Natural Convection on single layer board (1s)
RθJA
20
°C/W
1, 2
Junction-to-ambient Natural Convection on four layer board (2s2p)
RθJA
14
°C/W
1, 2, 3
Junction-to-ambient (@1 m/s) on single layer board (1s)
RθJMA
15
°C/W
1, 3
Junction-to-ambient (@ 1 m/s) on four layer board (2s2p)
RθJMA
11
°C/W
1, 3
Junction-to-board thermal
RθJB
6
°C/W
4
Junction-to-case thermal
RθJC
4
°C/W
5
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Thermal
Table 75. Package Thermal Characteristics for the PBGA Package (continued)
Characteristic
Junction-to-Package Natural Convection on Top
Symbol
Value
Unit
Notes
ψ JT
4
°C/W
6
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 and JEDEC JESD51-9 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal. 1 m/sec is approximately equal to 200 linear feet per minute (LFM).
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
23.2
Thermal Management Information
For the following sections, PD = (VDD X IDD) + PI/O where PI/O is the power dissipation of the I/O drivers.
See Table 5 for typical power dissipations values.
23.2.1
Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJA × PD)
where:
TJ = junction temperature (°C)
TA = ambient temperature for the package (°C)
RθJA = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. As a general statement, the value obtained on a single layer board is
appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
Test cases have demonstrated that errors of a factor of two (in the quantity TJ - TA) are possible.
23.2.2
Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
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many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package will be approximately the same as the local air temperature near the device.
Specifying the local ambient conditions explicitly as the board temperature provides a more precise
description of the local ambient conditions that determine the temperature of the device. At a known board
temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RθJB × PD)
where:
TJ = junction temperature (°C)
TB = board temperature at the package perimeter (°C)
RθJA = junction to board thermal resistance (°C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
23.2.3
Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the
Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
TJ = junction temperature (°C)
TT = thermocouple temperature on top of package (°C)
ΨJT = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
23.2.4
Heat Sinks and Junction-to-Case Thermal Resistance
In some application environments, a heat sink will be required to provide the necessary thermal
management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:
RθJA = RθJC + RθCA
where:
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Thermal
RθJA = junction to ambient thermal resistance (°C/W)
RθJC = junction to case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to
change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been
simulated with a few commercially available heat sinks. The heat sink choice is determined by the
application environment (temperature, air flow, adjacent component power dissipation) and the physical
space available. Because there is not a standard application environment, a standard heat sink is not
required.
Table 76 shows heat sinks and junction-to-case thermal resistance for PBGA package.
Table 76. Heat Sinks and Junction-to-Case Thermal Resistance of PBGA Package
29 × 29 mm PBGA
Heat Sink Assuming Thermal Grease
Air Flow
Thermal Resistance
AAVID 30
× 30 × 9.4 mm Pin Fin
Natural Convection
12.6
AAVID 30
× 30 × 9.4 mm Pin Fin
1 m/s
8.2
AAVID 30
× 30 × 9.4 mm Pin Fin
2 m/s
7.0
AAVID 31 × 35 × 23 mm Pin Fin
Natural Convection
10.5
AAVID 31 × 35 × 23 mm Pin Fin
1 m/s
6.6
AAVID 31 × 35 × 23 mm Pin Fin
2 m/s
6.1
Wakefield, 53 × 53
× 25 mm Pin Fin
Natural Convection
9.0
Wakefield, 53 × 53
× 25 mm Pin Fin
1 m/s
5.6
Wakefield, 53 × 53
× 25 mm Pin Fin
2 m/s
5.1
MEI, 75 × 85 × 12 no adjacent board, extrusion
Natural Convection
9.0
MEI, 75 × 85 × 12 no adjacent board, extrusion
1 m/s
5.7
MEI, 75 × 85 × 12 no adjacent board, extrusion
2 m/s
5.1
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling and the convection cooling of the
air moving through the application. Simplified thermal models of the packages can be assembled using the
junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More
detailed thermal models can be made available on request.
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Thermal
Heat sink vendors include the following:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
603-224-9988
408-749-7601
International Electronic Research Corporation (IERC)
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
818-842-7277
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
Internet: www.mei-millennium.com
408-436-8770
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
800-522-6752
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
603-635-5102
Interface material vendors include the following:
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
781-935-4850
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dowcorning.com
800-248-2481
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
888-642-7674
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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System Design Information
The Bergquist Company
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
23.3
800-347-4572
Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use
thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the
board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would
lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint
lifetime of the package. Recommended maximum force on the top of the package is 10 lb force (4.5 kg
force). If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or
plastic surfaces and its performance verified under the application requirements.
23.3.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction to case
thermal resistance.
TJ = TC + (RθJC × PD)
where:
TJ = junction temperature (°C)
TC = case temperature of the package (°C)
RθJC = junction to case thermal resistance (°C/W)
PD = power dissipation (W)
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8358E. Additional information can be found in AN3097, MPC8360E/MPC8358E PowerQUICC™
Design Checklist, Rev. 1.
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System Design Information
24.1
System Clocking
The device includes two PLLs.
1. The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN
input. The frequency ratio between the platform and CLKIN is selected using the platform PLL
ratio configuration bits as described in Section 22.1, “System PLL Configuration.”
2. The e300 core PLL (AVDD2) generates the core clock as a slave to the platform clock. The
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section 22.2, “Core PLL Configuration.”
24.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
AVDD2 respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages
will be derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 53, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
Figure 53 shows the PLL power supply filter circuit.
10 Ω
AVDDn
V DD
2.2 µF
2.2 µF
GND
Low ESL Surface Mount Capacitors
Figure 53. PLL Power Supply Filter Circuit
24.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These
decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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91
System Design Information
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
24.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of
the device.
24.5
Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 54). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
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System Design Information
OV DD
RN
SW2
Pad
Data
SW1
RP
OGND
Figure 54. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured
while driving logic 1 with an external precision differential termination resistor of value Rterm. The
measured voltage is V2 = 1/(1/R1 + 1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm
× (V1/V2 – 1). The drive current is then Isource = V1/Rsource.
Table 77 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal OVDD, 105°C.
Table 77. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI
DDR DRAM
Symbol
Unit
RN
42 Target
25 Target
20 Target
Z0
W
RP
42 Target
25 Target
20 Target
Z0
W
Differential
NA
NA
NA
ZDIFF
W
Note: Nominal supply voltages. See Table 1, TJ = 105°C.
24.6
Configuration Pin Muxing
The device provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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93
Document Revision History
and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these
pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize
the disruption of signal quality or speed for output pins thus configured.
24.7
Pull-Up Resistor Requirements
The device requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
including I2C pins, Ethernet Management MDIO pin, and EPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interface,
see AN3097, MPC8360E/MPC8358E PowerQUICC™ Design Checklist, Rev. 1.
25 Document Revision History
Table 78 provides a revision history for this hardware specification.
Table 78. Document Revision History
Rev.
Number
Date
1
12/07/2007
Substantive Change(s)
Initial release.
26 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 26.1, “Part Numbers Fully Addressed by this Document.”
26.1
Part Numbers Fully Addressed by this Document
Table 79 provides the Freescale part numbering nomenclature for the MPC8358E. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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Ordering Information
Table 79. Part Numbering Nomenclature 1
MPC nnnn
e
t
Product
Part
Encryption Temperature
Code Identifier Acceleration
Range
MPC
8358
Blank = Not
included
E = included
0°C TA to
105°C TJ
pp
aa
a
a
A
Package 2
Processor
Frequency 3
Platform
Frequency
QUICC
Engine
Frequency
Die
Revision
ZQ = PBGA
VR = PBGA
(no lead)
D = 266 MHz D = 266 MHz
e300 core
speed
AD = 266 MHz
AG = 400 MHz
A=revision
2.1 silicon
1
Not all processor, platform, and QUICC Engine frequency combinations are supported. For available frequency combinations,
contact your local Freescale Sales Office or authorized distributor.
2 See Section 21, “Package and Pin Listings,” for more information on available package types.
3
Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification
support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core
frequencies.
Table 80 shows the SVR settings by device and package type.
Table 80. SVR Settings
Package
SVR
(Rev 2.1)
MPC8358E
PBGA
0x804E_0021
MPC8358
PBGA
0x804F_0021
Device
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
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95
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Document Number: MPC8358EEC
Rev. 1
12/2007
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